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1. 发明申请

US20060172490A1 Method of improving flash memory performance 有权
公开(公告)号：US20060172490A1
公开(公告)日：2006-08-03
申请号：US11049230
申请日：2005-02-02
申请人： Pei-Ren Jeng , Hsuan-Ling Kao
发明人： Pei-Ren Jeng , Hsuan-Ling Kao
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , H01L29/66825
摘要： A method of improving flash memory performance. The method includes: providing a substrate having a gate structure thereon, the gate structure having a gate dielectric layer, a first polysilicon layer, an interploy dielectric layer, and a second polysilicon layer; then, depositing an gate insulating layer to enclose the gate structure, for forming side wall spacers; next, performing a first anneal on the substrate and the enclosed gate structure; then, performing a cell reoxidation on the substrate and the enclosed gate structure by dilute oxidation process using mixed gas comprising oxygen O2 and nitrogen N2. The invention reduces encroachment issues in the interpoly dielectric layer and the tunnel oxide and improves gate coupling ratio (GCR).

2. 发明授权

US07151042B2 Method of improving flash memory performance 有权
标题翻译：提高闪存性能的方法
公开(公告)号：US07151042B2
公开(公告)日：2006-12-19
申请号：US11049230
申请日：2005-02-02
申请人： Pei-Ren Jeng , Hsuan-Ling Kao
发明人： Pei-Ren Jeng , Hsuan-Ling Kao
IPC分类号： H01L21/76
CPC分类号： H01L21/28273 , H01L29/66825
摘要： A method of improving flash memory performance. The method includes: providing a substrate having a gate structure thereon, the gate structure having a gate dielectric layer, a first polysilicon layer, an interploy dielectric layer, and a second polysilicon layer; then, depositing an gate insulating layer to enclose the gate structure, for forming side wall spacers; next, performing a first anneal on the substrate and the enclosed gate structure; then, performing a cell reoxidation on the substrate and the enclosed gate structure by dilute oxidation process using mixed gas comprising oxygen O2 and nitrogen N2. The invention reduces encroachment issues in the interpoly dielectric layer and the tunnel oxide and improves gate coupling ratio (GCR).
摘要翻译：一种提高闪存性能的方法。该方法包括：提供其上具有栅极结构的衬底，栅极结构具有栅极电介质层，第一多晶硅层，工作介电层和第二多晶硅层; 然后，沉积栅极绝缘层以封闭栅极结构，用于形成侧壁间隔物; 接下来，在衬底和封闭的栅极结构上进行第一退火; 然后，通过使用包含氧O 2和氮气N 2的混合气体的稀释氧化方法在衬底和封闭的栅极结构上进行电池再氧化。本发明减少了interoly介电层和隧道氧化物中的侵蚀问题，并提高了栅极耦合比（GCR）。

3. 发明申请

US20050040467A1 Structure of nonvolatile memory array 有权
标题翻译：非易失性存储器阵列的结构
公开(公告)号：US20050040467A1
公开(公告)日：2005-02-24
申请号：US10644902
申请日：2003-08-21
申请人： Cheng-Ming Yih , Huei-Huarng Chen , Hsuan-Ling Kao
发明人： Cheng-Ming Yih , Huei-Huarng Chen , Hsuan-Ling Kao
IPC分类号： H01L21/8247 , H01L27/108 , H01L27/115
CPC分类号： H01L27/11521 , H01L27/115
摘要： A structure of a nonvolatile memory array with low source line sheet resistance is disclosed in this present invention. The key aspect of this present invention is employing a buried conductive region as the source line of a nonvolatile memory array. The topology of the above-mentioned buried conductive region is different from the source line in the prior art. Therefore, this invention can provide a nonvolatile memory array for reducing the source line sheet resistance and achieving the reliability and the operating performance of the nonvolatile memory array.
摘要翻译：在本发明中公开了具有低源极线电阻的非易失性存储器阵列的结构。本发明的关键方面是采用埋入导电区域作为非易失性存储器阵列的源极线。上述掩埋导电区域的拓扑与现有技术中的源极线不同。因此，本发明可以提供一种用于减少源极线电阻并实现非易失性存储器阵列的可靠性和操作性能的非易失性存储器阵列。

4. 发明授权

US06821841B1 Method for fabricating a mask read-only-memory with diode cells 有权
标题翻译：用二极管电池制造掩膜只读存储器的方法
公开(公告)号：US06821841B1
公开(公告)日：2004-11-23
申请号：US10643964
申请日：2003-08-20
申请人： Chun-Pei Wu , Huei-Huarng Chen , Wen-Bin Tsai , Hsuan-Ling Kao
发明人： Chun-Pei Wu , Huei-Huarng Chen , Wen-Bin Tsai , Hsuan-Ling Kao
IPC分类号： H01L218242
CPC分类号： H01L27/112 , H01L27/11253 , H01L27/1126
摘要： A method for fabricating a mask read-only-memory with diode cells is provided. A doped conductive layer with a first conductivity is formed on bit lines. Then, a photoresist layer with a mask ROM pattern is formed on an interlayer dielectric layer on the doped conductive layer for serving as an etching mask, thereby forming openings in the interlayer dielectric layer unto the exposed regions of the doped conductive layer. Performing ion implantation to form a diffusion region with a second conductivity opposite to the first conductivity in each exposed region of the doped conductive layer, so that the doped conductive layer and the diffusion regions formed therein constitute diode cells that are served as memory cells. A contact plug is formed in each opening unto the diode cell and a conductive layer is formed on the contact plug for serving as word lines.
摘要翻译：提供了一种制造具有二极管单元的掩模只读存储器的方法。在位线上形成具有第一导电性的掺杂导电层。然后，在用作蚀刻掩模的掺杂导电层上的层间电介质层上形成具有掩模ROM图案的光致抗蚀剂层，从而在层间电介质层中向掺杂导电层的暴露区域形成开口。进行离子注入以形成具有与掺杂导电层的每个暴露区域中的第一导电性相反的第二导电性的扩散区域，使得在其中形成的掺杂导电层和扩散区域构成用作存储单元的二极管单元。在二极管单元的每个开口中形成接触塞，并且在接触插塞上形成用作字线的导电层。

5. 发明授权

US07244661B2 Method for forming a buried diffusion layer with reducing topography in a surface of a semiconductor substrate 有权
标题翻译：用于在半导体衬底的表面中形成具有减小的形貌的掩埋扩散层的方法
公开(公告)号：US07244661B2
公开(公告)日：2007-07-17
申请号：US11032045
申请日：2005-01-11
申请人： Cheng-Ming Yih , Huei-Huarng Chen , Hsuan-Ling Kao
发明人： Cheng-Ming Yih , Huei-Huarng Chen , Hsuan-Ling Kao
IPC分类号： H01L21/76
CPC分类号： H01L27/115 , H01L27/11521
摘要： A method for forming a buried diffusion layer with reducing topography in a surface of a semiconductor substrate is provided. A patterned first dielectric layer is formed on a semiconductor substrate for being used as a first hard mask. A thermal oxidation process is performed to form field oxides on the exposed potions of the semiconductor substrate. The patterned first dielectric layer is then removed. A second patterned dielectric layer is formed on the field oxides and the semiconductor substrate for being used as a second hard mask. An isotropic etching process is performed to etch the exposed portions of the field oxides and the semiconductor substrate. The patterned second dielectric layer and the underlying field oxides are removed to form a plurality of trenches on the surface of the semiconductor substrate. A buried diffusion layer is formed along surroundings of the trenches in the semiconductor substrate.
摘要翻译：提供一种在半导体衬底的表面中形成具有减小的形貌的掩埋扩散层的方法。图案化的第一介电层形成在半导体衬底上用作第一硬掩模。进行热氧化处理以在半导体衬底的暴露的部分上形成场氧化物。然后去除图案化的第一介电层。在场氧化物和半导体衬底上形成用作第二硬掩模的第二图案化电介质层。执行各向同性蚀刻工艺以蚀刻场氧化物和半导体衬底的暴露部分。图案化的第二介电层和下面的场氧化物被去除以在半导体衬底的表面上形成多个沟槽。沿着半导体衬底中的沟槽的周围形成掩埋扩散层。

6. 发明授权

US07005696B2 Structure of nonvolatile memory array 有权
标题翻译：非易失性存储器阵列的结构
公开(公告)号：US07005696B2
公开(公告)日：2006-02-28
申请号：US10644902
申请日：2003-08-21
申请人： Cheng-Ming Yih , Huei-Huarng Chen , Hsuan-Ling Kao
发明人： Cheng-Ming Yih , Huei-Huarng Chen , Hsuan-Ling Kao
IPC分类号： H01L29/76
CPC分类号： H01L27/11521 , H01L27/115
摘要： A structure of a nonvolatile memory array with low source line sheet resistance is disclosed in this present invention. The key aspect of this present invention is employing a buried conductive region as the source line of a nonvolatile memory array. The topology of the above-mentioned buried conductive region is different from the source line in the prior art. Therefore, this invention can provide a nonvolatile memory array for reducing the source line sheet resistance and achieving the reliability and the operating performance of the nonvolatile memory array.
摘要翻译：在本发明中公开了具有低源极线电阻的非易失性存储器阵列的结构。本发明的关键方面是采用埋入导电区域作为非易失性存储器阵列的源极线。上述掩埋导电区域的拓扑与现有技术中的源极线不同。因此，本发明可以提供一种用于减少源极线电阻并实现非易失性存储器阵列的可靠性和操作性能的非易失性存储器阵列。

7. 发明申请

US20060154441A1 Method for forming a buried diffusion layer with reducing topography in a surface of a semiconductor substrate 有权
标题翻译：用于在半导体衬底的表面中形成具有减小的形貌的掩埋扩散层的方法
公开(公告)号：US20060154441A1
公开(公告)日：2006-07-13
申请号：US11032045
申请日：2005-01-11
申请人： Cheng-Ming Yih , Huei-Huarng Chen , Hsuan-Ling Kao
发明人： Cheng-Ming Yih , Huei-Huarng Chen , Hsuan-Ling Kao
IPC分类号： H01L21/76
CPC分类号： H01L27/115 , H01L27/11521
摘要： A method for forming a buried diffusion layer with reducing topography in a surface of a semiconductor substrate is provided. A patterned first dielectric layer is formed on a semiconductor substrate for being used as a first hard mask. A thermal oxidation process is performed to form field oxides on the exposed potions of the semiconductor substrate. The patterned first dielectric layer is then removed. A second patterned dielectric layer is formed on the field oxides and the semiconductor substrate for being used as a second hard mask. An isotropic etching process is performed to etch the exposed portions of the field oxides and the semiconductor substrate. The patterned second dielectric layer and the underlying field oxides are removed to form a plurality of trenches on the surface of the semiconductor substrate. A buried diffusion layer is formed along surroundings of the trenches in the semiconductor substrate.
摘要翻译：提供一种在半导体衬底的表面中形成具有减小的形貌的掩埋扩散层的方法。图案化的第一介电层形成在半导体衬底上用作第一硬掩模。进行热氧化处理以在半导体衬底的暴露的部分上形成场氧化物。然后去除图案化的第一介电层。在场氧化物和半导体衬底上形成用作第二硬掩模的第二图案化电介质层。执行各向同性蚀刻工艺以蚀刻场氧化物和半导体衬底的暴露部分。图案化的第二介电层和下面的场氧化物被去除以在半导体衬底的表面上形成多个沟槽。沿着半导体衬底中的沟槽的周围形成掩埋扩散层。

8. 发明授权

US06979620B1 Method for fabricating a flash memory cell 有权
标题翻译：闪存单元的制造方法
公开(公告)号：US06979620B1
公开(公告)日：2005-12-27
申请号：US11126301
申请日：2005-05-11
申请人： Chun-Pei Wu , Huei-Huarng Chen , Hong-Chi Chen , Hsuan-Ling Kao
发明人： Chun-Pei Wu , Huei-Huarng Chen , Hong-Chi Chen , Hsuan-Ling Kao
IPC分类号： H01L21/28 , H01L21/8247 , H01L27/105
CPC分类号： H01L21/28273 , H01L27/105 , H01L27/11526 , H01L27/11531
摘要： A method for fabricating a flash memory cell is provided. After an ONO dielectric layer is formed on a first conductive layer over a tunnel oxide layer, a second conductive layer is formed on the ONO dielectric layer. Then, patterning the second conductive layer to form a periphery region comprising an exposed portion of a semiconductor substrate and a memory cell region comprising the left second conductive layer. During the present process, the ONO dielectric layer is protected from being exposed in various solvents and gases with the second conductive layer. Thus, a flash memory cell with a high-quality ONO gate dielectric layer, without increasing complexity of the process and additional masks, is obtained.
摘要翻译：提供一种制造闪存单元的方法。在隧道氧化物层上的第一导电层上形成ONO电介质层之后，在ONO电介质层上形成第二导电层。然后，图案化第二导电层以形成包括半导体衬底的暴露部分和包括左第二导电层的存储单元区域的外围区域。在本工艺过程中，ONO介电层被保护不被暴露在各种溶剂和气体中与第二导电层。因此，获得具有高质量ONO栅介质层的闪存单元，而不增加工艺的复杂性和附加掩模。

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