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21. 发明授权

US08053323B1 Patterning methodology for uniformity control 有权
标题翻译：均匀性控制的图案化方法
公开(公告)号：US08053323B1
公开(公告)日：2011-11-08
申请号：US12938571
申请日：2010-11-03
申请人： Yu Chao Lin , Ming-Ching Chang , Yih-Ann Lin , Ryan Chia-Jen Chen , Chao-Cheng Chen
发明人： Yu Chao Lin , Ming-Ching Chang , Yih-Ann Lin , Ryan Chia-Jen Chen , Chao-Cheng Chen
IPC分类号： H01L21/336
CPC分类号： H01L21/32139 , H01L21/0276 , H01L21/28194 , H01L21/31122 , H01L21/31138 , H01L21/823437 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patternable layer over a substrate. The method includes forming a first layer over the patternable layer. The method includes forming a second layer over the first layer. The second layer is substantially thinner than the first layer. The method includes patterning the second layer with a photoresist material through a first etching process to form a patterned second layer. The method includes patterning the first layer with the patterned second layer through a second etching process to form a patterned first layer. The first and second layers have substantially different etching rates during the second etching process. The method includes patterning the patternable layer with the patterned first layer through a third etching process.
摘要翻译：本公开提供了制造半导体器件的方法。该方法包括在衬底上形成可图案化层。该方法包括在可图案层上形成第一层。该方法包括在第一层上形成第二层。第二层比第一层薄得多。该方法包括通过第一蚀刻工艺用光致抗蚀剂材料图案化第二层以形成图案化的第二层。该方法包括通过第二蚀刻工艺将具有图案化的第二层的第一层图案化以形成图案化的第一层。第一和第二层在第二蚀刻工艺期间具有显着不同的蚀刻速率。该方法包括通过第三蚀刻工艺对具有图案化的第一层的图案化层进行图案化。

22. 发明授权

US06794302B1 Dynamic feed forward temperature control to achieve CD etching uniformity 失效
标题翻译：动态前馈温度控制实现CD蚀刻均匀性
公开(公告)号：US06794302B1
公开(公告)日：2004-09-21
申请号：US10393909
申请日：2003-03-20
申请人： Li-Shiun Chen , Ming-Ching Chang , Huan-Just Lin , Li-Te S. Lin , Yung-Hog Chiu , Hun-Jan Tao
发明人： Li-Shiun Chen , Ming-Ching Chang , Huan-Just Lin , Li-Te S. Lin , Yung-Hog Chiu , Hun-Jan Tao
IPC分类号： H01L21302
CPC分类号： H01J37/32935 , H01L21/32135 , H01L21/32137
摘要： A method for compensating CD variations across a semiconductor process wafer surface in a plasma etching process including a semiconductor wafer having a process surface comprising patterned features; carrying out a first plasma etching process wherein the semiconductor wafer is heated to at least two selectively controllable temperature zones; determining a first dimensional variation of etched features with respect to reference dimensions over predetermined areas of the process surface including the two selectively controllable temperature zones; determining operating temperatures for the two selectively controllable temperature zones to achieve a targeted dimensional variation change in the first dimensional variation to achieve a desired second dimensional variation; plasma etching the process surface to the desired operating temperatures; and, determining an actual dimensional variation change for use in at least one subsequent plasma etching process.
摘要翻译：一种用于在包括具有包括图案特征的工艺表面的半导体晶片的等离子体蚀刻工艺中补偿半导体工艺晶片表面上的CD变化的方法; 执行第一等离子体蚀刻工艺，其中半导体晶片被加热到至少两个可选择性控制的温度区域; 确定相对于包括所述两个可选择性控制的温度区域的所述工艺表面的预定区域上的参考尺寸的蚀刻特征的第一尺寸变化; 确定所述两个可选择性控制的温度区域的操作温度，以实现所述第一尺寸变化中的目标尺寸变化变化以实现期望的第二维度变化; 将工艺表面等离子体蚀刻到所需的工作温度; 以及确定用于至少一个随后等离子体蚀刻工艺中的实际尺寸变化变化。

23. 发明授权

US09991375B2 Metal gate electrode of a semiconductor device 有权
公开(公告)号：US09991375B2
公开(公告)日：2018-06-05
申请号：US13484047
申请日：2012-05-30
申请人： Jr-Jung Lin , Chih-Han Lin , Jin-Aun Ng , Ming-Ching Chang , Chao-Cheng Chen
发明人： Jr-Jung Lin , Chih-Han Lin , Jin-Aun Ng , Ming-Ching Chang , Chao-Cheng Chen
IPC分类号： H01L29/78 , H01L21/283 , H01L29/49 , H01L29/66 , H01L21/8238
CPC分类号： H01L29/78 , H01L21/283 , H01L21/823842 , H01L29/4966 , H01L29/4983 , H01L29/66545
摘要： The invention relates to integrated circuit fabrication, and more particularly to a metal gate electrode. An exemplary structure for a semiconductor device comprises a substrate comprising a major surface; a first rectangular gate electrode on the major surface comprising a first layer of multi-layer material; a first dielectric material adjacent to one side of the first rectangular gate electrode; and a second dielectric material adjacent to the other 3 sides of the first rectangular gate electrode, wherein the first dielectric material and the second dielectric material collectively surround the first rectangular gate electrode.

24. 发明授权

US09153440B2 Method of forming a semiconductor device 有权
标题翻译：形成半导体器件的方法
公开(公告)号：US09153440B2
公开(公告)日：2015-10-06
申请号：US13428923
申请日：2012-03-23
申请人： Chih-Han Lin , Ming-Ching Chang , Ryan Chia-Jen Chen , Yih-Ann Lin , Jr-Jung Lin
发明人： Chih-Han Lin , Ming-Ching Chang , Ryan Chia-Jen Chen , Yih-Ann Lin , Jr-Jung Lin
IPC分类号： H01L21/308 , H01L21/033 , H01L21/311 , H01L21/768
CPC分类号： H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/31144 , H01L21/76816
摘要： A method includes providing a first mask pattern over a substrate, forming first spacers adjoining sidewalls of the first mask pattern, removing the first mask pattern, forming second spacers adjoining sidewalls of the first spacers, forming a filling layer over the substrate and between the second spacers, and forming a second mask pattern over the substrate.
摘要翻译：一种方法包括在衬底上提供第一掩模图案，形成与第一掩模图案的侧壁相邻的第一间隔物，去除第一掩模图案，形成邻接第一间隔物的侧壁的第二间隔物，在衬底上形成填充层，并且在衬底上形成第二掩模图案。

25. 发明申请

US20130203247A1 METHOD OF FABRICATING A SEMICONDUCTOR STRUCTURE 有权
标题翻译：制造半导体结构的方法
公开(公告)号：US20130203247A1
公开(公告)日：2013-08-08
申请号：US13366669
申请日：2012-02-06
申请人： Tzu-Yen HSIEH , Ming-Ching CHANG , Chia-Wei CHANG , Chao-Cheng CHEN , Chun-Hung LEE , Dai-Lin WU
发明人： Tzu-Yen HSIEH , Ming-Ching CHANG , Chia-Wei CHANG , Chao-Cheng CHEN , Chun-Hung LEE , Dai-Lin WU
IPC分类号： H01L21/20
CPC分类号： H01L21/3215 , H01L21/0338 , H01L21/26506 , H01L21/266 , H01L21/28026 , H01L21/28035 , H01L21/28123 , H01L21/32134 , H01L21/32139
摘要： An embodiment of the current disclosure includes a method of providing a substrate, forming a polysilicon layer over the substrate, forming a first photoresist layer on the polysislicon layer, creating a first pattern on the first photoresistlayer, wherein some portions of the polysilicon layer are covered by the first photoresist layer and some portions of the polysilicon layer are not covered by the first photoresist layer, implanting ions into the portions of the polysilicon layer that are not covered by the first photoresist layer, removing the first photoresist layer from the polysilicon layer, forming a second photoresist layer on the polysilicon layer, creating a second pattern on the second photoresistlayer, and implanting ions into the portions of the polysilicon layer that are not covered by the second photoresist layer, removing the second photoresist layer from the polysilicon layer, and removing portions of the polysilicon layer using an etchant.
摘要翻译：本公开的实施例包括提供衬底的方法，在衬底上形成多晶硅层，在聚苯乙烯层上形成第一光致抗蚀剂层，在第一光致抗蚀剂层上产生第一图案，其中多晶硅层的一些部分被覆盖通过第一光致抗蚀剂层，并且多晶硅层的一些部分未被第一光致抗蚀剂层覆盖，将离子注入未被第一光致抗蚀剂层覆盖的多晶硅层的部分中，从多晶硅层去除第一光致抗蚀剂层，在所述多晶硅层上形成第二光致抗蚀剂层，在所述第二光致抗蚀剂层上形成第二图案，以及将离子注入所述多晶硅层的未被所述第二光致抗蚀剂层覆盖的部分，从所述多晶硅层除去所述第二光致抗蚀剂层，以及使用蚀刻剂去除多晶硅层的部分。

26. 发明申请

US20130187235A1 COMPOSITE DUMMY GATE WITH CONFORMAL POLYSILICON LAYER FOR FINFET DEVICE 有权
标题翻译：用于FINFET器件的具有合成多晶硅层的复合绝缘栅
公开(公告)号：US20130187235A1
公开(公告)日：2013-07-25
申请号：US13353975
申请日：2012-01-19
申请人： Yuan-Sheng Huang , Tzu-Yen Hsieh , Ming-Ching Chang , Chao-Cheng Chen , Chia-Jen Chen
发明人： Yuan-Sheng Huang , Tzu-Yen Hsieh , Ming-Ching Chang , Chao-Cheng Chen , Chia-Jen Chen
IPC分类号： H01L27/092 , H01L21/28
CPC分类号： H01L29/66545 , H01L21/823807 , H01L21/823821 , H01L21/823828 , H01L27/0924 , H01L29/0649 , H01L29/66795 , H01L29/785
摘要： The present disclosure involves a FinFET. The FinFET includes a fin structure formed over a substrate. A gate dielectric layer is least partially wrapped around a segment of the fin structure. The gate dielectric layer contains a high-k gate dielectric material. The FinFET includes a polysilicon layer conformally formed on the gate dielectric layer. The FinFET includes a metal gate electrode layer formed over the polysilicon layer. The present disclosure provides a method of fabricating a FinFET. The method includes providing a fin structure containing a semiconductor material. The method includes forming a gate dielectric layer over the fin structure, the gate dielectric layer being at least partially wrapped around the fin structure. The method includes forming a polysilicon layer over the gate dielectric layer, wherein the polysilicon layer is formed in a conformal manner. The method includes forming a dummy gate layer over the polysilicon layer.
摘要翻译：本公开涉及FinFET。 FinFET包括在衬底上形成的翅片结构。栅介质层最少部分地缠绕在翅片结构的一段上。栅介质层包含高k栅介质材料。 FinFET包括在栅介质层上共形形成的多晶硅层。 FinFET包括在多晶硅层上形成的金属栅极电极层。本公开提供了制造FinFET的方法。该方法包括提供包含半导体材料的翅片结构。该方法包括在鳍结构上方形成栅极电介质层，栅介质层至少部分地围绕翅片结构缠绕。该方法包括在栅介质层上形成多晶硅层，其中多晶硅层以保形方式形成。该方法包括在多晶硅层上形成伪栅极层。

27. 发明申请

US20060154487A1 ETCHING PROCESS TO AVOID POLYSILICON NOTCHING 有权
标题翻译：蚀刻过程避免多晶硅缺口
公开(公告)号：US20060154487A1
公开(公告)日：2006-07-13
申请号：US11033912
申请日：2005-01-11
申请人： Shiang-Bau Wang , Li-Te Lin , Ming-Ching Chang , Ryan Chen , Yuan-Hung Chiu , Hun-Jan Tao
发明人： Shiang-Bau Wang , Li-Te Lin , Ming-Ching Chang , Ryan Chen , Yuan-Hung Chiu , Hun-Jan Tao
IPC分类号： H01L21/8234 , H01L21/302
CPC分类号： H01L21/32137 , H01L21/31116 , H01L21/823828
摘要： A method for plasma assisted etching of a polysilicon containing gate electrode to reduce or avoid polysilicon notching at a base portion including providing a semiconducting substrate; forming a gate dielectric layer on the semiconducting substrate; forming a polysilicon layer on the gate dielectric; patterning a photoresist layer over the polysilicon layer for etching a gate electrode; carrying out a first plasma assisted etch process to etch through a major thickness portion of the polysilicon layer; carrying out a first inert gas plasma treatment; carrying out a second plasma assisted etch process to include exposing portions of the underlying gate dielectric layer; carrying out a second inert gas plasma treatment; and, carrying out a third plasma assisted etch process to fully expose the underlying gate dielectric layer adjacent either side of the gate electrodes.
摘要翻译：一种用于等离子体辅助蚀刻含多晶硅栅电极的方法，以减少或避免在包括提供半导体衬底的基极部分处的多晶硅刻蚀; 在所述半导体衬底上形成栅介电层; 在栅极电介质上形成多晶硅层; 在多晶硅层上形成光致抗蚀剂层以蚀刻栅电极; 执行第一等离子体辅助蚀刻工艺以蚀刻通过多晶硅层的主要厚度部分; 进行第一惰性气体等离子体处理; 执行第二等离子体辅助蚀刻工艺以包括暴露下面的栅介电层的部分; 进行第二次惰性气体等离子体处理; 并且执行第三等离子体辅助蚀刻工艺以完全暴露邻近栅电极的任一侧的底层栅介质层。

28. 发明申请

US20050032386A1 Etching and plasma treatment process to improve a gate profile 有权
标题翻译：蚀刻和等离子体处理工艺，提高浇口型材
公开(公告)号：US20050032386A1
公开(公告)日：2005-02-10
申请号：US10634001
申请日：2003-08-04
申请人： Ming-Ching Chang , Li-Te Lin , Yu-I Wang , Yuan-Hung Chiu , Hui-Jan Tao
发明人： Ming-Ching Chang , Li-Te Lin , Yu-I Wang , Yuan-Hung Chiu , Hui-Jan Tao
IPC分类号： H01L21/302 , H01L21/3213 , H01L21/461 , H01L21/8238
CPC分类号： H01L21/823828 , H01L21/32137
摘要： A method for improving a polysilicon gate electrode profile to avoid preferential RIE etching in a polysilicon gate electrode etching process including carrying out a multi-step etching process wherein at least one of a lower RF source power and RF bias power are reduced to complete a polysilicon etching process and an in-situ plasma treatment with an inert gas plasma is carried out prior to neutralize an electrical charge imbalance prior to carrying out an overetch step.
摘要翻译：一种用于改善多晶硅栅极电极轮廓的方法，以避免在多晶硅栅极电极蚀刻工艺中的优先RIE蚀刻，包括进行多步蚀刻工艺，其中降低RF源功率和RF偏置功率中的至少一个以完成多晶硅蚀刻工艺和惰性气体等离子体的原位等离子体处理在进行过蚀刻步骤之前中和电荷不平衡之前进行。

29. 发明授权

US06794313B1 Oxidation process to improve polysilicon sidewall roughness 有权
标题翻译：氧化工艺提高多晶硅侧壁粗糙度
公开(公告)号：US06794313B1
公开(公告)日：2004-09-21
申请号：US10251327
申请日：2002-09-20
申请人： Ming-Ching Chang
发明人： Ming-Ching Chang
IPC分类号： H01L2131
CPC分类号： H01L21/28247 , H01L21/28035 , H01L21/32137
摘要： A new step is provided for the creation of polysilicon gate electrode structures. A layer of polysilicon is deposited over the surface of a layer of semiconductor material, the layer of polysilicon is etched using a layer of hardmask material for this purpose. The etch of the layer of polysilicon is performed using a dual power source plasma system. During the etching of the layer of polysilicon, a step of inert oxidation is inserted. This step forms a layer of passivation over the sidewalls of the etched layer of polysilicon. The step of inert oxidation is an oxygen-based plasma exposure.
摘要翻译：提供了创建多晶硅栅电极结构的新步骤。在半导体材料层的表面上沉积多晶硅层，为此目的，使用一层硬掩模材料蚀刻多晶硅层。使用双电源等离子体系统来执行多晶硅层的蚀刻。在蚀刻多晶硅层期间，插入惰性氧化步骤。该步骤在蚀刻多晶硅层的侧壁上形成钝化层。惰性氧化的步骤是氧基等离子体暴露。

30. 发明授权

US09111861B2 Method of fabricating a semiconductor structure with ion-implanted conductive layer 有权
标题翻译：用离子注入导电层制造半导体结构的方法
公开(公告)号：US09111861B2
公开(公告)日：2015-08-18
申请号：US13366669
申请日：2012-02-06
申请人： Tzu-Yen Hsieh , Ming-Ching Chang , Chia-Wei Chang , Chao-Cheng Chen , Chun-Hung Lee , Dai-Lin Wu
发明人： Tzu-Yen Hsieh , Ming-Ching Chang , Chia-Wei Chang , Chao-Cheng Chen , Chun-Hung Lee , Dai-Lin Wu
IPC分类号： H01L21/266 , H01L21/28 , H01L21/033 , H01L21/3213 , H01L21/265
CPC分类号： H01L21/3215 , H01L21/0338 , H01L21/26506 , H01L21/266 , H01L21/28026 , H01L21/28035 , H01L21/28123 , H01L21/32134 , H01L21/32139
摘要： An embodiment of the current disclosure includes a method of providing a substrate, forming a polysilicon layer over the substrate, forming a first photoresist layer on the polysislicon layer, creating a first pattern on the first photoresist layer, wherein some portions of the polysilicon layer are covered by the first photoresist layer and some portions of the polysilicon layer are not covered by the first photoresist layer, implanting ions into the portions of the polysilicon layer that are not covered by the first photoresist layer, removing the first photoresist layer from the polysilicon layer, forming a second photoresist layer on the polysilicon layer, creating a second pattern on the second photoresist layer, and implanting ions into the portions of the polysilicon layer that are not covered by the second photoresist layer, removing the second photoresist layer from the polysilicon layer, and removing portions of the polysilicon layer using an etchant.
摘要翻译：本公开的实施例包括提供衬底的方法，在衬底上形成多晶硅层，在聚苯乙烯层上形成第一光致抗蚀剂层，在第一光致抗蚀剂层上形成第一图案，其中多晶硅层的一些部分由第一光致抗蚀剂层覆盖，并且多晶硅层的一些部分不被第一光致抗蚀剂层覆盖，将离子注入到未被第一光致抗蚀剂层覆盖的多晶硅层的部分中，从多晶硅层去除第一光致抗蚀剂层在所述多晶硅层上形成第二光致抗蚀剂层，在所述第二光致抗蚀剂层上产生第二图案，以及将离子注入所述多晶硅层的未被所述第二光致抗蚀剂层覆盖的部分，从所述多晶硅层除去所述第二光致抗蚀剂层并且使用蚀刻剂去除多晶硅层的部分。

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