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1. 发明授权

US09287179B2 Composite dummy gate with conformal polysilicon layer for FinFET device 有权
标题翻译：用于FinFET器件的具有适形多晶硅层的复合伪栅极
公开(公告)号：US09287179B2
公开(公告)日：2016-03-15
申请号：US13353975
申请日：2012-01-19
申请人： Yuan-Sheng Huang , Tzu-Yen Hsieh , Ming-Ching Chang , Chao-Cheng Chen , Chia-Jen Chen
发明人： Yuan-Sheng Huang , Tzu-Yen Hsieh , Ming-Ching Chang , Chao-Cheng Chen , Chia-Jen Chen
IPC分类号： H01L29/78 , H01L21/8238 , H01L29/66 , H01L27/092
CPC分类号： H01L29/66545 , H01L21/823807 , H01L21/823821 , H01L21/823828 , H01L27/0924 , H01L29/0649 , H01L29/66795 , H01L29/785
摘要： The present disclosure involves a FinFET. The FinFET includes a fin structure formed over a substrate. A gate dielectric layer is least partially wrapped around a segment of the fin structure. The gate dielectric layer contains a high-k gate dielectric material. The FinFET includes a polysilicon layer conformally formed on the gate dielectric layer. The FinFET includes a metal gate electrode layer formed over the polysilicon layer. The present disclosure provides a method of fabricating a FinFET. The method includes providing a fin structure containing a semiconductor material. The method includes forming a gate dielectric layer over the fin structure, the gate dielectric layer being at least partially wrapped around the fin structure. The method includes forming a polysilicon layer over the gate dielectric layer, wherein the polysilicon layer is formed in a conformal manner. The method includes forming a dummy gate layer over the polysilicon layer.
摘要翻译：本公开涉及FinFET。 FinFET包括在衬底上形成的翅片结构。栅介质层最少部分地缠绕在翅片结构的一段上。栅介质层包含高k栅介质材料。 FinFET包括在栅介质层上共形形成的多晶硅层。 FinFET包括在多晶硅层上形成的金属栅极电极层。本公开提供了制造FinFET的方法。该方法包括提供包含半导体材料的翅片结构。该方法包括在鳍结构上方形成栅极电介质层，栅介质层至少部分地围绕翅片结构缠绕。该方法包括在栅介质层上形成多晶硅层，其中多晶硅层以保形方式形成。该方法包括在多晶硅层上形成伪栅极层。

2. 发明申请

US20130187235A1 COMPOSITE DUMMY GATE WITH CONFORMAL POLYSILICON LAYER FOR FINFET DEVICE 有权
标题翻译：用于FINFET器件的具有合成多晶硅层的复合绝缘栅
公开(公告)号：US20130187235A1
公开(公告)日：2013-07-25
申请号：US13353975
申请日：2012-01-19
申请人： Yuan-Sheng Huang , Tzu-Yen Hsieh , Ming-Ching Chang , Chao-Cheng Chen , Chia-Jen Chen
发明人： Yuan-Sheng Huang , Tzu-Yen Hsieh , Ming-Ching Chang , Chao-Cheng Chen , Chia-Jen Chen
IPC分类号： H01L27/092 , H01L21/28
CPC分类号： H01L29/66545 , H01L21/823807 , H01L21/823821 , H01L21/823828 , H01L27/0924 , H01L29/0649 , H01L29/66795 , H01L29/785
摘要： The present disclosure involves a FinFET. The FinFET includes a fin structure formed over a substrate. A gate dielectric layer is least partially wrapped around a segment of the fin structure. The gate dielectric layer contains a high-k gate dielectric material. The FinFET includes a polysilicon layer conformally formed on the gate dielectric layer. The FinFET includes a metal gate electrode layer formed over the polysilicon layer. The present disclosure provides a method of fabricating a FinFET. The method includes providing a fin structure containing a semiconductor material. The method includes forming a gate dielectric layer over the fin structure, the gate dielectric layer being at least partially wrapped around the fin structure. The method includes forming a polysilicon layer over the gate dielectric layer, wherein the polysilicon layer is formed in a conformal manner. The method includes forming a dummy gate layer over the polysilicon layer.
摘要翻译：本公开涉及FinFET。 FinFET包括在衬底上形成的翅片结构。栅介质层最少部分地缠绕在翅片结构的一段上。栅介质层包含高k栅介质材料。 FinFET包括在栅介质层上共形形成的多晶硅层。 FinFET包括在多晶硅层上形成的金属栅极电极层。本公开提供了制造FinFET的方法。该方法包括提供包含半导体材料的翅片结构。该方法包括在鳍结构上方形成栅极电介质层，栅介质层至少部分地围绕翅片结构缠绕。该方法包括在栅介质层上形成多晶硅层，其中多晶硅层以保形方式形成。该方法包括在多晶硅层上形成伪栅极层。

3. 发明授权

US08691655B2 Method of semiconductor integrated circuit fabrication 有权
标题翻译：半导体集成电路制造方法
公开(公告)号：US08691655B2
公开(公告)日：2014-04-08
申请号：US13471649
申请日：2012-05-15
申请人： Tzu-Yen Hsieh , Ming-Ching Chang , Yuan-Sheng Huang , Ming-Chia Tai , Chao-Cheng Chen
发明人： Tzu-Yen Hsieh , Ming-Ching Chang , Yuan-Sheng Huang , Ming-Chia Tai , Chao-Cheng Chen
IPC分类号： H01L21/02
CPC分类号： H01L27/0629 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes receiving a semiconductor device, patterning a first hard mask to form a first recess in a high-resistor (Hi-R) stack, removing the first hard mask, forming a second recess in the Hi-R stack, forming a second hard mask in the second recess in the Hi-R stack. A HR can then be formed in the semiconductor substrate by the second hard mask and a gate trench etch.
摘要翻译：公开了制造半导体集成电路（IC）的方法。该方法包括接收半导体器件，图案化第一硬掩模以在高电阻（Hi-R）堆叠中形成第一凹槽，去除第一硬掩模，在Hi-R堆叠中形成第二凹槽，形成第二硬掩模在Hi-R堆叠的第二个凹槽中。然后可以通过第二硬掩模和栅沟槽蚀刻在半导体衬底中形成HR。

4. 发明申请

US20130309834A1 METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT FABRICATION 有权
标题翻译：半导体集成电路制造方法
公开(公告)号：US20130309834A1
公开(公告)日：2013-11-21
申请号：US13471649
申请日：2012-05-15
申请人： Tzu-Yen Hsieh , Ming-Ching Chang , Yuan-Sheng Huang , Ming-Chia Tai , Chao-Cheng Chen
发明人： Tzu-Yen Hsieh , Ming-Ching Chang , Yuan-Sheng Huang , Ming-Chia Tai , Chao-Cheng Chen
IPC分类号： H01L21/283 , H01L21/02
CPC分类号： H01L27/0629 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes receiving a semiconductor device, patterning a first hard mask to form a first recess in a high-resistor (Hi-R) stack, removing the first hard mask, forming a second recess in the Hi-R stack, forming a second hard mask in the second recess in the Hi-R stack. A HR can then be formed in the semiconductor substrate by the second hard mask and a gate trench etch.
摘要翻译：公开了制造半导体集成电路（IC）的方法。该方法包括接收半导体器件，图案化第一硬掩模以在高电阻（Hi-R）堆叠中形成第一凹槽，去除第一硬掩模，在Hi-R堆叠中形成第二凹槽，形成第二硬掩模在Hi-R堆叠的第二个凹槽中。然后可以通过第二硬掩模和栅沟槽蚀刻在半导体衬底中形成HR。

5. 发明授权

US09111861B2 Method of fabricating a semiconductor structure with ion-implanted conductive layer 有权
标题翻译：用离子注入导电层制造半导体结构的方法
公开(公告)号：US09111861B2
公开(公告)日：2015-08-18
申请号：US13366669
申请日：2012-02-06
申请人： Tzu-Yen Hsieh , Ming-Ching Chang , Chia-Wei Chang , Chao-Cheng Chen , Chun-Hung Lee , Dai-Lin Wu
发明人： Tzu-Yen Hsieh , Ming-Ching Chang , Chia-Wei Chang , Chao-Cheng Chen , Chun-Hung Lee , Dai-Lin Wu
IPC分类号： H01L21/266 , H01L21/28 , H01L21/033 , H01L21/3213 , H01L21/265
CPC分类号： H01L21/3215 , H01L21/0338 , H01L21/26506 , H01L21/266 , H01L21/28026 , H01L21/28035 , H01L21/28123 , H01L21/32134 , H01L21/32139
摘要： An embodiment of the current disclosure includes a method of providing a substrate, forming a polysilicon layer over the substrate, forming a first photoresist layer on the polysislicon layer, creating a first pattern on the first photoresist layer, wherein some portions of the polysilicon layer are covered by the first photoresist layer and some portions of the polysilicon layer are not covered by the first photoresist layer, implanting ions into the portions of the polysilicon layer that are not covered by the first photoresist layer, removing the first photoresist layer from the polysilicon layer, forming a second photoresist layer on the polysilicon layer, creating a second pattern on the second photoresist layer, and implanting ions into the portions of the polysilicon layer that are not covered by the second photoresist layer, removing the second photoresist layer from the polysilicon layer, and removing portions of the polysilicon layer using an etchant.
摘要翻译：本公开的实施例包括提供衬底的方法，在衬底上形成多晶硅层，在聚苯乙烯层上形成第一光致抗蚀剂层，在第一光致抗蚀剂层上形成第一图案，其中多晶硅层的一些部分由第一光致抗蚀剂层覆盖，并且多晶硅层的一些部分不被第一光致抗蚀剂层覆盖，将离子注入到未被第一光致抗蚀剂层覆盖的多晶硅层的部分中，从多晶硅层去除第一光致抗蚀剂层在所述多晶硅层上形成第二光致抗蚀剂层，在所述第二光致抗蚀剂层上产生第二图案，以及将离子注入所述多晶硅层的未被所述第二光致抗蚀剂层覆盖的部分，从所述多晶硅层除去所述第二光致抗蚀剂层并且使用蚀刻剂去除多晶硅层的部分。

6. 发明授权

US08507979B1 Semiconductor integrated circuit with metal gate 有权
标题翻译：半导体集成电路与金属门
公开(公告)号：US08507979B1
公开(公告)日：2013-08-13
申请号：US13563470
申请日：2012-07-31
申请人： Yuan-Sheng Huang , Ming-Ching Chang , Chao-Cheng Chen
发明人： Yuan-Sheng Huang , Ming-Ching Chang , Chao-Cheng Chen
IPC分类号： H01L29/66
CPC分类号： H01L29/4966 , H01L29/517 , H01L29/66477 , H01L29/66545 , H01L29/78
摘要： A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a semiconductor substrate and forming a gate trench therein. The method also includes filling in the gate trench partially with a work-function (WF) metal stack, and filling in the remaining gate trench with a dummy-filling-material (DFM) over the WF metal stack. A sub-gate trench is formed by etching-back the WF metal stack in the gate trench, and is filled with an insulator cap to form an isolation region in the gate trench. The DFM is fully removed to from a MG-center trench (MGCT) in the gate trench, which is filled with a fill metal.
摘要翻译：公开了制造半导体集成电路（IC）的方法。该方法包括提供半导体衬底并在其中形成栅极沟槽。该方法还包括用工作功能（WF）金属堆叠部分地填充栅极沟槽，并且在WF金属堆叠上用虚拟填充材料（DFM）填充剩余的栅极沟槽。通过蚀刻在栅极沟槽中的WF金属堆叠形成子栅极沟槽，并且填充有绝缘体帽以在栅极沟槽中形成隔离区域。 DFM从栅极沟槽中的MG-中心沟槽（MGCT）被完全去除，其填充有填充金属。

7. 发明申请

US20120108046A1 Patterning Methodology for Uniformity Control 有权
标题翻译：均匀性控制的图案化方法
公开(公告)号：US20120108046A1
公开(公告)日：2012-05-03
申请号：US13281862
申请日：2011-10-26
申请人： Yu Chao Lin , Ming-Ching Chang , Yih-Ann Lin , Ryan Chia-Jen Chen , Chao-Cheng Chen
发明人： Yu Chao Lin , Ming-Ching Chang , Yih-Ann Lin , Ryan Chia-Jen Chen , Chao-Cheng Chen
IPC分类号： H01L21/28 , H01L21/308
CPC分类号： H01L21/32139 , H01L21/0276 , H01L21/28194 , H01L21/31122 , H01L21/31138 , H01L21/823437 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patternable layer over a substrate. The method includes forming a first layer over the patternable layer. The method includes forming a second layer over the first layer. The second layer is substantially thinner than the first layer. The method includes patterning the second layer with a photoresist material through a first etching process to form a patterned second layer. The method includes patterning the first layer with the patterned second layer through a second etching process to form a patterned first layer. The first and second layers have substantially different etching rates during the second etching process. The method includes patterning the patternable layer with the patterned first layer through a third etching process.
摘要翻译：本公开提供了制造半导体器件的方法。该方法包括在衬底上形成可图案化层。该方法包括在可图案层上形成第一层。该方法包括在第一层上形成第二层。第二层比第一层薄得多。该方法包括通过第一蚀刻工艺用光致抗蚀剂材料图案化第二层以形成图案化的第二层。该方法包括通过第二蚀刻工艺将具有图案化的第二层的第一层图案化以形成图案化的第一层。第一和第二层在第二蚀刻工艺期间具有显着不同的蚀刻速率。该方法包括通过第三蚀刻工艺对具有图案化的第一层的图案化层进行图案化。

8. 发明授权

US08273632B2 Patterning methodology for uniformity control 有权
标题翻译：均匀性控制的图案化方法
公开(公告)号：US08273632B2
公开(公告)日：2012-09-25
申请号：US13281862
申请日：2011-10-26
申请人： Yu Chao Lin , Ming-Ching Chang , Yih-Ann Lin , Ryan Chia-Jen Chen , Chao-Cheng Chen
发明人： Yu Chao Lin , Ming-Ching Chang , Yih-Ann Lin , Ryan Chia-Jen Chen , Chao-Cheng Chen
IPC分类号： H01L21/336
CPC分类号： H01L21/32139 , H01L21/0276 , H01L21/28194 , H01L21/31122 , H01L21/31138 , H01L21/823437 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patternable layer over a substrate. The method includes forming a first layer over the patternable layer. The method includes forming a second layer over the first layer. The second layer is substantially thinner than the first layer. The method includes patterning the second layer with a photoresist material through a first etching process to form a patterned second layer. The method includes patterning the first layer with the patterned second layer through a second etching process to form a patterned first layer. The first and second layers have substantially different etching rates during the second etching process. The method includes patterning the patternable layer with the patterned first layer through a third etching process.
摘要翻译：本公开提供了制造半导体器件的方法。该方法包括在衬底上形成可图案化层。该方法包括在可图案层上形成第一层。该方法包括在第一层上形成第二层。第二层比第一层薄得多。该方法包括通过第一蚀刻工艺用光致抗蚀剂材料图案化第二层以形成图案化的第二层。该方法包括通过第二蚀刻工艺将具有图案化的第二层的第一层图案化以形成图案化的第一层。第一和第二层在第二蚀刻工艺期间具有显着不同的蚀刻速率。该方法包括通过第三蚀刻工艺对具有图案化的第一层的图案化层进行图案化。

9. 发明授权

US08053323B1 Patterning methodology for uniformity control 有权
标题翻译：均匀性控制的图案化方法
公开(公告)号：US08053323B1
公开(公告)日：2011-11-08
申请号：US12938571
申请日：2010-11-03
申请人： Yu Chao Lin , Ming-Ching Chang , Yih-Ann Lin , Ryan Chia-Jen Chen , Chao-Cheng Chen
发明人： Yu Chao Lin , Ming-Ching Chang , Yih-Ann Lin , Ryan Chia-Jen Chen , Chao-Cheng Chen
IPC分类号： H01L21/336
CPC分类号： H01L21/32139 , H01L21/0276 , H01L21/28194 , H01L21/31122 , H01L21/31138 , H01L21/823437 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patternable layer over a substrate. The method includes forming a first layer over the patternable layer. The method includes forming a second layer over the first layer. The second layer is substantially thinner than the first layer. The method includes patterning the second layer with a photoresist material through a first etching process to form a patterned second layer. The method includes patterning the first layer with the patterned second layer through a second etching process to form a patterned first layer. The first and second layers have substantially different etching rates during the second etching process. The method includes patterning the patternable layer with the patterned first layer through a third etching process.
摘要翻译：本公开提供了制造半导体器件的方法。该方法包括在衬底上形成可图案化层。该方法包括在可图案层上形成第一层。该方法包括在第一层上形成第二层。第二层比第一层薄得多。该方法包括通过第一蚀刻工艺用光致抗蚀剂材料图案化第二层以形成图案化的第二层。该方法包括通过第二蚀刻工艺将具有图案化的第二层的第一层图案化以形成图案化的第一层。第一和第二层在第二蚀刻工艺期间具有显着不同的蚀刻速率。该方法包括通过第三蚀刻工艺对具有图案化的第一层的图案化层进行图案化。

10. 发明授权

US07109085B2 Etching process to avoid polysilicon notching 有权
标题翻译：蚀刻工艺避免多晶硅切口
公开(公告)号：US07109085B2
公开(公告)日：2006-09-19
申请号：US11033912
申请日：2005-01-11
申请人： Shiang-Bau Wang , Li-Te Lin , Ming-Ching Chang , Ryan Chia-Jen Chen , Yuan-Hung Chiu , Hun-Jan Tao
发明人： Shiang-Bau Wang , Li-Te Lin , Ming-Ching Chang , Ryan Chia-Jen Chen , Yuan-Hung Chiu , Hun-Jan Tao
IPC分类号： H01L21/336
CPC分类号： H01L21/32137 , H01L21/31116 , H01L21/823828
摘要： A method for plasma assisted etching of a polysilicon containing gate electrode to reduce or avoid polysilicon notching at a base portion including providing a semiconducting substrate; forming a gate dielectric layer on the semiconducting substrate; forming a polysilicon layer on the gate dielectric; patterning a photoresist layer over the polysilicon layer for etching a gate electrode; carrying out a first plasma assisted etch process to etch through a major thickness portion of the polysilicon layer; carrying out a first inert gas plasma treatment; carrying out a second plasma assisted etch process to include exposing portions of the underlying gate dielectric layer; carrying out a second inert gas plasma treatment; and, carrying out a third plasma assisted etch process to fully expose the underlying gate dielectric layer adjacent either side of the gate electrodes.
摘要翻译：一种用于等离子体辅助蚀刻含多晶硅栅电极的方法，以减少或避免在包括提供半导体衬底的基极部分处的多晶硅刻蚀; 在所述半导体衬底上形成栅介电层; 在栅极电介质上形成多晶硅层; 在多晶硅层上形成光致抗蚀剂层以蚀刻栅电极; 执行第一等离子体辅助蚀刻工艺以蚀刻通过多晶硅层的主要厚度部分; 进行第一惰性气体等离子体处理; 执行第二等离子体辅助蚀刻工艺以包括暴露下面的栅介电层的部分; 进行第二次惰性气体等离子体处理; 并且执行第三等离子体辅助蚀刻工艺以完全暴露邻近栅电极的任一侧的底层栅介质层。

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