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1. 发明申请

US20130320410A1 METAL GATE ELECTRODE OF A SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件的金属栅极电极
公开(公告)号：US20130320410A1
公开(公告)日：2013-12-05
申请号：US13484047
申请日：2012-05-30
申请人： Jr-Jung Lin , Chih-Han Lin , Jin-Aun Ng , Ming-Ching Chang , Chao-Cheng Chen
发明人： Jr-Jung Lin , Chih-Han Lin , Jin-Aun Ng , Ming-Ching Chang , Chao-Cheng Chen
IPC分类号： H01L29/78 , H01L21/283
CPC分类号： H01L29/78 , H01L21/283 , H01L21/823842 , H01L29/4966 , H01L29/4983 , H01L29/66545
摘要： The invention relates to integrated circuit fabrication, and more particularly to a metal gate electrode. An exemplary structure for a semiconductor device comprises a substrate comprising a major surface; a first rectangular gate electrode on the major surface comprising a first layer of multi-layer material; a first dielectric material adjacent to one side of the first rectangular gate electrode; and a second dielectric material adjacent to the other 3 sides of the first rectangular gate electrode, wherein the first dielectric material and the second dielectric material collectively surround the first rectangular gate electrode.
摘要翻译：本发明涉及集成电路制造，更具体地涉及金属栅电极。半导体器件的示例性结构包括：包括主表面的衬底; 主表面上的第一矩形栅电极，包括第一层多层材料; 与第一矩形栅电极的一侧相邻的第一电介质材料; 以及与所述第一矩形栅电极的其他3侧相邻的第二电介质材料，其中所述第一电介质材料和所述第二电介质材料共同围绕所述第一矩形栅电极。

2. 发明授权

US09991375B2 Metal gate electrode of a semiconductor device 有权
公开(公告)号：US09991375B2
公开(公告)日：2018-06-05
申请号：US13484047
申请日：2012-05-30
申请人： Jr-Jung Lin , Chih-Han Lin , Jin-Aun Ng , Ming-Ching Chang , Chao-Cheng Chen
发明人： Jr-Jung Lin , Chih-Han Lin , Jin-Aun Ng , Ming-Ching Chang , Chao-Cheng Chen
IPC分类号： H01L29/78 , H01L21/283 , H01L29/49 , H01L29/66 , H01L21/8238
CPC分类号： H01L29/78 , H01L21/283 , H01L21/823842 , H01L29/4966 , H01L29/4983 , H01L29/66545
摘要： The invention relates to integrated circuit fabrication, and more particularly to a metal gate electrode. An exemplary structure for a semiconductor device comprises a substrate comprising a major surface; a first rectangular gate electrode on the major surface comprising a first layer of multi-layer material; a first dielectric material adjacent to one side of the first rectangular gate electrode; and a second dielectric material adjacent to the other 3 sides of the first rectangular gate electrode, wherein the first dielectric material and the second dielectric material collectively surround the first rectangular gate electrode.

3. 发明申请

US20140001559A1 Dummy Gate Electrode of Semiconductor Device 有权
公开(公告)号：US20140001559A1
公开(公告)日：2014-01-02
申请号：US13538734
申请日：2012-06-29
申请人： Jr-Jung Lin , Chih-Han Lin , Ming-Ching Chang
发明人： Jr-Jung Lin , Chih-Han Lin , Ming-Ching Chang
IPC分类号： H01L27/088 , H01L21/283
CPC分类号： H01L29/66795 , H01L21/30604 , H01L21/823431 , H01L29/42372 , H01L29/66545 , H01L29/6681
摘要： The disclosure relates to a dummy gate electrode of a semiconductor device. An embodiment comprises a substrate comprising a first surface; an insulation region covering a portion of the first surface, wherein the top of the insulation region defines a second surface; and a dummy gate electrode over the second surface, wherein the dummy gate electrode comprises a bottom and a base broader than the bottom, wherein a ratio of a width of the bottom to a width of the base is from about 0.5 to about 0.9.

4. 发明授权

US08803241B2 Dummy gate electrode of semiconductor device 有权
标题翻译：半导体器件的虚拟栅电极
公开(公告)号：US08803241B2
公开(公告)日：2014-08-12
申请号：US13538734
申请日：2012-06-29
申请人： Jr-Jung Lin , Chih-Han Lin , Ming-Ching Chang
发明人： Jr-Jung Lin , Chih-Han Lin , Ming-Ching Chang
IPC分类号： H01L21/70
CPC分类号： H01L29/66795 , H01L21/30604 , H01L21/823431 , H01L29/42372 , H01L29/66545 , H01L29/6681
摘要： The disclosure relates to a dummy gate electrode of a semiconductor device. An embodiment comprises a substrate comprising a first surface; an insulation region covering a portion of the first surface, wherein the top of the insulation region defines a second surface; and a dummy gate electrode over the second surface, wherein the dummy gate electrode comprises a bottom and a base broader than the bottom, wherein a ratio of a width of the bottom to a width of the base is from about 0.5 to about 0.9.
摘要翻译：本公开涉及半导体器件的虚拟栅电极。一个实施例包括一个包括第一表面的基底; 覆盖所述第一表面的一部分的绝缘区域，其中所述绝缘区域的顶部限定第二表面; 以及在所述第二表面上的虚拟栅电极，其中所述虚拟栅电极包括底部和比所述底部宽的底部，其中所述底部的宽度与所述基部的宽度的比率为约0.5至约0.9。

5. 发明授权

US09153440B2 Method of forming a semiconductor device 有权
标题翻译：形成半导体器件的方法
公开(公告)号：US09153440B2
公开(公告)日：2015-10-06
申请号：US13428923
申请日：2012-03-23
申请人： Chih-Han Lin , Ming-Ching Chang , Ryan Chia-Jen Chen , Yih-Ann Lin , Jr-Jung Lin
发明人： Chih-Han Lin , Ming-Ching Chang , Ryan Chia-Jen Chen , Yih-Ann Lin , Jr-Jung Lin
IPC分类号： H01L21/308 , H01L21/033 , H01L21/311 , H01L21/768
CPC分类号： H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/31144 , H01L21/76816
摘要： A method includes providing a first mask pattern over a substrate, forming first spacers adjoining sidewalls of the first mask pattern, removing the first mask pattern, forming second spacers adjoining sidewalls of the first spacers, forming a filling layer over the substrate and between the second spacers, and forming a second mask pattern over the substrate.
摘要翻译：一种方法包括在衬底上提供第一掩模图案，形成与第一掩模图案的侧壁相邻的第一间隔物，去除第一掩模图案，形成邻接第一间隔物的侧壁的第二间隔物，在衬底上形成填充层，并且在衬底上形成第二掩模图案。

6. 发明授权

US08163625B2 Method for fabricating an isolation structure 有权
标题翻译：隔离结构的制造方法
公开(公告)号：US08163625B2
公开(公告)日：2012-04-24
申请号：US12753972
申请日：2010-04-05
申请人： Yih-Ann Lin , Hao-Ming Lien , Ryan Chia-Jen Chen , Jr Jung Lin , Yu Chao Lin , Chih-Han Lin
发明人： Yih-Ann Lin , Hao-Ming Lien , Ryan Chia-Jen Chen , Jr Jung Lin , Yu Chao Lin , Chih-Han Lin
IPC分类号： H01L21/76
CPC分类号： H01L21/76232
摘要： The disclosure relates to integrated circuit fabrication, and more particularly to an electronic device with an isolation structure having almost no divot. An exemplary method for fabricating an isolation structure, comprising: forming a pad oxide layer over a top surface of a substrate; forming an opening in the pad oxide layer, exposing a portion of the substrate; etching the exposed portion of the substrate, forming a trench in the substrate; filling the trench with an insulator; exposing a surface of the pad oxide layer and a surface of the insulator to a vapor mixture including at least an NH3 and a fluorine-containing compound; and heating the substrate at a temperature between 100° C. to 200° C.
摘要翻译：本公开涉及集成电路制造，并且更具体地涉及具有几乎没有纹波的隔离结构的电子器件。一种用于制造隔离结构的示例性方法，包括：在衬底的顶表面上形成衬垫氧化物层; 在所述衬垫氧化物层中形成开口，暴露所述衬底的一部分; 蚀刻衬底的暴露部分，在衬底中形成沟槽; 用绝缘体填充沟槽; 将衬垫氧化物层的表面和绝缘体的表面暴露于至少包含NH 3和含氟化合物的蒸汽混合物; 并在100℃至200℃的温度下加热基材。

7. 发明授权

US08722541B2 Double patterning method for semiconductor devices 有权
标题翻译：半导体器件的双重图案化方法
公开(公告)号：US08722541B2
公开(公告)日：2014-05-13
申请号：US13421606
申请日：2012-03-15
申请人： Chih-Han Lin
发明人： Chih-Han Lin
IPC分类号： H01L21/302
CPC分类号： H01L29/49 , H01L21/0337 , H01L21/32139 , H01L21/823437 , H01L27/0207
摘要： A method of fabricating a semiconductor device is disclosed. The exemplary method includes providing a substrate including a device layer and a sacrificial layer formed over the device layer and patterning the sacrificial layer thereby defining a cut pattern. The cut pattern of the sacrificial layer having an initial width. The method further includes depositing a mask layer over the device layer and over the cut pattern of the sacrificial layer. The method further includes patterning the mask layer thereby defining a line pattern including first and second portions separated by the cut pattern of the sacrificial layer and selectively removing the cut pattern of the sacrificial layer thereby forming a gap that separates the first and second portions of the line pattern of the mask layer. The method further includes patterning the device layer using the first and second portions of the line pattern of the mask layer.
摘要翻译：公开了制造半导体器件的方法。示例性方法包括提供包括在器件层上形成的器件层和牺牲层的衬底，并且图案化牺牲层，从而限定切割图案。具有初始宽度的牺牲层的切割图案。该方法还包括在器件层上方和牺牲层的切割图案上方沉积掩模层。该方法还包括图案化掩模层，从而限定线图案，该线图案包括由牺牲层的切割图案分隔开的第一和第二部分，并且选择性地移除牺牲层的切割图案，从而形成分隔第一和第二部分的间隙掩模层的线图案。该方法还包括使用掩模层的线图案的第一和第二部分图案化器件层。

8. 发明申请

US20070238306A1 METHOD OF FORMING DUAL DAMASCENE SEMICONDUCTOR DEVICE 有权
标题翻译：形成双重半导体半导体器件的方法
公开(公告)号：US20070238306A1
公开(公告)日：2007-10-11
申请号：US11279055
申请日：2006-04-07
申请人： Chih-Han Lin , Kun-Ei Chen
发明人： Chih-Han Lin , Kun-Ei Chen
IPC分类号： H01L21/467
CPC分类号： H01L21/76829 , H01L21/76804 , H01L21/76807 , H01L21/76808
摘要： A method of forming a dual damascene includes forming first, second and third material layers sequentially over a substrate. The first, second and third material layers have first, second and third thicknesses, respectively. An opening is etched within the first material layer while a portion or all of the thickness of the third layer is simultaneously removed. The ratio of the depth of the opening and the thickness of the third material layer removed, correspond to an etch selectivity of the first material layer and the second material layer. The etching operation may be automatically terminated to produce the opening with a predetermined depth.
摘要翻译：形成双镶嵌层的方法包括在衬底上依次形成第一，第二和第三材料层。第一，第二和第三材料层分别具有第一，第二和第三厚度。在第一材料层内蚀刻开口，同时去除第三层的厚度的一部分或全部。开口的深度与去除的第三材料层的厚度的比率对应于第一材料层和第二材料层的蚀刻选择性。蚀刻操作可以自动终止以产生具有预定深度的开口。

9. 发明申请

US20100255654A1 METHOD FOR FABRICATING AN ISOLATION STRUCTURE 有权
标题翻译：制造隔离结构的方法
公开(公告)号：US20100255654A1
公开(公告)日：2010-10-07
申请号：US12753972
申请日：2010-04-05
申请人： Yih-Ann Lin , Hao-Ming Lien , Ryan Chia-Jen Chen , Jung Lin, JR. , Yu Chao Lin , Chih-Han Lin
发明人： Yih-Ann Lin , Hao-Ming Lien , Ryan Chia-Jen Chen , Jung Lin, JR. , Yu Chao Lin , Chih-Han Lin
IPC分类号： H01L21/762
CPC分类号： H01L21/76232
摘要： The disclosure relates to integrated circuit fabrication, and more particularly to an electronic device with an isolation structure having almost no divot. An exemplary method for fabricating an isolation structure, comprising: forming a pad oxide layer over a top surface of a substrate; forming an opening in the pad oxide layer, exposing a portion of the substrate; etching the exposed portion of the substrate, forming a trench in the substrate; filling the trench with an insulator; exposing a surface of the pad oxide layer and a surface of the insulator to a vapor mixture including at least an NH3 and a fluorine-containing compound; and heating the substrate at a temperature between 100° C. to 200° C.
摘要翻译：本公开涉及集成电路制造，并且更具体地涉及具有几乎没有纹波的隔离结构的电子器件。一种用于制造隔离结构的示例性方法，包括：在衬底的顶表面上形成衬垫氧化物层; 在所述衬垫氧化物层中形成开口，暴露所述衬底的一部分; 蚀刻衬底的暴露部分，在衬底中形成沟槽; 用绝缘体填充沟槽; 将衬垫氧化物层的表面和绝缘体的表面暴露于至少包含NH 3和含氟化合物的蒸汽混合物; 并在100℃至200℃的温度下加热基材。

10. 发明申请

US20130244430A1 Double Patterning Method for Semiconductor Devices 有权
标题翻译：半导体器件的双重图案化方法
公开(公告)号：US20130244430A1
公开(公告)日：2013-09-19
申请号：US13421606
申请日：2012-03-15
申请人： Chih-Han Lin
发明人： Chih-Han Lin
IPC分类号： H01L21/306 , H01L21/308
CPC分类号： H01L29/49 , H01L21/0337 , H01L21/32139 , H01L21/823437 , H01L27/0207
摘要： A method of fabricating a semiconductor device is disclosed. The exemplary method includes providing a substrate including a device layer and a sacrificial layer formed over the device layer and patterning the sacrificial layer thereby defining a cut pattern. The cut pattern of the sacrificial layer having an initial width. The method further includes depositing a mask layer over the device layer and over the cut pattern of the sacrificial layer. The method further includes patterning the mask layer thereby defining a line pattern including first and second portions separated by the cut pattern of the sacrificial layer and selectively removing the cut pattern of the sacrificial layer thereby forming a gap that separates the first and second portions of the line pattern of the mask layer. The method further includes patterning the device layer using the first and second portions of the line pattern of the mask layer.
摘要翻译：公开了制造半导体器件的方法。示例性方法包括提供包括在器件层上形成的器件层和牺牲层的衬底，并且图案化牺牲层，从而限定切割图案。具有初始宽度的牺牲层的切割图案。该方法还包括在器件层上方和牺牲层的切割图案上方沉积掩模层。该方法还包括图案化掩模层，从而限定线图案，该线图案包括由牺牲层的切割图案分隔开的第一和第二部分，并且选择性地移除牺牲层的切割图案，从而形成将第一和第二部分分隔开的间隙掩模层的线图案。该方法还包括使用掩模层的线图案的第一和第二部分图案化器件层。

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