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21. 发明授权

US06312997B1 Low voltage high performance semiconductor devices and methods 失效
公开(公告)号：US06312997B1
公开(公告)日：2001-11-06
申请号：US09132904
申请日：1998-08-12
申请人： Luan C. Tran
发明人： Luan C. Tran
IPC分类号： H01L21336
CPC分类号： H01L29/66537 , H01L21/26586 , H01L21/823807 , H01L27/0922 , H01L29/1083
摘要： A method for adjusting Vt while minimizing parasitic capacitance for low voltage high speed semiconductor devices. The method uses shadow effects and an angled punch through prevention implant between vertical structures to provide a graded implant. The implant angle is greater than or equal to arc tangent of S/H where S is the horizontal distance between, and H is the height of, such vertical structures.

22. 发明授权

US06215151B1 Methods of forming integrated circuitry and integrated circuitry 有权
标题翻译：形成集成电路和集成电路的方法
公开(公告)号：US06215151B1
公开(公告)日：2001-04-10
申请号：US09255667
申请日：1999-02-23
申请人： Zhiqiang Wu , Luan C. Tran , Robert Kerr , Shubneesh Batra , Rongsheng Yang
发明人： Zhiqiang Wu , Luan C. Tran , Robert Kerr , Shubneesh Batra , Rongsheng Yang
IPC分类号： H01L27148
CPC分类号： H01L21/823807
摘要： Integrated circuitry and methods of forming integrated circuitry are described. In one implementation, a common masking step is utilized to provide source/drain diffusion regions and halo ion implantation or dopant regions relative to the source/drain regions within one well region of a substrate; and well contact diffusion regions within another well region of the substrate. The common masking step preferably defines at least one mask opening over the substrate within which the well contact diffusion region is to be formed, and the mask opening is suitably dimensioned to reduce the amount of halo ion implantation dopant which ultimately reaches the substrate therebelow. According to one aspect, a plurality of mask openings are provided. According to another aspect, a suitably-dimensioned single mask opening is provided. In yet another aspect, a unique well region construction is provided with one or more complementary mask openings which is (are) configured to, in connection with the provision of the halo ion implantation dopant, block the amount of implantation dopant which ultimately reaches the substrate adjacent the well contact diffusion regions. Accordingly, at least some of the well contact diffusion region(s) remain in substantial contact with the well region after the doping of the substrate with the halo ion implantation dopant.
摘要翻译：描述了形成集成电路的集成电路和方法。在一个实现中，利用公共掩模步骤来相对于衬底的一个阱区域内的源极/漏极区域提供源极/漏极扩散区域和晕圈离子注入或掺杂区域; 以及在衬底的另一个阱区域内的良好接触扩散区域。常见的掩蔽步骤优选地限定在其上将要形成阱接触扩散区的衬底上的至少一个掩模开口，并且掩模开口被适当地设定尺寸以减少最终到达衬底的卤素离子注入掺杂剂的量。根据一个方面，提供了多个掩模开口。根据另一方面，提供了适当尺寸的单个掩模开口。在另一方面，独特的井区结构设置有一个或多个互补掩模开口，其被配置为与提供卤素离子注入掺杂剂相结合，阻止最终到达衬底的注入掺杂剂的量邻近阱接触扩散区。因此，在用卤素离子注入掺杂剂掺杂衬底之后，至少一些阱接触扩散区域保持与阱区基本接触。

23. 发明授权

US6159790A Method of controlling outdiffusion in doped three-dimensional film by using angled implants 有权
标题翻译：通过使用倾斜植入物控制掺杂三维膜中的扩散扩散的方法
公开(公告)号：US6159790A
公开(公告)日：2000-12-12
申请号：US310489
申请日：1999-05-12
申请人： Fernando Gonzalez , D. Mark Durcan , Luan C. Tran , Robert B. Kerr , David F. Cheffings , Howard E. Rhodes
发明人： Fernando Gonzalez , D. Mark Durcan , Luan C. Tran , Robert B. Kerr , David F. Cheffings , Howard E. Rhodes
IPC分类号： H01L21/02 , H01L21/8242 , H01L21/70
CPC分类号： H01L27/10852 , H01L28/82
摘要： A solid state fabrication technique for controlling the amount of outdiffusion from a three-dimensional film is comprised of the step of providing a first layer of insitu doped film in a manner to define an upper portion and a lower portion. A second layer of undoped film is provided on top of the first layer to similarly define an upper portion and a lower portion. The first and second layers are etched according to a predetermined pattern. The second layer is doped to obtain a desired dopant density which decreases from the upper portion to the lower portion. Outdiffusion of the dopant from the upper portion of the second layer results in the dopant migrating to the lower portion of the second layer. Thus, outdiffusion into the substrate, and the problems caused thereby, are eliminated or greatly reduced.
摘要翻译：用于控制来自三维膜的向外扩散量的固态制造技术包括以限定上部和下部的方式提供第一层原位掺杂膜的步骤。第二层未掺杂的膜设置在第一层的顶部上，以类似地限定上部和下部。根据预定图案蚀刻第一层和第二层。掺杂第二层以获得从上部向下部减小的期望的掺杂剂密度。从第二层的上部扩散掺杂剂导致掺杂剂迁移到第二层的下部。因此，消除或大大降低了向基板的扩散和由此引起的问题。

24. 发明授权

US08723326B2 Semiconductor structures including tight pitch contacts 有权
标题翻译：包括紧密节距触点的半导体结构
公开(公告)号：US08723326B2
公开(公告)日：2014-05-13
申请号：US13194558
申请日：2011-07-29
申请人： Luan C. Tran
发明人： Luan C. Tran
IPC分类号： H01L23/48
CPC分类号： H01L21/76802 , H01L21/02164 , H01L21/0228 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/31144 , H01L21/3141 , H01L21/31608 , H01L21/7681 , H01L21/76816 , H01L21/76877 , H01L23/481 , H01L27/108 , H01L2924/0002 , H01L2924/00
摘要： Methods of fabricating semiconductor structures incorporating tight pitch contacts aligned with active area features and of simultaneously fabricating self-aligned tight pitch contacts and conductive lines using various techniques for defining patterns having sublithographic dimensions. Semiconductor structures having tight pitch contacts aligned with active area features and, optionally, aligned conductive lines are also disclosed, as are semiconductor structures with tight pitch contact holes and aligned trenches for conductive lines.
摘要翻译：制造具有与有源区域特征对准的紧密节距触点的半导体结构的方法，并且使用用于限定具有亚光刻尺寸的图案的各种技术同时制造自对准的紧密节距触点和导线。还公开了具有与有源区域特征对准的紧密节距触点的半导体结构以及可选地对齐的导线，半导体结构具有紧密的节距接触孔和用于导线的对准的沟槽。

25. 发明授权

US08481417B2 Semiconductor structures including tight pitch contacts and methods to form same 有权
标题翻译：半导体结构包括紧密节距触点和形成相同的方法
公开(公告)号：US08481417B2
公开(公告)日：2013-07-09
申请号：US11833386
申请日：2007-08-03
申请人： Luan C. Tran
发明人： Luan C. Tran
IPC分类号： H01L21/44
CPC分类号： H01L21/76802 , H01L21/02164 , H01L21/0228 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/31144 , H01L21/3141 , H01L21/31608 , H01L21/7681 , H01L21/76816 , H01L21/76877 , H01L23/481 , H01L27/108 , H01L2924/0002 , H01L2924/00
摘要： Methods of fabricating semiconductor structures incorporating tight pitch contacts aligned with active area features and of simultaneously fabricating self-aligned tight pitch contacts and conductive lines using various techniques for defining patterns having sublithographic dimensions. Semiconductor structures having tight pitch contacts aligned with active area features and, optionally, aligned conductive lines are also disclosed, as are semiconductor structures with tight pitch contact holes and aligned trenches for conductive lines.
摘要翻译：制造具有与有源区域特征对准的紧密节距触点的半导体结构的方法，并且使用用于限定具有亚光刻尺寸的图案的各种技术同时制造自对准的紧密节距触点和导线。还公开了具有与有源区域特征对准的紧密节距触点的半导体结构以及可选地对齐的导线，半导体结构具有紧密的节距接触孔和用于导线的对准的沟槽。

26. 发明授权

US08158476B2 Integrated circuit fabrication 有权
标题翻译：集成电路制造
公开(公告)号：US08158476B2
公开(公告)日：2012-04-17
申请号：US12850511
申请日：2010-08-04
申请人： Luan C. Tran , John Lee , Zengtao “Tony” Liu , Eric Freeman , Russell Nielsen
发明人： Luan C. Tran , John Lee , Zengtao “Tony” Liu , Eric Freeman , Russell Nielsen
IPC分类号： H01L21/8242
CPC分类号： H01L21/0334 , H01L21/0337 , H01L21/0338 , H01L21/30604 , H01L21/3083 , H01L21/31144 , H01L21/76816 , H01L21/76877 , H01L21/76897 , H01L23/544 , H01L27/1052 , H01L2924/0002 , Y10S438/947 , H01L2924/00
摘要： A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.
摘要翻译：用于限定集成电路中的图案的方法包括在衬底的第一区域上使用光刻法在第一光致抗蚀剂层中限定多个特征。该方法还包括使用音调倍增以在光致抗蚀剂层中的每个特征的下掩蔽层中产生至少两个特征。下掩蔽层中的特征包括环形端。该方法还包括用第二光致抗蚀剂层覆盖包括下掩蔽层中的环状末端的衬底的第二区域。该方法还包括通过下掩蔽层中的特征蚀刻衬底中的沟槽图案，而不在第二区域内进行蚀刻。沟槽具有沟槽宽度。

27. 发明申请

US20120025869A1 NON-VOLATILE FIELD PROGRAMMABLE GATE ARRAY 有权
标题翻译：非挥发性可编程门阵列
公开(公告)号：US20120025869A1
公开(公告)日：2012-02-02
申请号：US13209704
申请日：2011-08-15
申请人： Chih-Wei Hung , Chia-Ta Hsieh , Luan C. Tran
发明人： Chih-Wei Hung , Chia-Ta Hsieh , Luan C. Tran
IPC分类号： H03K19/177
CPC分类号： G11C16/10 , G11C16/0441 , H03K19/1776
摘要： A non-volatile memory device includes a first metal-oxide-semiconductor (CMOS) device coupled to a bit line and a word line and a second CMOS device coupled to the first CMOS device. The second CMOS device is also coupled to a complementary bit line and a complementary word line. The first and second CMOS devices are complementary to one another. An output node is coupled between the first CMOS device and the second CMOS device. A method of programming a non-volatile field programmable gate array (NV-FPGA) includes coupling an information handling system to the FPGA, performing a block erase of a plurality of memory cells in the FPGA, verifying that the block erase is successful, programming an upper page of the FPGA, verifying that the upper page programming is successful, programming a lower page of the FPGA and verifying that the lower page programming is successful.
摘要翻译：非易失性存储器件包括耦合到位线和字线的第一金属氧化物半导体（CMOS）器件和耦合到第一CMOS器件的第二CMOS器件。第二CMOS器件还耦合到互补位线和互补字线。第一和第二CMOS器件彼此互补。输出节点耦合在第一CMOS器件和第二CMOS器件之间。编程非易失性现场可编程门阵列（NV-FPGA）的方法包括将信息处理系统耦合到FPGA，对FPGA中的多个存储单元进行块擦除，验证块擦除成功，编程 FPGA的上一页，验证上页编程是否成功，编写FPGA的下一页，并验证下页编程是否成功。

28. 发明申请

US20110014574A1 METHOD OF FORMING PITCH MULTIPLED CONTACTS 有权
标题翻译：形成拼接联系人的方法
公开(公告)号：US20110014574A1
公开(公告)日：2011-01-20
申请号：US12894633
申请日：2010-09-30
申请人： Luan C. Tran
发明人： Luan C. Tran
IPC分类号： G03F7/20
CPC分类号： H01L21/3088 , H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/76805 , H01L21/76816 , H01L21/76838 , H01L27/1052 , H01L27/10888 , H01L27/11521
摘要： Methods of forming electrically conductive and/or semiconductive features for use in integrated circuits are disclosed. Various pattern transfer and etching steps can be used, in combination with pitch-reduction techniques, to create densely-packed features. The features can have a reduced pitch in one direction and a wider pitch in another direction. Conventional photo-lithography steps can be used in combination with pitch-reduction techniques to form elongate, pitch-reduced features such as bit-line contacts, for example.
摘要翻译：公开了形成用于集成电路的导电和/或半导体特征的方法。可以使用各种图案转移和蚀刻步骤，结合减音技术来产生密集包装的特征。这些特征可以在一个方向上具有减小的间距，在另一方向上可以具有较宽的间距。常规的光刻步骤可以与俯仰减小技术组合使用以形成例如细长的俯仰特征，例如位线接触。

29. 发明申请

US20110008970A1 Methods of Forming Semiconductor Constructions 有权
标题翻译：形成半导体结构的方法
公开(公告)号：US20110008970A1
公开(公告)日：2011-01-13
申请号：US12886459
申请日：2010-09-20
申请人： Ramakanth Alapati , Ardavan Niroomand , Gurtej S. Sandhu , Luan C. Tran
发明人： Ramakanth Alapati , Ardavan Niroomand , Gurtej S. Sandhu , Luan C. Tran
IPC分类号： H01L21/31
CPC分类号： H01L21/3086 , H01L21/0337 , H01L21/76232 , H01L27/105 , H01L27/1052
摘要： The invention includes methods of forming isolation regions for semiconductor constructions. A hard mask can be formed and patterned over a semiconductor substrate, with the patterned hard mask exposing a region of the substrate. Such exposed region can be etched to form a first opening having a first width. The first opening is narrowed with a conformal layer of carbon-containing material. The conformal layer is punched through to expose substrate along a bottom of the narrowed opening. The exposed substrate is removed to form a second opening which joins to the first opening, and which has a second width less than the first width. The carbon-containing material is then removed from within the first opening, and electrically insulative material is formed within the first and second openings The electrically insulative material can substantially fill the first opening, and leave a void within the second opening.
摘要翻译：本发明包括形成用于半导体结构的隔离区域的方法。可以在半导体衬底上形成并图案化硬掩模，其中图案化的硬掩模暴露衬底的区域。可以蚀刻这样的暴露区域以形成具有第一宽度的第一开口。第一个开口用含碳材料的共形层变窄。穿过保形层以沿着狭窄的开口的底部露出衬底。去除暴露的衬底以形成连接到第一开口的第二开口，并且具有小于第一宽度的第二宽度。然后从第一开口内去除含碳材料，并且电绝缘材料形成在第一和第二开口内。电绝缘材料可以基本上填充第一开口，并在第二开口内留下空隙。

30. 发明授权

US07659161B2 Methods of forming storage nodes for a DRAM array 有权
标题翻译：形成DRAM阵列的存储节点的方法
公开(公告)号：US07659161B2
公开(公告)日：2010-02-09
申请号：US11111360
申请日：2005-04-21
申请人： Luan C. Tran , Fred D. Fishburn
发明人： Luan C. Tran , Fred D. Fishburn
IPC分类号： H01L21/00
CPC分类号： H01L27/10888 , H01L27/1052 , H01L27/10814 , H01L27/10855 , H01L27/10885 , H01L27/10894 , H01L27/10897 , H01L27/115 , H01L27/11521 , H01L27/11531 , H01L27/24 , Y10S257/906 , Y10S257/908
摘要： The invention includes memory arrays, and methods which can be utilized for forming memory arrays. A patterned etch stop can be used during memory array fabrication, with the etch stop covering storage node contact locations while leaving openings to bitline contact locations. An insulative material can be formed over the etch stop and over the bitline contact locations, and trenches can be formed through the insulative material. Conductive material can be provided within the trenches to form bitline interconnect lines which are in electrical contact with the bitline contact locations, and which are electrically isolated from the storage node contact locations by the etch stop. In subsequent processing, openings can be formed through the etch stop to the storage node contact locations. Memory storage devices can then be formed within the openings and in electrical contact with the storage node contact locations.
摘要翻译：本发明包括可用于形成存储器阵列的存储器阵列和方法。在存储器阵列制造期间可以使用图案化蚀刻停止件，其中蚀刻停止覆盖存储节点接触位置，同时将开口留在位线接触位置。可以在蚀刻停止点上方和位线接触位置上形成绝缘材料，并且可以通过绝缘材料形成沟槽。可以在沟槽内提供导电材料以形成与位线接触位置电接触的位线互连线，并且通过蚀刻停止件与存储节点接触位置电隔离。在随后的处理中，可以通过蚀刻停止件向存储节点接触位置形成开口。然后可以在开口内形成存储器存储装置，并与存储节点接触位置电接触。

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