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21. 发明申请

US20120187541A1 EPITAXIAL METHODS FOR REDUCING SURFACE DISLOCATION DENSITY IN SEMICONDUCTOR MATERIALS 审中-公开
标题翻译：用于减少半导体材料中表面偏心密度的外延方法
公开(公告)号：US20120187541A1
公开(公告)日：2012-07-26
申请号：US13440749
申请日：2012-04-05
申请人： Chantal Arena , Laurent Clavelier , Marc Rabarot
发明人： Chantal Arena , Laurent Clavelier , Marc Rabarot
IPC分类号： H01L29/20
CPC分类号： H01L29/2003 , H01L21/0242 , H01L21/0243 , H01L21/02458 , H01L21/0254 , H01L21/02639
摘要： The invention provides methods and structures for reducing surface dislocations of a semiconductor layer, and can be employed during the epitaxial growth of semiconductor structures and layers comprising III-nitride materials. Embodiments involve the formation of a plurality of dislocation pit plugs to prevent propagation of dislocations from an underlying layer of material into a following semiconductor layer of material.
摘要翻译：本发明提供了用于减少半导体层的表面位错的方法和结构，并且可以在半导体结构和包含III族氮化物材料的层的外延生长期间使用。实施例涉及形成多个位错坑塞，以防止位错从材料的下层扩散到随后的材料半导体层中。

22. 发明授权

US07993949B2 Heterogeneous substrate including a sacrificial layer, and a method of fabricating it 有权
标题翻译：包括牺牲层的非均相基板及其制造方法
公开(公告)号：US07993949B2
公开(公告)日：2011-08-09
申请号：US12488854
申请日：2009-06-22
申请人： François Perruchot , Bernard Diem , Vincent Larrey , Laurent Clavelier , Emmanuel Defay
发明人： François Perruchot , Bernard Diem , Vincent Larrey , Laurent Clavelier , Emmanuel Defay
IPC分类号： H01L21/02
CPC分类号： B81C1/00595 , B81B2201/0271 , B81C2201/0109 , B81C2201/014
摘要： The invention relates to a method of making a component from a heterogeneous substrate comprising first and second portions in at least one monocrystalline material, and a sacrificial layer constituted by at least one stack of at least one layer of monocrystalline Si situated between two layers of monocrystalline SiGe, the stack being disposed between said first and second portions of monocrystalline material, wherein the method consists in etching said stack by making: e) at least one opening in the first and/or second portion and the first and/or second layer of SiGe so as to reach the layer of Si; and f) eliminating all or part of the layer of Si.
摘要翻译：本发明涉及一种从包含至少一种单晶材料中的第一和第二部分的异质衬底制备组分的方法，以及由位于两层单晶之间的至少一层单晶硅的至少一个叠层构成的牺牲层 SiGe，堆叠设置在单晶材料的第一和第二部分之间，其中该方法包括通过以下步骤蚀刻所述堆叠：e）在第一和/或第二部分中的至少一个开口，以及第一和/ SiGe，以达到Si层; 和f）消除Si的全部或部分层。

23. 发明申请

US20110001184A1 METHOD OF ADJUSTING THE THRESHOLD VOLTAGE OF A TRANSISTOR BY A BURIED TRAPPING LAYER 有权
标题翻译：通过一个BURIED TRAPPING层调整晶体管的阈值电压的方法
公开(公告)号：US20110001184A1
公开(公告)日：2011-01-06
申请号：US12865549
申请日：2009-02-11
申请人： Francois Andrieu , Emmanuel Augendre , Laurent Clavelier , Marek Kostrzewa
发明人： Francois Andrieu , Emmanuel Augendre , Laurent Clavelier , Marek Kostrzewa
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/42348 , H01L21/84 , H01L27/1203 , H01L29/792
摘要： An electronic subassembly and associated method for the production of an electronic subassembly include a semiconductor layer bearing at least a first transistor having an adjustable threshold voltage is joined to an insulator layer and a in which a first trapping zone is formed at a predetermined first depth. The first trapping zone extends at least beneath a channel of the first transistor and includes traps of greater density than the density of traps outside the first trapping zone, in such a way that the semiconductor layer and the first trapping zone are capacitively coupled. The useful information from the first transistor includes the charge transport within this transistor. A second trapping zone can be formed that extends at least beneath a channel of a second transistor that is formed by a second implantation with an energy and/or a dose and/or atoms that differ from those used to form the first trapping zone.
摘要翻译：一种用于生产电子组件的电子组件和相关联的方法，包括至少具有可调阈值电压的第一晶体管的半导体层被连接到绝缘体层，其中在预定的第一深度处形成第一捕集区。第一捕获区至少在第一晶体管的沟道下方延伸，并且包括具有比第一捕获区外的阱的密度更高密度的陷阱，使得半导体层和第一捕获区电容耦合。来自第一晶体管的有用信息包括该晶体管内的电荷传输。可以形成第二捕获区，其至少在通过第二注入形成的第二晶体管的沟道下方延伸，所述第二晶体管具有不同于用于形成第一捕获区的能量和/或剂量和/或原子的能量和/或原子。

24. 发明授权

US07759175B2 Fabrication method of a mixed substrate and use of the substrate for producing circuits 有权
标题翻译：混合基板的制造方法和用于制造电路的基板的使用
公开(公告)号：US07759175B2
公开(公告)日：2010-07-20
申请号：US12071886
申请日：2008-02-27
申请人： Laurent Clavelier , Cyrille Le Royer , Jean-François Damlencourt
发明人： Laurent Clavelier , Cyrille Le Royer , Jean-François Damlencourt
IPC分类号： H01L21/02
CPC分类号： H01L29/1054 , H01L21/02381 , H01L21/02488 , H01L21/02532 , H01L21/02694 , H01L21/823807 , H01L21/823878 , H01L21/84
摘要： The fabrication method of a mixed substrate comprising a tensile strained silicon-on-insulator portion and a compressive strained germanium-on-insulator portion comprises a first step of producing a strained silicon-on-insulator base substrate comprising first and second tensile strained silicon zones. After the base substrate has been produced, the method comprises the successive steps of masking the first tensile strained silicon zone forming the tensile strained silicon-on-insulator portion of the substrate, of performing germanium enrichment treatment of the second tensile strained silicon zone of the base substrate until a compressive strained germanium layer is obtained forming said compressive strained germanium-on-insulator portion of the substrate, and of removing the masking.
摘要翻译：包括拉伸应变绝缘体上的部分和压电应变绝缘体上的部分的混合衬底的制造方法包括：第一步骤，制造在绝缘体上的应变基底衬底，其包括第一和第二拉伸应变硅区。在制造基底衬底之后，该方法包括以下连续步骤：掩蔽形成衬底的拉伸应变绝缘体上的部分的第一拉伸应变硅区，进行锗的第二拉伸应变硅区的锗富集处理从而形成压缩的应变锗层，形成所述压电应变绝缘体上的绝缘体上的部分，并且去除掩模。

25. 发明授权

US07678635B2 Method of producing a transistor 有权
标题翻译：晶体管的制造方法
公开(公告)号：US07678635B2
公开(公告)日：2010-03-16
申请号：US12030672
申请日：2008-02-13
申请人： Laurent Clavelier , Frederic Mayer , Maud Vinet , Simon Deleonibus
发明人： Laurent Clavelier , Frederic Mayer , Maud Vinet , Simon Deleonibus
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L21/28123 , H01L29/66325 , H01L29/66659 , H01L29/7391 , H01L29/78
摘要： Method of producing a transistor, comprising in particular the steps of: producing a first etching mask on a gate layer, one edge of the first mask forming a pattern of the first edge of a gate of the transistor, etching the gate layer according to the first etching mask, first ion implantation in a part of the substrate not covered by the gate layer, trimming the first etching mask over a length equal to a gate length of the transistor, producing a second etching mask on the gate layer, removing the first etching mask etching the gate layer according to the second etching mask, second ion implantation in another part of the substrate.
摘要翻译：制造晶体管的方法，其特别包括以下步骤：在栅极层上制造第一蚀刻掩模，第一掩模的一个边缘形成晶体管的栅极的第一边缘的图案，根据该栅极层蚀刻栅极层第一蚀刻掩模，在未被栅极层覆盖的衬底的一部分中的第一离子注入，在等于晶体管的栅极长度的长度上修整第一蚀刻掩模，在栅极层上产生第二蚀刻掩模，去除第一蚀刻掩模蚀刻掩模根据第二蚀刻掩模蚀刻栅极层，在衬底的另一部分中进行第二离子注入。

26. 发明授权

US07608491B2 Method for manufacturing a SOI substrate associating silicon based areas and GaAs based areas 失效
标题翻译：制造与硅基区域和GaAs基区域相关联的SOI衬底的方法
公开(公告)号：US07608491B2
公开(公告)日：2009-10-27
申请号：US11959924
申请日：2007-12-19
申请人： Laurent Clavelier , Chrystel Deguet
发明人： Laurent Clavelier , Chrystel Deguet
IPC分类号： H01L21/00
CPC分类号： H01L31/184 , C30B19/12 , C30B23/025 , C30B25/18 , C30B29/08 , C30B29/42 , G02B6/12004 , G02B6/43 , H01L21/02381 , H01L21/02433 , H01L21/0245 , H01L21/02543 , H01L21/02546 , H01L21/02625 , H01L21/02639 , H01L21/02647 , H01L21/8258 , H01L21/84 , H01L27/1203 , Y02E10/544
摘要： The invention relates to a method for manufacturing an SOI substrate, associating silicon based areas and areas of GaAs based material at the thin layer of the SOI substrate, the SOI substrate comprising a silicon support supporting successively a layer of dielectric material and a thin layer of silicon. The method comprises the following steps: supply of a SOI substrate comprising a silicon support mismatched by an angle of between 2° and 10° inclusive, the thin silicon based layer being oriented parallel to the plane (001) or (010), or (100) or (110) or (101) or (011) or (111), preservation of at least one area of the thin silicon layer, elimination of at least one non-preserved area of the thin silicon layer until the layer of dielectric material is revealed, opening, in said non-preserved area, of the layer of dielectric material until the silicon support is revealed, growth, from the silicon of the support revealed by said opening and by liquid phase epitaxy or by lateral epitaxy, of mismatched germanium on the layer of dielectric material revealed, growth of GaAs based material from the mismatched germanium obtained in the preceding step.
摘要翻译：本发明涉及一种用于制造SOI衬底的方法，该SOI衬底的薄层将基于硅的区域和GaAs基材料的区域相关联，所述SOI衬底包括依次支撑介电材料层和硅层的薄层硅。该方法包括以下步骤：提供包含不同于2°和10°之间角度的硅载体的SOI衬底，所述薄硅基层平行于平面（001）或（010）或（010）定向，或（ 100）或（110）或（101）或（011）或（111），保存薄硅层的至少一个区域，消除薄硅层的至少一个未保存区域直到电介质层在所述非保存区域中，揭示介质材料层的开口，直到硅支撑体露出，从由所述开口显示的支撑体的硅和通过液相外延或横向外延生长的不匹配的介电材料层上的锗显示出，在前面步骤中获得的来自错配锗的GaAs基材料的生长。

27. 发明授权

US07598145B2 Method for producing Si1-yGey based zones with different contents in Ge on a same substrate by condensation of germanium 有权
标题翻译：通过锗的缩合在同一基板上生产Ge中具有不同含量的Si1-yGey基区的方法
公开(公告)号：US07598145B2
公开(公告)日：2009-10-06
申请号：US11761074
申请日：2007-06-11
申请人： Jean-Francois Damlencourt , Yves Morand , Laurent Clavelier
发明人： Jean-Francois Damlencourt , Yves Morand , Laurent Clavelier
IPC分类号： H01L21/336
CPC分类号： H01L21/32105 , H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L21/84 , H01L27/1203 , H01L29/78684
摘要： A method for producing a microelectronic device comprising a plurality of Si1-yGey based semi-conductor zones (wherein 0
摘要翻译：一种微电子器件的制造方法，该微电子器件包括具有不同锗锗含量的多个Si 1-y Ga y基半导体区（其中0

28. 发明申请

US20090161405A1 DATA STORAGE MEDIUM AND ASSOCIATED METHOD 有权
标题翻译：数据存储介质及相关方法
公开(公告)号：US20090161405A1
公开(公告)日：2009-06-25
申请号：US12338281
申请日：2008-12-18
申请人： Chrystel Deguet , Laurent Clavelier , Franck Fournel , Jean-Sebastien Moulet
发明人： Chrystel Deguet , Laurent Clavelier , Franck Fournel , Jean-Sebastien Moulet
IPC分类号： G11C11/22 , H01L21/02
CPC分类号： G11B9/02 , B82Y10/00 , G11B5/743 , G11B9/1472 , G11B9/149 , Y10T428/115
摘要： A data storage medium includesa carrier substrate having an electrode layer on the surface,and a sensitive material layer extending along the electrode layer, the volume whereof is adapted to be locally modified between two electrical states by the action of a localized electric field.A reference plane extends globally parallel to the sensitive material layerand is configured to pass along it at least one element for application of an electrostatic field in combination with the electrode layer. The storage medium also includes, parallel to the reference plane, a plurality of conductive portions forming part of the electrode layer and separated by at least one electrically insulative zone, the electrically conductive portions having, in at least one direction parallel to the reference plane, a dimension at most equal to 100 nm, where at least some of the conductive portions are electrically interconnected, the conductive portions defining data write/read locations within the sensitive material layer.
摘要翻译：数据存储介质包括在表面上具有电极层的载体衬底和沿着电极层延伸的敏感材料层，其体积适于通过局部电场的作用在两个电气状态之间局部改变。参考平面全局平行于敏感材料层延伸，并被配置为沿着至少一个元件传递静电场与电极层的组合。存储介质还包括平行于参考平面的多个导电部分，其形成电极层的一部分并由至少一个电绝缘区隔开，导电部分在平行于参考平面的至少一个方向上具有，至多等于100nm的尺寸，其中至少一些导电部分电互连，导电部分在敏感材料层内定义数据写入/读取位置。

29. 发明申请

US20090096028A1 Transistor of the I-MOS Type Comprising Two Independent Gates and Method of Using Such a Transistor 有权
标题翻译：包含两个独立门的I-MOS型晶体管和使用这种晶体管的方法
公开(公告)号：US20090096028A1
公开(公告)日：2009-04-16
申请号：US12085866
申请日：2006-12-01
申请人： Cyrille Le Royer , Olivier Faynot , Laurent Clavelier
发明人： Cyrille Le Royer , Olivier Faynot , Laurent Clavelier
IPC分类号： H01L27/088
CPC分类号： H01L27/1057 , H01L29/7391
摘要： The transistor comprises a source (1) and a drain (2) separated by a lightly doped intermediate zone (I). The intermediate zone (I) forms first (3) and second (4) junctions respectively with the source (1) and with the drain (2). The transistor comprises a first gate (5) to generate an electric field in the intermediate zone (I), on the same side as the first junction (3), and a second gate (6) to generate an electric field in the intermediate zone (I), on the same side as the second junction (4).
摘要翻译：晶体管包括由轻掺杂中间区（I）分离的源（1）和漏极（2）。中间区域（I）分别与源极（1）和漏极（2）形成第一（3）和第二（4）结。晶体管包括在与第一结（3）相同的一侧在中间区（I）中产生电场的第一栅极（5）和在中间区域中产生电场的第二栅极（6）（I），与第二结（4）相同。

30. 发明申请

US20070284625A1 METHOD FOR PRODUCING SI1-YGEY BASED ZONES WITH DIFFERENT CONTENTS IN GE ON A SAME SUBSTRATE BY CONDENSATION OF GERMANIUM 有权
标题翻译：通过对锗进行同位素生产在同一基片上的不同含量的SI1-YGEY基区的方法
公开(公告)号：US20070284625A1
公开(公告)日：2007-12-13
申请号：US11761122
申请日：2007-06-11
申请人： Jean-Francois Damlencourt , Yves Morand , Laurent Clavelier
发明人： Jean-Francois Damlencourt , Yves Morand , Laurent Clavelier
IPC分类号： H01L23/58
CPC分类号： H01L21/32105 , H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L21/3083 , H01L21/7624 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/78684 , H01L2924/0002 , H01L2924/00
摘要： The disclosure relates to a method for producing a microelectronic device including a plurality of Si1-yGey based semi-conducting zones (where 0
摘要翻译：本公开涉及一种用于生产包括多个基于Si 1-y基于半导电区（其中0

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