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    • 26. 发明申请
    • Method and device for clearance adjustment for lead-in roller clearance adjustment mechanism
    • 导入辊间隙调整机构间隙调整方法及装置
    • US20070107613A1
    • 2007-05-17
    • US11591476
    • 2006-11-02
    • Hideaki Kuroda
    • Hideaki Kuroda
    • B41F13/54
    • B65H20/02B41F13/03B65H2301/522B65H2511/13B65H2511/22B65H2511/224B65H2801/21B65H2220/01B65H2220/11B65H2220/02
    • A lead-in roller clearance adjustment mechanism includes a pair of lead-in rollers for guiding a web with a clearance therebetween and a clearance adjustment mechanism for adjusting an amount of clearance. The lead-in roller clearance adjustment mechanism further includes motors for driving the clearance adjustment mechanism and potentiometers for detecting output positions of these motors, and adjusts the amount of clearance automatically. A clearance adjustment device for the lead-in roller clearance adjustment mechanism includes a control device for an automated paper threading device and for clearance adjustment between the lead-in rollers, a web thickness of the web being inputted in the control device, the control device controlling the motors in order that the amount of clearance can be set at a predetermined value before threading the web into a lead-in roller unit, and that the amount of clearance can be set at a value corresponding to the inputted web thickness of the web after threading the web into the lead-in roller unit.
    • 导入辊间隙调节机构包括一对用于引导具有间隙的腹板的引入辊和用于调节间隙量的间隙调节机构。 导入辊间隙调节机构还包括用于驱动间隙调节机构的电动机和用于检测这些电动机的输出位置的电位器,并且自动调节间隙量。 用于引入滚轮间隙调节机构的间隙调节装置包括用于自动纸张穿线装置的控制装置,以及引导辊之间的间隙调整,卷筒纸的卷材厚度输入到控制装置中,控制装置 控制电动机,以便在将幅材穿入导入辊单元之前将间隙量设定在预定值,并且间隙量可以被设定为对应于幅材的输入幅材厚度的值 将网状物穿入导入辊单元后。
    • 27. 发明授权
    • Semiconductor device having a selectively deposited conductive layer
    • 具有选择性沉积的导电层的半导体器件
    • US06696351B1
    • 2004-02-24
    • US09056794
    • 1998-04-08
    • Hideaki Kuroda
    • Hideaki Kuroda
    • H01L2170
    • H01L27/10894H01L21/28518H01L27/1052H01L27/10817H01L27/10897H01L28/86
    • A process of production of a semiconductor memory device having a memory array including memory cells and a peripheral circuit on one substrate comprising the process of forming an interlayer insulating layer covering the memory array and peripheral circuit; forming the memory cells; exposing a surface of diffusion regions in the peripheral circuit after forming the memory cells; and forming a covering conductive layer on the exposed region of the diffusion regions in peripheral circuit. A semiconductor memory device produced by such a process has memory area having a good data retention due to a low junction leakage in the diffusion regions of the memory cells, whereas it has a high processing speed peripheral circuit due to a low resistance of the diffusion regions of the peripheral circuit.
    • 一种制造半导体存储器件的方法,所述半导体存储器件具有包括存储单元和在一个衬底上的外围电路的存储器阵列,包括形成覆盖所述存储器阵列和外围电路的层间绝缘层的工艺; 形成记忆单元; 在形成存储单元之后暴露外围电路中的扩散区域的表面; 并且在外围电路的扩散区域的露出区域上形成覆盖导电层。通过这种工艺制造的半导体存储器件由于存储单元的扩散区域中的低结泄漏而具有良好的数据保持性的存储区域, 而由于外围电路的扩散区域的低电阻,它具有高处理速度的外围电路。
    • 29. 发明授权
    • Chip-type piezoelectric resonator and method for adjusting resonance frequency thereof
    • 片式压电谐振器及其谐振频率的调节方法
    • US06215229B1
    • 2001-04-10
    • US09310237
    • 1999-05-12
    • Hideaki KurodaMasaya WajimaRyuhei Yoshida
    • Hideaki KurodaMasaya WajimaRyuhei Yoshida
    • H03H917
    • H03H9/177H03H3/04H03H9/0561H03H9/1035H03H2003/0428
    • A capacitor-included, chip-type piezoelectric resonator allows minute and highly precise adjustment of electrostatic capacitance and the resonance frequency after production of the piezoelectric resonator by laminating a piezoelectric element and dielectric substrates. The resonator includes a piezoelectric substrate laminated with dielectric substrates and external electrodes disposed on the laminate body. A plurality of external electrodes are arranged to extend from the outer major surface of the first dielectric substrate to the outer major surface of the second dielectric substrate along first and second side surfaces disposed opposite to each other. On the outer major surface of the second dielectric substrate, at least one external electrode is divided into first and second electrode portions.
    • 包含电容器的芯片型压电谐振器通过层叠压电元件和电介质基板,能够在制造压电谐振器之后对静电电容和谐振频率进行微调和高度精确的调整。 谐振器包括层叠有电介质基板的压电基板和设置在层叠体上的外部电极。 多个外部电极布置成沿着彼此相对设置的第一和第二侧表面从第一电介质基板的外主表面延伸到第二电介质基板的外主表面。 在第二电介质基板的外主表面上,至少一个外电极被分成第一和第二电极部分。
    • 30. 发明授权
    • Memory analyzing apparatus
    • 内存分析装置
    • US6029260A
    • 2000-02-22
    • US919149
    • 1997-08-28
    • Ken HashizumeNorifumi KobayashiHideaki Kuroda
    • Ken HashizumeNorifumi KobayashiHideaki Kuroda
    • G06F12/16G11C29/00G11C29/44
    • G11C29/44
    • When defective bits of a memory are remedied, the disclosed memory analyzing apparatus can execute remedy analysis of a large capacity memory freely and effectively in a short time. Data are transferred from a defect cell memory (3) provided for a memory tester body (1) to a remedy analyzing apparatus (2) in the sequence suitable for defect remedy. The transferred data are regenerated in address sequence, and the numbers of the defective bits are counted and stored in an X line defect memory (26) and a Y line defect memory (27) at the same time. Further, a line detect flag is raised on the basis of the number of detective bits in the same row and the same column. Further, with respect to the defective bits of a line other than the defect line, the addresses thereof are stored in the bit defect memory (35), and the number of the defect bits is stored in a unit region defect number memory (33) for each defect remedy unit region. A CPU (5) allocates remedy lines to the line defects with a priority, and further processes the allocation analysis of the remedy lines on the basis of the data obtained from the respective memories (26, 27, 33, and 35), so that it is possible to reduce the remedy processing time markedly.
    • 当修复存储器的有缺陷的位时,所公开的存储器分析装置可以在短时间内自由而有效地执行大容量存储器的补救分析。 将数据从适合于缺陷补救的顺序从针对存储器测试器主体(1)的缺陷单元存储器(3)传送到补救分析设备(2)。 传送的数据以地址顺序重新生成,并且有缺陷位的数量被同时计数并存储在X行缺陷存储器(26)和Y行缺陷存储器(27)中。 此外,基于同一行和同一列中的检测位的数量,生成行检测标志。 此外,对于缺陷线以外的线的有缺陷的位,其地址被存储在位缺陷存储器(35)中,并且缺陷位的数量被存储在单位区域缺陷数存储器(33)中, 针对每个缺陷补救单位区域。 CPU(5)以优先级为线路缺陷分配补救线路,并且根据从各个存储器(26,27,33和35)获得的数据进一步处理补救线路的分配分析,使得 可以显着减少补救处理时间。