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    • 1. 发明授权
    • Memory analyzing apparatus
    • 内存分析装置
    • US6029260A
    • 2000-02-22
    • US919149
    • 1997-08-28
    • Ken HashizumeNorifumi KobayashiHideaki Kuroda
    • Ken HashizumeNorifumi KobayashiHideaki Kuroda
    • G06F12/16G11C29/00G11C29/44
    • G11C29/44
    • When defective bits of a memory are remedied, the disclosed memory analyzing apparatus can execute remedy analysis of a large capacity memory freely and effectively in a short time. Data are transferred from a defect cell memory (3) provided for a memory tester body (1) to a remedy analyzing apparatus (2) in the sequence suitable for defect remedy. The transferred data are regenerated in address sequence, and the numbers of the defective bits are counted and stored in an X line defect memory (26) and a Y line defect memory (27) at the same time. Further, a line detect flag is raised on the basis of the number of detective bits in the same row and the same column. Further, with respect to the defective bits of a line other than the defect line, the addresses thereof are stored in the bit defect memory (35), and the number of the defect bits is stored in a unit region defect number memory (33) for each defect remedy unit region. A CPU (5) allocates remedy lines to the line defects with a priority, and further processes the allocation analysis of the remedy lines on the basis of the data obtained from the respective memories (26, 27, 33, and 35), so that it is possible to reduce the remedy processing time markedly.
    • 当修复存储器的有缺陷的位时,所公开的存储器分析装置可以在短时间内自由而有效地执行大容量存储器的补救分析。 将数据从适合于缺陷补救的顺序从针对存储器测试器主体(1)的缺陷单元存储器(3)传送到补救分析设备(2)。 传送的数据以地址顺序重新生成,并且有缺陷位的数量被同时计数并存储在X行缺陷存储器(26)和Y行缺陷存储器(27)中。 此外,基于同一行和同一列中的检测位的数量,生成行检测标志。 此外,对于缺陷线以外的线的有缺陷的位,其地址被存储在位缺陷存储器(35)中,并且缺陷位的数量被存储在单位区域缺陷数存储器(33)中, 针对每个缺陷补救单位区域。 CPU(5)以优先级为线路缺陷分配补救线路,并且根据从各个存储器(26,27,33和35)获得的数据进一步处理补救线路的分配分析,使得 可以显着减少补救处理时间。
    • 4. 发明申请
    • SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE
    • 半导体器件制造方法和半导体器件
    • US20100140617A1
    • 2010-06-10
    • US12629150
    • 2009-12-02
    • Hideaki Kuroda
    • Hideaki Kuroda
    • H01L29/78H01L21/66H01L23/544
    • H01L27/105H01L21/84H01L22/14H01L22/20H01L27/11H01L27/1104H01L27/1116H01L27/1203H01L29/78H01L29/7855
    • A semiconductor device manufacturing method includes the steps of: forming a transistor on a surface side of a silicon layer of a silicon-on-insulator substrate, the silicon-on-insulator substrate being formed by laminating a substrate, an insulating layer, and the silicon layer; forming a first insulating film covering the transistor and a wiring section including a part electrically connected to the transistor on the silicon-on-insulator substrate; measuring a threshold voltage of the transistor through the wiring section; forming a supporting substrate on a surface of the first insulating film with a second insulating film interposed between the supporting substrate and the first insulating film; removing at least a part of the substrate and the insulating layer on a back side of the silicon-on-insulator substrate; and adjusting the threshold voltage of the transistor on a basis of the measured threshold voltage.
    • 半导体器件制造方法包括以下步骤:在绝缘体上硅衬底的硅层的表面侧上形成晶体管,绝缘体上硅衬底通过层叠衬底,绝缘层和 硅层; 形成覆盖晶体管的第一绝缘膜和包括与绝缘体上硅基板上的晶体管电连接的部分的布线部分; 通过所述布线部分测量所述晶体管的阈值电压; 在所述第一绝缘膜的表面上形成支撑衬底,其中所述第二绝缘膜置于所述支撑衬底和所述第一绝缘膜之间; 在绝缘体上硅衬底的背面去除衬底和绝缘层的至少一部分; 以及基于测量的阈值电压来调整晶体管的阈值电压。
    • 6. 发明申请
    • Electroacoustic Transducer
    • 电声传感器
    • US20080218031A1
    • 2008-09-11
    • US12126022
    • 2008-05-23
    • Hideaki KurodaYoshihiro Sonoda
    • Hideaki KurodaYoshihiro Sonoda
    • H04R17/00
    • H04R17/10
    • An electroacoustic transducer having one end portion of a first piezoelectric element and one end portion of a second piezoelectric element fixed to a frame such that the first piezoelectric element and the second piezoelectric element are supported by the frame in an opening of the frame in the cantilever manner. A flexible thin film is bonded to the frame and the first and second piezoelectric elements so that it covers at least a gap between each of the piezoelectric elements and the frame. The other end portions of the piezoelectric elements are free end portions, and face each other with a gap therebetween.
    • 一种电声换能器,其具有第一压电元件的一个端部和固定到框架的第二压电元件的一个端部,使得第一压电元件和第二压电元件由框架支撑在悬臂中的框架的开口中 方式。 柔性薄膜结合到框架和第一和第二压电元件,使得它覆盖每个压电元件和框架之间的至少一个间隙。 压电元件的另一端部是自由端部,并且彼此面对地间隔开。
    • 9. 发明授权
    • Memory element with small threshold voltage variance and high-speed logic element with low power consumption
    • 具有小阈值电压差异的存储元件和低功耗的高速逻辑元件
    • US08362565B2
    • 2013-01-29
    • US12630396
    • 2009-12-03
    • Hideaki Kuroda
    • Hideaki Kuroda
    • H01L29/66
    • H01L21/84H01L27/105H01L27/11H01L27/1116H01L27/12H01L29/78648
    • A semiconductor device includes: a semiconductor layer; an element isolation region formed in the semiconductor layer for separation between a memory element part and a logic element part; first and second field-effect transistors formed in the memory element part and having first and second gate electrodes on a first surface side of the semiconductor layer and a second surface side opposite to the first surface, respectively, and having a source and drain region in common with each other; a third field-effect transistor formed in the logic element part and having a third gate electrode on the second surface side; and first and second insulating films formed on the semiconductor layer to cover the first field-effect transistor and the second and third field-effect transistors, respectively. The first field-effect transistor and the second field-effect transistor are fully-depleted field-effect transistors. The first gate electrode and the second gate electrode are electrically connected.
    • 半导体器件包括:半导体层; 形成在所述半导体层中用于在存储元件部分和逻辑元件部分之间分离的元件隔离区; 第一和第二场效应晶体管形成在存储元件部分中,并且在半导体层的第一表面侧上分别具有第一和第二栅极电极以及与第一表面相对的第二表面侧,并且具有源极和漏极区域 相互共同; 形成在所述逻辑元件部分中并且在所述第二表面侧上具有第三栅电极的第三场效应晶体管; 以及形成在所述半导体层上以分别覆盖所述第一场效应晶体管和所述第二和第三场效应晶体管的第一和第二绝缘膜。 第一场效应晶体管和第二场效应晶体管是完全耗尽的场效应晶体管。 第一栅电极和第二栅极电连接。