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1. 发明授权

US08362565B2 Memory element with small threshold voltage variance and high-speed logic element with low power consumption 有权
标题翻译：具有小阈值电压差异的存储元件和低功耗的高速逻辑元件
公开(公告)号：US08362565B2
公开(公告)日：2013-01-29
申请号：US12630396
申请日：2009-12-03
申请人： Hideaki Kuroda
发明人： Hideaki Kuroda
IPC分类号： H01L29/66
CPC分类号： H01L21/84 , H01L27/105 , H01L27/11 , H01L27/1116 , H01L27/12 , H01L29/78648
摘要： A semiconductor device includes: a semiconductor layer; an element isolation region formed in the semiconductor layer for separation between a memory element part and a logic element part; first and second field-effect transistors formed in the memory element part and having first and second gate electrodes on a first surface side of the semiconductor layer and a second surface side opposite to the first surface, respectively, and having a source and drain region in common with each other; a third field-effect transistor formed in the logic element part and having a third gate electrode on the second surface side; and first and second insulating films formed on the semiconductor layer to cover the first field-effect transistor and the second and third field-effect transistors, respectively. The first field-effect transistor and the second field-effect transistor are fully-depleted field-effect transistors. The first gate electrode and the second gate electrode are electrically connected.
摘要翻译：半导体器件包括：半导体层; 形成在所述半导体层中用于在存储元件部分和逻辑元件部分之间分离的元件隔离区; 第一和第二场效应晶体管形成在存储元件部分中，并且在半导体层的第一表面侧上分别具有第一和第二栅极电极以及与第一表面相对的第二表面侧，并且具有源极和漏极区域相互共同; 形成在所述逻辑元件部分中并且在所述第二表面侧上具有第三栅电极的第三场效应晶体管; 以及形成在所述半导体层上以分别覆盖所述第一场效应晶体管和所述第二和第三场效应晶体管的第一和第二绝缘膜。第一场效应晶体管和第二场效应晶体管是完全耗尽的场效应晶体管。第一栅电极和第二栅极电连接。

2. 发明授权

US08349840B2 Piperazine-substituted benzothiophenes for treatment of mental disorders 有权
公开(公告)号：US08349840B2
公开(公告)日：2013-01-08
申请号：US12970690
申请日：2010-12-16
申请人： Hiroshi Yamashita , Nobuaki Ito , Shin Miyamura , Kunio Oshima , Jun Matsubara , Hideaki Kuroda , Haruka Takahashi , Satoshi Shimizu , Tatsuyoshi Tanaka
发明人： Hiroshi Yamashita , Nobuaki Ito , Shin Miyamura , Kunio Oshima , Jun Matsubara , Hideaki Kuroda , Haruka Takahashi , Satoshi Shimizu , Tatsuyoshi Tanaka
IPC分类号： A61K31/496
CPC分类号： A61K31/496 , C07D405/12 , C07D409/12 , C07D409/14
摘要： The present invention provides a heterocyclic compound represented by the general formula (1): The compound of the present invention has a wide treatment spectrum for mental disorders including central nervous system disorders, no side effects and high safety.

3. 发明授权

US06362561B1 Piezoelectric vibration device and piezoelectric resonance component 有权
标题翻译：压电振动装置和压电谐振元件
公开(公告)号：US06362561B1
公开(公告)日：2002-03-26
申请号：US09501086
申请日：2000-02-09
申请人： Hideaki Kuroda , Ryuhei Yoshida
发明人： Hideaki Kuroda , Ryuhei Yoshida
IPC分类号： H01L4104
CPC分类号： H03H9/177 , H03H9/0547 , H03H9/1014
摘要： An energy-trapping piezoelectric vibration device generates a thickness shear mode and includes an elongated piezoelectric element having first and second longitudinally opposed ends, top and bottom surfaces provided between the first and second ends such that the top and bottom surfaces oppose each other, and beveled surfaces disposed at a vicinity of the first and second ends such that the thickness of the piezoelectric element gradually decreases towards the first and second ends, respectively. First and second vibration electrodes are disposed on the top surface and the bottom surface of the piezoelectric element, respectively. The first and second vibration electrodes are located at an approximate middle portion of the piezoelectric element so as to oppose each other with the piezoelectric element disposed therebetween, to define opposing portions which constitute a vibrator. A roughness of the beveled surfaces is greater than a roughness of a flat portion of the top and bottom surfaces of the piezoelectric substrate disposed beneath the vibration electrodes.
摘要翻译：能量捕获压电振动装置产生厚度剪切模式，并且包括具有第一和第二纵向相对端的细长压电元件，顶表面和底表面设置在第一和第二端之间，使得顶表面和底表面彼此相对，并且倾斜表面设置在第一端和第二端附近，使得压电元件的厚度分别朝向第一端和第二端逐渐减小。第一和第二振动电极分别设置在压电元件的顶表面和底表面上。第一和第二振动电极位于压电元件的大致中间部分处以彼此相对的压电元件设置在它们之间，以限定构成振动器的相对部分。倾斜表面的粗糙度大于设置在振动电极下方的压电基板的顶表面和底表面的平坦部分的粗糙度。

4. 发明授权

US6147383A LDD buried channel field effect semiconductor device and manufacturing method 失效
标题翻译： LDD掩埋沟道场效应半导体器件及其制造方法
公开(公告)号：US6147383A
公开(公告)日：2000-11-14
申请号：US611188
申请日：1996-03-05
申请人： Hideaki Kuroda
发明人： Hideaki Kuroda
IPC分类号： H01L21/265 , H01L21/336 , H01L29/10 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062
CPC分类号： H01L29/6659 , H01L29/1083 , H01L29/7833 , H01L29/7838 , H01L21/26586
摘要： An LDD-structured field-effect semiconductor device that can eliminate fluctuations in the threshold voltage caused by variations in the position of higher-density diffusion layers, thereby suppressing variations in the threshold voltage to a lower level. The junction depth of each of the lower-density diffusion layers in contact with a substrate is greater than the depth of a depletion layer at the place corresponding to a portion of the channel region contacting the source region. This prevents a change in the positional relationship between diffusion layers serving as, what are referred to as "pocket layers", and the depletion layer adjacent to the source, even though the position of the higher-density diffusion layers is varied in the longitudinal direction of the channel due to variations in the width of a spacer. Thus, there are no fluctuations in the quantity of impurities contained in the pocket layers within the depletion layer adjacent to the source, which would otherwise influence the threshold voltage.
摘要翻译：一种LDD结构的场效应半导体器件，其可以消除由高密度扩散层的位置变化引起的阈值电压的波动，从而将阈值电压的变化抑制到较低的水平。与衬底接触的每个较低密度扩散层的结深度大于在与源区域接触的沟道区的一部分相对应的位置处的耗尽层的深度。这防止了即使高密度扩散层的位置在纵向方向上变化，即用作“袋层”的扩散层和与源极相邻的耗尽层之间的位置关系发生变化由于间隔物的宽度的变化引起的通道。因此，与源极相邻的耗尽层内的杂质层中所含杂质的量不会有波动，否则会影响阈值电压。

5. 发明授权

US6093950A Semiconductor device having various threshold voltages and manufacturing same 失效
标题翻译：具有各种阈值电压并制造相同的半导体装置
公开(公告)号：US6093950A
公开(公告)日：2000-07-25
申请号：US231459
申请日：1999-01-14
申请人： Hideaki Kuroda
发明人： Hideaki Kuroda
IPC分类号： H01L27/088 , G11C11/407 , H01L21/265 , H01L21/8234 , H01L21/8238 , H01L27/092 , H01L29/76
CPC分类号： H01L27/088 , H01L21/823412 , H01L21/823807 , H01L27/0922
摘要： An impurity for adjusting a threshold voltage is ion-implanted using, as masks, a resist for forming P.sup.- -type diffusion layers, a resist for forming N.sup.+ -type diffusion layers and N-type diffusion layers and a resist for forming P.sup.+ -type diffusion layers and N-type diffusion layers. For this reason, a semiconductor device including first to third N-channel transistors and first and second P-channel transistors, all of which respectively have different threshold voltages, can be manufactured without using an additional resist except for the above resists. Therefore, an operating margin at a low voltage can be increased and data retention characteristics can be improved in a memory without causing an increase in cost, an increase in power consumption and the like.
摘要翻译：使用用于形成P型扩散层的抗蚀剂，用于形成N +型扩散层和N型扩散层的抗蚀剂和用于形成P +型扩散层的抗蚀剂，使用用于调整阈值电压的杂质作为掩模扩散层和N型扩散层。为此，除了上述抗蚀剂之外，可以制造包括第一至第三N沟道晶体管和第一和第二P沟道晶体管的半导体器件，所有这些都分别具有不同的阈值电压。因此，可以提高低电压的运行裕度，并且可以在存储器中提高数据保持特性，而不会导致成本的增加，功耗的增加等。

6. 发明授权

US6001698A MOS transistor and fabrication process for the same 失效
标题翻译： MOS晶体管和制造工艺相同
公开(公告)号：US6001698A
公开(公告)日：1999-12-14
申请号：US842655
申请日：1997-04-15
申请人： Hideaki Kuroda
发明人： Hideaki Kuroda
IPC分类号： H01L21/265 , H01L21/28 , H01L21/336 , H01L21/768 , H01L21/8238 , H01L23/485 , H01L27/092 , H01L29/423 , H01L29/49 , H01L29/78
CPC分类号： H01L29/6659 , H01L21/28114 , H01L21/76877 , H01L21/823807 , H01L23/485 , H01L29/42376 , H01L29/4941 , H01L29/495 , H01L29/66537 , H01L29/66545 , H01L2924/0002
摘要： Disclosed is a MOS transistor and a fabrication process for the MOS transistor. Each gate electrode pattern made of silicon is formed on a gate oxide film formed on a silicon base body. An impurity is doped in the silicon base body using the gate electrode patterns as a mask, followed by activation of the impurity thus doped, to form diffusion layers in a surface layer of the silicon base body. An interlayer insulating film is formed in such a manner as to cover the gate electrode patterns. An upper portion of the interlayer insulating film is removed to expose the upper portion of each gate electrode pattern. The gate electrode pattern thus exposed is removed by selective etching. After that, a recessed portion formed by removal of each gate electrode pattern is embedded with a metal material, to form a CMOS transistor.
摘要翻译：公开了用于MOS晶体管的MOS晶体管和制造工艺。在硅基体上形成的栅极氧化膜上形成由硅构成的各栅电极图案。使用栅极电极图案作为掩模在硅基体中掺杂杂质，然后激活所掺杂的杂质，以在硅基体的表面层中形成扩散层。以覆盖栅电极图案的方式形成层间绝缘膜。去除层间绝缘膜的上部以露出每个栅电极图案的上部。通过选择性蚀刻去除由此露出的栅极电极图案。之后，通过去除每个栅极电极图案而形成的凹部嵌入金属材料，以形成CMOS晶体管。

7. 发明授权

US5986312A Field effect semiconductor device having improved connections 失效
标题翻译：场效应半导体器件具有改进的连接
公开(公告)号：US5986312A
公开(公告)日：1999-11-16
申请号：US922876
申请日：1997-09-03
申请人： Hideaki Kuroda
发明人： Hideaki Kuroda
IPC分类号： H01L21/28 , H01L21/285 , H01L21/336 , H01L21/768 , H01L29/10 , H01L29/45 , H01L29/49 , H01L29/78
CPC分类号： H01L21/76895 , H01L29/1083 , H01L29/456 , H01L29/4933 , H01L29/6659 , H01L29/7838
摘要： In a field effect semiconductor device, in order to increase the operation speed and to make the device finer by lowering the sheet resistance, and to lower the production cost by reducing the process steps, the diffusion layer 17 is surrounded by SiO.sub.2 films 16 and 34 covering the tungsten polycide layer 35 provided as the gate electrode and by the SiO.sub.2 film 12 in the device isolating region, and the titanium polycide layer 44 is brought into contact with the entire surface of the diffusion layer 17 while being extended on the SiO.sub.2 films 12 an d 16. Accordingly, a large allowance in aligning the contact hole 25 with respect to the titanium polycide layer 44 can be assured to make the contact compensation ion implantation unnecessary.
摘要翻译：在场效应半导体装置中，为了提高操作速度，通过降低薄层电阻使装置更细，通过减少工艺步骤降低制造成本，扩散层17被SiO 2膜16和34包围覆盖设置为栅电极的多晶硅化钨层35和器件隔离区域中的SiO 2膜12，并且多晶硅化物层44与扩散层17的整个表面接触，同时在SiO 2膜12上延伸因此，可以确保相对于多晶硅化钛层44对准接触孔25的大的余量使得不需要接触补偿离子注入。

8. 发明授权

US5580805A Semiconductor device having various threshold voltages and manufacturing same 失效
标题翻译：具有各种阈值电压并制造相同的半导体器件
公开(公告)号：US5580805A
公开(公告)日：1996-12-03
申请号：US296038
申请日：1994-08-25
申请人： Hideaki Kuroda
发明人： Hideaki Kuroda
IPC分类号： H01L27/088 , G11C11/407 , H01L21/265 , H01L21/8234 , H01L21/8238 , H01L27/092
CPC分类号： H01L27/088 , H01L21/823412 , H01L21/823807 , H01L27/0922
摘要： An impurity for adjusting a threshold voltage is ion-implanted using, as masks, a resist for forming P.sup.- -type diffusion layers, a resist for forming N.sup.+ -type diffusion layers and N-type diffusion layers and a resist for forming P.sup.+ -type diffusion layers and N-type diffusion layers. For this reason, a semiconductor device including first to third N-channel transistors and first and second P-channel transistors, all of which respectively have different threshold voltages, can be manufactured without using an additional resist except for the above resists. Therefore, an operating margin at a low voltage can be improved and data retention characteristics can be improved in a memory without causing an increase in cost, an increase in power consumption and the like.
摘要翻译：使用用于形成P型扩散层的抗蚀剂，用于形成N +型扩散层和N型扩散层的抗蚀剂和用于形成P +型扩散层的抗蚀剂，使用用于调整阈值电压的杂质作为掩模扩散层和N型扩散层。为此，除了上述抗蚀剂之外，可以制造包括第一至第三N沟道晶体管和第一和第二P沟道晶体管的半导体器件，所有这些都分别具有不同的阈值电压。因此，可以提高低电压的工作裕度，并且可以在存储器中提高数据保持特性，而不会导致成本的增加，功耗的增加等。

9. 发明授权

US5459093A Method for forming dummy pattern in a semiconductor device 失效
标题翻译：在半导体器件中形成虚拟图案的方法
公开(公告)号：US5459093A
公开(公告)日：1995-10-17
申请号：US214141
申请日：1994-03-17
申请人： Hideaki Kuroda , Keiichi Ono
发明人： Hideaki Kuroda , Keiichi Ono
IPC分类号： H01L21/3205 , G06F17/50 , H01L21/82 , H01L23/52 , H01L27/02 , H01L21/70 , H01L27/00
CPC分类号： H01L27/0207 , Y10S438/926
摘要： Method of forming a dummy pattern without inducing crosstalk between conductive interconnects which would normally be caused by increase in capacitance between the interconnects. Also, absolute steps of devices are made uniform. Furthermore, the flatness of devices is improved. In a device having a multilayer aluminum metallization structure, let Chip be data about a region on which a dummy pattern should be defined. Let I.sub.Mi be data about a region occupied by an aluminum interconnect pattern on the ith layer. Let I.sub.Di be data about a dummy pattern on the ith layer, or data sought for. Let (Chip-I.sub.Mi).sub.D be data about the dummy pattern region obtained by decrement of data. The data (Chip-I.sub.Mi).sub.D about the dummy pattern region is ANDed with data I.sub.M(i+1) about the conduction pattern on the (i+1)th layer or with data I.sub.D(i+1) about the dummy pattern. Thus, data I.sub.Di about the dummy pattern is created. The dummy pattern on the ith layer is created, based on the created data I.sub.Di.
摘要翻译：形成虚设图案的方法，而不会引起通常由互连之间的电容增加引起的导电互连之间的串扰。此外，设备的绝对步骤均匀。此外，设备的平坦度得到改善。在具有多层铝金属化结构的器件中，令芯片是关于其上应限定虚拟图案的区域的数据。使IMi是关于第i层上的铝互连图案所占据的区域的数据。让IDi是关于第i层上的虚拟模式或寻求的数据的数据。令（Chip-IMi）D是通过数据递减获得的虚拟图形区域的数据。关于虚拟图案区域的数据（Chip-IMi）D与关于第（i + 1）层上的导电图案的数据IM（i + 1）或关于虚拟图案的数据ID（i + 1）进行AND。因此，创建关于虚拟图案的数据IDi。基于创建的数据IDi创建第i层上的虚拟模式。

10. 发明授权

US5346843A Method of manufacturing a semiconductor device having a memory cell and peripheral circuit including forming a first electrode for the capacitor 失效
标题翻译：制造具有存储单元和外围电路的半导体器件的方法包括形成电容器的第一电极
公开(公告)号：US5346843A
公开(公告)日：1994-09-13
申请号：US871705
申请日：1992-04-21
申请人： Hideaki Kuroda
发明人： Hideaki Kuroda
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/105 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10808 , H01L27/105 , Y10S438/97
摘要： According to this invention, a conductive film for forming a plate electrode of a capacitor constituting a memory cell is patterned in only a memory cell region at first. After the conductive film in a peripheral circuit region is used as a stopper for wet-etching a low-melting insulating film of the peripheral circuit region, the conductive film is patterned using the same mask as the low-melting insulating film or the low-melting insulating film itself as a mask. For this reason, an SiN film formed by a low pressure CVD method is not used as a stopper, and an additional lithographic step is not required. Therefore, while a memory cell region is planarized and the step of the peripheral circuit region is reduced, data retaining characteristics can be improved without increasing the number of steps.
摘要翻译：根据本发明，用于形成构成存储单元的电容器的电极板的导电膜首先在存储单元区域中被图案化。在外围电路区域中的导电膜用作湿式蚀刻外围电路区域的低熔点绝缘膜的阻挡层之后，使用与低熔点绝缘膜或低熔点绝缘膜相同的掩模对导电膜进行构图，熔化绝缘膜本身作为掩模。因此，通过低压CVD法形成的SiN膜不能用作阻挡体，不需要附加的光刻工序。因此，当存储单元区域被平坦化并且外围电路区域的步骤减小时，可以在不增加步数的情况下提高数据保持特性。

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