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21. 发明授权

US6014417A On-chip phase step generator for a digital phase locked loop 失效
标题翻译：用于数字锁相环的片上相位发生器
公开(公告)号：US6014417A
公开(公告)日：2000-01-11
申请号：US920498
申请日：1997-08-29
申请人： Wong Hee , Gabriel Li
发明人： Wong Hee , Gabriel Li
IPC分类号： H03L7/08 , H03L7/089 , H03L7/099 , H03D3/24 , H04L7/00 , H04L25/36 , H04L25/40
CPC分类号： H03L7/08 , H03L7/089 , H03L7/0995
摘要： A method and circuitry are provided for generating a phase shift in the recovered clock in a high speed, digital data recovery phase locked loop. Since phase step injection can be done in a closed loop environment, the dynamic of the real time phase step response of the PLL can be analyzed using a phase meter. In an open-loop environment, the output of the phase meter with a step response of 60 degree phase shift tracks closely with the internal RC response at the multi-phase outputs of the PLL's phase-to-frequency converter. Since the register and capacitor values vary with process, the scheme for verifying the relative accuracy of the PLL's internal filters can be verified without actually probing the device.
摘要翻译：提供了一种方法和电路，用于在高速数字数据恢复锁相环中产生恢复的时钟中的相移。由于相位步进注入可以在闭环环境中进行，所以可以使用相位计来分析PLL的实时相位阶跃响应的动态。在开环环境中，具有60度相移的阶跃响应的相位计的输出与PLL的相 - 相变频器的多相输出端的内部RC响应密切相关。由于寄存器和电容值随过程而变化，所以可以验证PLL内部滤波器相对精度的方案，而无需实际探测器件。

22. 发明授权

US5477181A Programmable multiphase clock divider 失效
标题翻译：可编程多相时钟分频器
公开(公告)号：US5477181A
公开(公告)日：1995-12-19
申请号：US322709
申请日：1994-10-13
申请人： Gabriel Li , Wong Hee
发明人： Gabriel Li , Wong Hee
IPC分类号： H03K5/00 , H03K5/15 , H03L7/099
CPC分类号： H03K5/15066 , H03K5/00006 , H03K5/1502 , H03L7/0991
摘要： A programmable multiphase clock divider for selectively frequency dividing a multiphase input clock to provide a lower-frequency, self-aligned, multiphase output clock includes a counter, combinational logic circuitry, a multiphase signal generator and a multiplexor. With the counter serving as the sole frequency divider element, multiple phase-aligned clock phases are generated which are then programmably multiplexed to provide the desired frequency-divided, self-aligned clock phases. The counter, in response to a preset signal and an input clock phase, generates a multibit count signal, one bit of which forms the first output clock phase. The combinational logic circuitry receives a programming signal for decoding the multibit count signal to generate the counter preset signal and an output control signal. The multiphase signal generator successively latches the first output clock phase with the aforementioned input clock phase and additional input clock phases to generate a number of synchronous, intermediate clock phases. The multiplexor, in response to the output control signal, multiplexes the intermediate clock phases to provide further output clock phases. All of the output clock phases are phase-aligned with one another and are at a lower frequency than that of the input clock phase. Multiple ones of such clock dividers can be programmed to frequency divide by selected prime numbers and cascaded to achieve virtually any desired frequency division ratio while maintaining self-aligned output clock phases.
摘要翻译：一种可编程多相时钟分频器，用于选择性地分频多相输入时钟以提供低频，自对准的多相输出时钟，包括计数器，组合逻辑电路，多相信号发生器和多路复用器。利用计数器作为唯一的分频器元件，产生多个相位对准的时钟相位，然后可编程地复用多个相位对准的时钟相位以提供期望的分频，自对准时钟相位。计数器响应于预置信号和输入时钟相位，产生一个多位计数信号，其中一位形成第一输出时钟相位。组合逻辑电路接收用于解码多位计数信号的编程信号以产生计数器预置信号和输出控制信号。多相信号发生器以上述输入时钟相位和附加的输入时钟相位来连续地锁存第一输出时钟相位，以产生多个同步的中间时钟相位。多路复用器响应于输出控制信号复用中间时钟相位以提供进一步的输出时钟相位。所有输出时钟相位彼此相位对准，频率低于输入时钟相位的频率。多个这样的时钟分频器可以被编程为对所选择的素数进行分频并级联以实现几乎任何期望的分频比，同时保持自对准的输出时钟相位。

23. 发明授权

US08290109B2 Circuit, system and method for multiplexing signals with reduced jitter 有权
标题翻译：具有减少抖动的信号复用的电路，系统和方法
公开(公告)号：US08290109B2
公开(公告)日：2012-10-16
申请号：US13038028
申请日：2011-03-01
申请人： Gabriel Li
发明人： Gabriel Li
IPC分类号： H03D3/24
CPC分类号： H04J3/047 , H03K17/002 , H03K19/1737
摘要： An apparatus having a plurality of power supply domains and a plurality of logic components. Each of the plurality of logic components residing within a different one of the plurality of power supply domains. Each of the plurality of logic components is configured to operate with a corresponding clock signal within a respective one of the plurality of power supply domains.
摘要翻译：一种具有多个电源域和多个逻辑部件的装置。多个逻辑组件中的每一个驻留在多个电源域中的不同的一个中。所述多个逻辑部件中的每一个被配置为与所述多个电源域中的相应一个中的对应的时钟信号一起操作。

24. 发明授权

US07330078B1 Apparatus and method for limiting the overshoot and undershoot when turning on the spread spectrum of a reference signal 失效
标题翻译：当开启参考信号的扩展频谱时，限制过冲和下冲的装置和方法
公开(公告)号：US07330078B1
公开(公告)日：2008-02-12
申请号：US11300718
申请日：2005-12-13
申请人： Gabriel Li , Dusan Vecera
发明人： Gabriel Li , Dusan Vecera
IPC分类号： H03L7/06
CPC分类号： H03L7/18
摘要： Disclosed is a circuit, comprising an input spread spectrum enable signal, a crystal oscillator, a first, second and third sampling flip-flop clocked by the crystal oscillator, configured to sample the input spread spectrum enable signal, and a plurality of control output signals derived from or provided directly from the sampling flip-flops. A method of operating the circuit is further described.
摘要翻译：公开了一种电路，包括输入扩频使能信号，晶体振荡器，由晶体振荡器定时的第一，第二和第三采样触发器，被配置为对输入扩频使能信号进行采样，以及多个控制输出信号来自或直接从采样触发器提供。进一步描述操作电路的方法。

25. 发明申请

US20060224910A1 Circuit and method for monitoring the status of a clock signal 有权
标题翻译：用于监视时钟信号状态的电路和方法
公开(公告)号：US20060224910A1
公开(公告)日：2006-10-05
申请号：US11097527
申请日：2005-03-31
申请人： Gabriel Li , Greg Richmond , Sangeeta Raman
发明人： Gabriel Li , Greg Richmond , Sangeeta Raman
IPC分类号： G06F1/00
CPC分类号： H03K5/26 , G01R23/005 , G06F1/12 , H03K5/19
摘要： A circuit and method are provided herein for monitoring the status of a clock signal. In general, the method may include supplying a pair of clock signals to a clock monitor circuit, which is configured for monitoring a status of one clock signal relative to the other. The status indicates whether the frequency of the one clock signal is faster, slower or substantially equal to the frequency of the other clock signal. Once determined, the status may be stored as a bit pattern within a status register, which is operatively coupled to the clock monitor circuit. This enables the status to be read by detecting a logic state of one or more bits within the status register.
摘要翻译：本文提供了一种用于监视时钟信号的状态的电路和方法。通常，该方法可以包括将一对时钟信号提供给时钟监控电路，时钟监视电路被配置为监视相对于另一个时钟信号的一个时钟信号的状态。该状态指示一个时钟信号的频率是否比其他时钟信号的频率更快，更慢或基本上等于其他时钟信号的频率。一旦确定，状态可以作为位模式存储在状态寄存器内，状态寄存器可操作地耦合到时钟监视器电路。这样可以通过检测状态寄存器中的一个或多个位的逻辑状态来读取状态。

26. 发明授权

US06944691B1 Architecture that converts a half-duplex bus to a full-duplex bus while keeping the bandwidth of the bus constant 有权
标题翻译：将半双工总线转换为全双工总线，同时保持总线带宽恒定的架构
公开(公告)号：US06944691B1
公开(公告)日：2005-09-13
申请号：US09915794
申请日：2001-07-26
申请人： Gabriel Li , Edward L. Grivna
发明人： Gabriel Li , Edward L. Grivna
IPC分类号： G06F13/42
CPC分类号： G06F13/4009
摘要： An architecture comprising a first circuit, a second circuit, and one or more pairs of communication channels. The first circuit may be configured to transmit one or more first serial streams in response to a plurality of first source data streams and recover a plurality of second source data streams from one or more second serial streams. The second circuit may be configured to transmit the one or more second serial streams in response to the plurality of second source data streams and recover the plurality of first source data streams in response to the one or more first serial streams. The first circuit and the second circuit may be coupled by the one or more pairs of communication channels. The first and second circuits may be configured to transmit simultaneously.
摘要翻译：一种包括第一电路，第二电路和一对或多对通信信道的架构。第一电路可以被配置为响应于多个第一源数据流传输一个或多个第一串行流，并且从一个或多个第二串行流恢复多个第二源数据流。第二电路可以被配置为响应于多个第二源数据流来发送一个或多个第二串行流，并响应于一个或多个第一串行流恢复多个第一源数据流。第一电路和第二电路可以由一对或多对通信信道耦合。第一和第二电路可以被配置为同时传输。

27. 发明授权

US06369636B1 Method, architecture and circuit for selecting, calibrating and monitoring circuits 失效
标题翻译：选择，校准和监控电路的方法，架构和电路
公开(公告)号：US06369636B1
公开(公告)日：2002-04-09
申请号：US09468171
申请日：1999-12-21
申请人： Gabriel Li
发明人： Gabriel Li
IPC分类号： H03K1776
CPC分类号： G01R31/31853 , G01R31/318525 , G11C2029/5002
摘要： A circuit including a plurality of first calibration circuits, a second circuit and a third circuit. The plurality of calibration circuits may each be configured to present a calibration signal. The second circuit may be configured to select one of the calibration signals in response to a plurality of configuration signals. The third circuit may be configured to generate a control signal in response to (i) a reference signal and (ii) the selected calibration signal.
摘要翻译：一种包括多个第一校准电路，第二电路和第三电路的电路。多个校准电路可以各自被配置为呈现校准信号。第二电路可以被配置为响应于多个配置信号来选择一个校准信号。第三电路可以被配置为响应于（i）参考信号和（ii）所选择的校准信号而产生控制信号。

28. 发明授权

US06321003B1 Tunable semiconductor laser system 有权
标题翻译：可调谐半导体激光系统
公开(公告)号：US06321003B1
公开(公告)日：2001-11-20
申请号：US09686129
申请日：2000-10-10
申请人： Peter Kner , Gabriel Li , Philip Worland , Rang-Chen Yu , Wupen Yuen
发明人： Peter Kner , Gabriel Li , Philip Worland , Rang-Chen Yu , Wupen Yuen
IPC分类号： G02B628
CPC分类号： H01S5/06804 , H01L2224/48091 , H01L2924/16195 , H01S5/0078 , H01S5/02248 , H01S5/0687 , H01S5/18366 , H01L2924/00014
摘要： A multiplexer for a wavelength division multiplexed optical communication system includes an optical circulator with at least first, second, third and fourth circulator ports. An optical fiber with a first optical transmission path is coupled to the first circulator port and carries a wavelength division multiplexed optical signal that includes signals 1−n. A second optical transmission path is in optical communication with the second circulator port. A first laser is coupled to the second optical transmission path. The first laser reflects the 1−n signals and adds a signal n+1. A control loop is coupled to the first laser. In response to a detected change in temperature the control loop sends a signal to adjust a voltage or current supplied to the first laser and provide a controlled frequency and power of an output beam. A third optical transmission path is in optical communication with the third circulator port and transmits the signals 1−n and the signals n+1 that are received from the optical circulator. A fourth optical transmission path is in optical communication with the fourth optical circulator port. The fourth optical transmission path is positioned after the second optical transmission path and before the third optical transmission path. A first optoelectronic device is coupled to the fourth optical transmission path.
摘要翻译：用于波分复用光通信系统的多路复用器包括具有至少第一，第二，第三和第四循环端口的光循环器。具有第一光传输路径的光纤耦合到第一循环端口，并携带包括信号1-n的波分复用光信号。第二光传输路径与第二环行器端口光通信。第一激光器耦合到第二光传输路径。第一激光器反射1-n个信号并加上信号n + 1。控制回路耦合到第一激光器。响应于检测到的温度变化，控制回路发送信号以调节提供给第一激光器的电压或电流，并提供输出光束的受控频率和功率。第三光传输路径与第三环行器端口光通信，并发送从光环行器接收的信号1-n和信号n + 1。第四光传输路径与第四光循环器端口光通信。第四光传输路径位于第二光传输路径之后且位于第三光传输路径之前。第一光电子器件耦合到第四光传输路径。

29. 发明授权

US5652533A Circuit for generating sampling signals at closely spaced time intervals 失效
标题翻译：用于以紧密间隔的时间间隔产生采样信号的电路
公开(公告)号：US5652533A
公开(公告)日：1997-07-29
申请号：US545560
申请日：1995-10-19
申请人： Hee Wong , Gabriel Li
发明人： Hee Wong , Gabriel Li
IPC分类号： H03K5/15 , H03K5/22
CPC分类号： H03K5/15073
摘要： An electronic circuit suitable for sampling an incoming data bit stream in order to recover the information contained in the data stream contains an input section, a reference section, and a comparing section. The input section produces a ramp signal that switches between a first endpoint voltage and a second endpoint voltage in a periodic manner. The reference section furnishes a plurality of reference voltages between the two endpoint voltages. The comparing section compares the ramp signal to the reference voltages to produce corresponding sampling signals. Each sampling signal makes a first voltage transition as the ramp signal passes a corresponding reference voltage in going from the second endpoint voltage to the first endpoint voltage. Accordingly, the first transitions of the sampling signals occur in groups, each group being spread out in time during part of a period of the ramp signal. A data sampling portion of the circuit utilizes the sampling signals to sample the input data bit stream.
摘要翻译：适于对进入的数据比特流进行采样以便恢复包含在数据流中的信息的电子电路包含输入部分，参考部分和比较部分。输入部分产生以周期性方式在第一端点电压和第二端点电压之间切换的斜坡信号。参考部分在两个端点电压之间提供多个参考电压。比较部分将斜坡信号与参考电压进行比较，以产生相应的采样信号。当斜坡信号从第二端点电压进入第一端点电压时，每个采样信号进行第一电压转换。因此，采样信号的第一跃迁以组为单位发生，每个组在斜坡信号的一段时间的一部分期间在时间上展开。电路的数据采样部分利用采样信号对输入数据位流进行采样。

30. 发明授权

US07876133B1 Output buffer circuit 有权
标题翻译：输出缓冲电路
公开(公告)号：US07876133B1
公开(公告)日：2011-01-25
申请号：US11904901
申请日：2007-09-27
申请人： Alan McLaughlin , Gabriel Li
发明人： Alan McLaughlin , Gabriel Li
IPC分类号： H03B1/00 , H03K3/00
CPC分类号： H03K19/018521
摘要： An output driver circuit can include at least a first driver transistor having a source-drain path coupled between a first power supply node and an output node. A first variable current supply can generate a current having at least one component that is inversely proportional to a power supply voltage. A first driver switch element can be coupled in series with the first variable current supply between a gate of the at least first driver transistor and a second power supply node.
摘要翻译：输出驱动器电路可以包括至少第一驱动器晶体管，其具有耦合在第一电源节点和输出节点之间的源极 - 漏极路径。第一可变电流源可以产生具有与电源电压成反比的至少一个分量的电流。第一驱动器开关元件可以与至少第一驱动器晶体管的栅极和第二电源节点之间的第一可变电流源串联耦合。

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