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21. 发明授权

US08193580B2 Shielded gate trench MOSFET device and fabrication 有权
标题翻译：屏蔽栅沟槽MOSFET器件和制造
公开(公告)号：US08193580B2
公开(公告)日：2012-06-05
申请号：US12583191
申请日：2009-08-14
申请人： John Chen , Il Kwan Lee , Hong Chang , Wenjun Li , Anup Bhalla , Hamza Yilmaz
发明人： John Chen , Il Kwan Lee , Hong Chang , Wenjun Li , Anup Bhalla , Hamza Yilmaz
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/42372 , H01L29/4238 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A semiconductor device embodiment includes a substrate, an active gate trench in the substrate, and an asymmetric trench in the substrate. The asymmetric trench has a first trench wall and a second trench wall, the first trench wall is lined with oxide having a first thickness, and the second trench wall is lined with oxide having a second thickness that is different from the first thickness. Another semiconductor device embodiment includes a substrate, an active gate trench in the substrate; and a source polysilicon pickup trench in the substrate. The source polysilicon pickup trench includes a polysilicon electrode, and top surface of the polysilicon electrode is below a bottom of a body region. Another semiconductor device includes a substrate, an active gate trench in the substrate, the active gate trench has a first top gate electrode and a first bottom source electrode, and a gate runner trench comprising a second top gate electrode and a second bottom source electrode. The second top gate electrode is narrower than the second bottom source electrode.
摘要翻译：半导体器件实施例包括衬底，衬底中的有源栅极沟槽和衬底中的不对称沟槽。非对称沟槽具有第一沟槽壁和第二沟槽壁，第一沟槽壁衬有具有第一厚度的氧化物，并且第二沟槽壁衬有具有不同于第一厚度的第二厚度的氧化物。另一半导体器件实施例包括衬底，衬底中的有源栅极沟槽; 以及衬底中的源极多晶硅拾取沟槽。源多晶硅拾取沟槽包括多晶硅电极，并且多晶硅电极的顶表面在身体区域的底部之下。另一个半导体器件包括衬底，衬底中的有源栅极沟槽，有源栅极沟槽具有第一顶部栅电极和第一底部源极电极，以及包括第二顶部栅电极和第二底部源极电极的栅极流道沟槽。第二顶栅电极比第二底源电极窄。

22. 发明授权

US08098466B2 Circuit configurations to reduce snapback of a transient voltage suppressor 有权
标题翻译：电路配置，以减少瞬态电压抑制器的快速恢复
公开(公告)号：US08098466B2
公开(公告)日：2012-01-17
申请号：US13066907
申请日：2011-04-26
申请人： Shekar Mallikarjunaswamy
发明人： Shekar Mallikarjunaswamy
IPC分类号： H02H9/00
CPC分类号： H01L27/0262 , H01L29/87
摘要： This invention discloses an electronic device formed as an integrated circuit (IC) wherein the electronic device further includes a transient voltage suppressing (TVS) circuit. The TVS circuit includes a triggering Zener diode connected between an emitter and a collector of a bipolar-junction transistor (BJT) wherein the Zener diode having a reverse breakdown voltage BV less than or equal to a BVceo of the BJT where BVceo stands for a collector to emitter breakdown voltage with base left open. The TVS circuit further includes a rectifier connected in parallel to the BJT for triggering a rectified current through the rectifier for further limiting an increase of a reverse blocking voltage. In a preferred embodiment, the triggering Zener diode, the BJT and the rectifier are formed in a semiconductor substrate by implanting and configuring dopant regions of a first and a second conductivity types in a N-well and a P-well whereby the TVS can be formed in parallel as part of the manufacturing processes of the electronic device.
摘要翻译：本发明公开了一种形成为集成电路（IC）的电子设备，其中电子设备还包括瞬态电压抑制（TVS）电路。 TVS电路包括连接在双极结型晶体管（BJT）的发射极和集电极之间的触发齐纳二极管，其中齐纳二极管的反向击穿电压BV小于或等于BJT的BVceo，其中BVceo代表集电极到发射极击穿电压，基极左开。 TVS电路还包括与BJT并联连接的整流器，用于触发整流器的整流电流，用于进一步限制反向阻断电压的增加。在优选实施例中，触发齐纳二极管，BJT和整流器通过在N阱和P阱中注入和配置第一和第二导电类型的掺杂区而形成在半导体衬底中，由此TVS可以作为电子设备的制造过程的一部分并行形成。

23. 发明申请

US20110089492A1 High voltage semiconductor device with JFET regions containing dielectrically isolated junctions and method of fabricating the same 有权
标题翻译：具有包含介电隔离结的JFET区域的高电压半导体器件及其制造方法
公开(公告)号：US20110089492A1
公开(公告)日：2011-04-21
申请号：US12928682
申请日：2010-12-16
申请人： Hamza Yilmaz
发明人： Hamza Yilmaz
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7393 , H01L29/0634 , H01L29/0653 , H01L29/0696 , H01L29/42368 , H01L29/66681 , H01L29/7816 , H01L29/8611 , H01L2924/0002 , H01L2924/00
摘要： A high-voltage field-effect device contains an extended drain or “drift” region including an embedded stack of JFET regions separated by intervening layers of the drift region. Each of the JFET regions is filled with material of an opposite conductivity type to that of the drift region, and the floor and ceiling of each JFET region is lined with an oxide layer. When the device is blocking a voltage in the off condition, the semiconductor material inside the JFET regions and in the drift region that separates the JFET regions is depleted. This improves the voltage-blocking ability of the device while conserving chip area. The oxide layer prevents dopant from the JFET regions from diffusing into the drift region.
摘要翻译：高电压场效应器件包含延伸的漏极或“漂移”区域，包括由漂移区的中间层隔开的JFET区域的嵌入堆叠。每个JFET区域都填充有与漂移区域相反的导电类型的材料，并且每个JFET区域的地板和天花板都衬有氧化物层。当器件在断开状态下阻塞电压时，JFET区域内部和分离JFET区域的漂移区域内的半导体材料耗尽。这提高了器件的压阻能力，同时节省了芯片面积。氧化物层防止来自JFET区域的掺杂剂扩散到漂移区域。

24. 发明授权

US07906375B2 Compact co-packaged semiconductor dies with elevation-adaptive interconnection plates 有权
标题翻译：具有高度自适应互连板的紧凑型共封装半导体管芯
公开(公告)号：US07906375B2
公开(公告)日：2011-03-15
申请号：US12832913
申请日：2010-07-08
申请人： Kai Liu , Ming Sun
发明人： Kai Liu , Ming Sun
IPC分类号： H01L21/50 , H01L21/48 , H01L21/44 , H01L23/495 , H01L29/00
CPC分类号： H01L24/49 , H01L23/49524 , H01L23/49541 , H01L23/49562 , H01L23/49575 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/48 , H01L24/73 , H01L25/0655 , H01L25/072 , H01L2224/37011 , H01L2224/40095 , H01L2224/40245 , H01L2224/4103 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/49171 , H01L2224/73221 , H01L2224/73265 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01027 , H01L2924/01033 , H01L2924/01082 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H01L2924/00 , H01L2224/45099 , H01L2224/37099
摘要： A semiconductor package is disclosed for packaging two adjacent semiconductor dies atop a circuit substrate. The dies are separated from each other along their longitudinal edges with an inter-die distance. An elevation-adaptive electrical connection connects a top metalized contact of die two to the bottom surface of die one while accommodating for elevation difference between the surfaces. The elevation-adaptive electrical connection includes: a) An L-shaped circuit route that is part of the circuit substrate, extending transversely from a die one longitudinal edge and placing an intermediate contact area next to a die two transverse edge. b) An interconnection plate connecting the top metalized contact area of die two with the intermediate contact area while being formed to accommodate for elevation difference between the contact areas. Consequently, the semiconductor package reduces the inter-die distance from an otherwise direct transverse circuit routing between the longitudinal edges of the dies.
摘要翻译：公开了一种半导体封装，用于在电路基板顶部封装两个相邻的半导体管芯。模具沿其纵向边缘彼此分开，具有模间距离。高度自适应电连接将模具2的顶部金属化接触件连接到模具的底表面，同时容纳表面之间的高度差。升降自适应电连接包括：a）L形电路，其是电路基板的一部分，从模具的一个纵向边缘横向延伸，并将中间接触区域放置在模具两个横向边缘旁边。 b）互连板，其在形成时将模具2的顶部金属化接触区域与中间接触区域连接，以适应接触区域之间的高度差。因此，半导体封装减少了在芯片的纵向边缘之间的另外直接的横向电路布线的晶片间距离。

25. 发明授权

US09153653B2 Termination design by metal strapping guard ring trenches shorted to a body region to shrink termination area 有权
标题翻译：通过金属绑带保护环的沟槽终止设计，短路到身体区域以缩小端接区域
公开(公告)号：US09153653B2
公开(公告)日：2015-10-06
申请号：US14098538
申请日：2013-12-06
申请人： Karthik Padmanabhan , Madhur Bobde
发明人： Karthik Padmanabhan , Madhur Bobde
IPC分类号： H01L29/00 , H01L29/40 , H01L29/36 , H01L29/78
CPC分类号： H01L29/7802 , H01L29/0623 , H01L29/0878 , H01L29/1095 , H01L29/36 , H01L29/407 , H01L29/66712 , H01L29/78 , H01L29/7811
摘要： This invention discloses a semiconductor power device formed in a semiconductor substrate of a first conductivity type comprises an active cell area and a termination area surrounding the active cell area and disposed near edges of the semiconductor substrate. The termination area includes a plurality of trenches filled with a conductivity material forming a shield electrode and insulated by a dielectric layer along trench sidewalls and trench bottom surface wherein the trenches extending vertically through a body region of a second conductivity type near a top surface of the semiconductor substrate and further extending through a surface shield region of the first conductivity type. A dopant region of the second conductivity type disposed below the surface shield region extending across and surrounding a trench bottom portion of the trenches. At least a metal connector disposed above the top surface of the semiconductor substrates electrically connecting to the shield electrode of at least two trenches and shorted to the body region.
摘要翻译：本发明公开了一种形成在第一导电类型的半导体衬底中的半导体功率器件，包括有源电池区域和围绕有源电池区域的端接区域，并设置在半导体衬底的边缘附近。终端区域包括填充有形成屏蔽电极的导电材料的多个沟槽，并且沿着沟槽侧壁和沟槽底表面被电介质层绝缘，其中沟槽垂直延伸穿过第二导电类型的体区附近靠近顶部表面并且还延伸穿过第一导电类型的表面屏蔽区域。第二导电类型的掺杂剂区域设置在表面屏蔽区域的下方，延伸穿过并围绕沟槽的沟槽底部。至少一个金属连接器，设置在半导体衬底的顶表面之上，电连接到至少两个沟槽的屏蔽电极并且短路到身体区域。

26. 发明申请

US20130119393A1 Vertical Gallium Nitride Schottky Diode 有权
标题翻译：立式氮化镓肖特基二极管
公开(公告)号：US20130119393A1
公开(公告)日：2013-05-16
申请号：US13294903
申请日：2011-11-11
申请人： TingGang Zhu , Anup Bhalla , Ping Huang , Yueh-se Ho
发明人： TingGang Zhu , Anup Bhalla , Ping Huang , Yueh-se Ho
IPC分类号： H01L29/20 , H01L29/06 , H01L21/20
CPC分类号： H01L29/872 , H01L21/0217 , H01L21/0254 , H01L21/28581 , H01L21/30612 , H01L21/31111 , H01L21/56 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L25/18 , H01L27/0248 , H01L27/0814 , H01L29/0619 , H01L29/0688 , H01L29/2003 , H01L29/402 , H01L29/405 , H01L29/417 , H01L29/66136 , H01L29/66143 , H01L29/66212 , H01L29/861 , H01L29/8611 , H01L2224/0401 , H01L2224/04042 , H01L2224/05016 , H01L2224/05567 , H01L2224/11616 , H01L2224/13017 , H01L2224/13021 , H01L2224/13022 , H01L2924/00014 , H01L2924/1033 , H01L2924/12032 , H01L2924/12036 , H01L2924/12041 , H01L2924/12042 , H01L2924/00012 , H01L2924/00 , H01L2224/05552
摘要： A vertical conduction nitride-based Schottky diode is formed using an insulating substrate which was lifted off after the diode device is encapsulated on the front side with a wafer level molding compound. The wafer level molding compound provides structural support on the front side of the diode device to allow the insulating substrate to be lifted off so that a conductive layer can be formed on the backside of the diode device as the cathode electrode. A vertical conduction nitride-based Schottky diode is thus realized. In another embodiment, a protection circuit for a vertical GaN Schottky diode employs a silicon-based vertical PN junction diode connected in parallel to the GaN Schottky diode to divert reverse bias avalanche current.
摘要翻译：使用绝缘基板形成垂直导电氮化物基肖特基二极管，绝缘基板在二极管器件用晶片级模塑料封装在前侧之后被提起。晶片级成型复合体在二极管器件的前侧提供结构支撑，以允许绝缘基板被提起，使得可以在作为阴极的二极管器件的背面上形成导电层。因此实现了基于垂直导电氮化物的肖特基二极管。在另一个实施例中，用于垂直GaN肖特基二极管的保护电路采用与GaN肖特基二极管并联连接的硅基垂直PN结二极管，以转移反向偏置雪崩电流。

27. 发明授权

US08076183B2 Method of attaching an interconnection plate to a semiconductor die within a leadframe package 有权
标题翻译：将互连板附接到引线框架封装内的半导体管芯的方法
公开(公告)号：US08076183B2
公开(公告)日：2011-12-13
申请号：US12606290
申请日：2009-10-27
申请人： Yan Xun Xue , Jun Lu , Le Shi , Liang Zhao
发明人： Yan Xun Xue , Jun Lu , Le Shi , Liang Zhao
IPC分类号： H01L21/50 , H01L21/48 , H01L21/44
CPC分类号： H01L24/73 , H01L21/4842 , H01L23/3107 , H01L23/49541 , H01L23/49551 , H01L24/29 , H01L24/37 , H01L24/40 , H01L24/48 , H01L24/83 , H01L24/84 , H01L24/85 , H01L24/92 , H01L24/97 , H01L2224/0603 , H01L2224/29339 , H01L2224/371 , H01L2224/37599 , H01L2224/48247 , H01L2224/73221 , H01L2224/83101 , H01L2224/83801 , H01L2224/8385 , H01L2224/85 , H01L2224/92 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01057 , H01L2924/01082 , H01L2924/014 , H01L2924/13091 , H01L2924/30107 , H01L2924/3011 , H01L2224/83 , H01L2224/84 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method is disclosed for attaching an interconnection plate to semiconductor die within leadframe package. A base leadframe is provided with die pad for attaching semiconductor die. An interconnection plate is provided for attachment to the base leadframe and semiconductor die. Add a base registration feature onto base leadframe and a plate registration feature onto interconnection plate with the registration features designed to match each other such that, upon approach of the interconnection plate to base leadframe, the two registration features would engage and guide each other causing concomitant self-aligned attachment of the interconnection plate to base leadframe. Next, the interconnection plate is brought into close approach to base leadframe to engage and lock plate registration feature to base registration feature hence completing attachment of the interconnection plate to semiconductor die and forming a leadframe package.
摘要翻译：公开了一种将引线框封装内的互连板连接到半导体管芯的方法。基座引线框架设置有用于附接半导体管芯的管芯焊盘。提供互连板，用于附接到基底引线框架和半导体管芯。将基准注册功能添加到基准引线框架和板对准特征到互连板上，其中配准特征被设计成彼此匹配，使得在互连板到基底引线框架的接近时，两个配准特征将相互接合并引导彼此引起伴随互连板与基座引线框架的自对准连接。接下来，使互连板靠近基底引线框架以将板对准特征接合并锁定到基准对准特征，从而完成互连板连接到半导体管芯并形成引线框封装。

28. 发明授权

US08067304B2 Method for forming a patterned thick metallization atop a power semiconductor chip 有权
标题翻译：在功率半导体芯片顶上形成图案化的厚金属化的方法
公开(公告)号：US08067304B2
公开(公告)日：2011-11-29
申请号：US12356077
申请日：2009-01-20
申请人： Il Kwan Lee
发明人： Il Kwan Lee
IPC分类号： H01L21/20
CPC分类号： H01L29/7811 , H01L23/544 , H01L24/45 , H01L24/48 , H01L24/49 , H01L29/41741 , H01L29/456 , H01L29/7813 , H01L2224/05624 , H01L2224/0603 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48247 , H01L2224/48624 , H01L2224/48724 , H01L2224/48824 , H01L2224/49111 , H01L2924/00015 , H01L2924/01013 , H01L2924/01014 , H01L2924/01079 , H01L2924/10253 , H01L2924/13091 , H01L2924/00014 , H01L2924/01029 , H01L2924/0132 , H01L2924/00
摘要： A method is disclosed for forming a patterned thick metallization atop a semiconductor chip wafer. The method includes fabricating a nearly complete semiconductor chip wafer ready for metallization; depositing a bottom metal layer of sub-thickness TK1 together with its built-in alignment mark using a hot metal process; depositing a top metal layer of sub-thickness TK2 using a cold metal process thus forming a stacked thick metallization of total thickness TK=TK1+TK2; then, use the built-in alignment mark as reference, patterning the stacked thick metallization. A patterned thick metallization is thus formed with the advantages of better metal step coverage owing to the superior step coverage nature of the hot metal process as compared to the cold metal process; and lower alignment error rate owing to the lower alignment signal noise nature of the cold metal process as compared to the hot metal process.
摘要翻译：公开了用于在半导体芯片晶片顶上形成图案化的厚金属化的方法。该方法包括制备准备金属化的几乎完整的半导体芯片晶片; 使用热金属工艺沉积次厚度TK1的底部金属层及其内置对准标记; 使用冷金属工艺沉积亚层厚度TK2的顶金属层，从而形成总厚度TK = TK1 + TK2的层叠厚金属化; 然后，使用内置的对准标记作为参考，图案化堆叠的厚金属化。因此，与冷金属工艺相比，由于与金属工艺相比，热金属工艺具有优异的阶梯覆盖性，因此形成了图案化的金属化，具有更好的金属台阶覆盖的优点; 并且由于与金属热处理相比，冷金属工艺的对准信号噪声特性较低，因此对准误差率降低。

29. 发明授权

US07902894B2 Accurate hysteretic comparator and method 有权
标题翻译：准确的滞后比较器和方法
公开(公告)号：US07902894B2
公开(公告)日：2011-03-08
申请号：US12493142
申请日：2009-06-26
申请人： Behzad Mohtashemi
发明人： Behzad Mohtashemi
IPC分类号： H03K5/22
CPC分类号： H03K5/2481
摘要： A hysteretic comparator is proposed for comparing input signals and producing an output signal VOT with a hysteresis window Vhys. The hysteretic comparator includes a differential input stage with current output (DICO) having input transistors with transconductance Gmtnx for converting the input signals, with an input stage transconductance Gmin, into intermediate signal currents. A steerable offset current generator, driven by a steering control signal, steers an offset current source IOS to alternative offset currents. A current-to-voltage summing converter (IVSC) sums up the intermediate signal currents and the offset currents and converts the result into VOT plus the steering control signal causing Vhys=IOS/Gmin. A feedback resistance RNF is connected to the input transistors to form a negative feedback loop. The RNF is sized such that GMin, hence Vhys, becomes essentially solely dependent upon the feedback conductance GNF=1/RNF independent of the Gmtnx thus its process and environmental variation.
摘要翻译：提出了一种滞后比较器，用于比较输入信号并产生具有滞后窗口Vhys的输出信号VOT。迟滞比较器包括具有电流输出（DICO）的差分输入级，具有跨导Gmtnx的输入晶体管，用于将具有输入级跨导Gmin的输入信号转换成中间信号电流。由转向控制信号驱动的可转向偏移电流发生器将偏移电流源IOS转向替代偏移电流。电流 - 电压求和转换器（IVSC）将中间信号电流和偏移电流相加，并将结果转换为VOT加上导致Vhys = IOS / Gmin的转向控制信号。反馈电阻RNF连接到输入晶体管以形成负反馈回路。 RNF的大小使得GMin因此Vhys基本上仅依赖于反馈电导GNF = 1 / RNF，而与Gmtnx无关，因此其过程和环境变化。

30. 发明申请

US20130075808A1 Trench MOSFET with Integrated Schottky Barrier Diode 有权
标题翻译：集成肖特基势垒二极管的沟槽MOSFET
公开(公告)号：US20130075808A1
公开(公告)日：2013-03-28
申请号：US13241126
申请日：2011-09-22
申请人： Daniel Calafut , Yi Su , Jongoh Kim , Hong Chang , Hamza Yilmaz , Daniel S. Ng
发明人： Daniel Calafut , Yi Su , Jongoh Kim , Hong Chang , Hamza Yilmaz , Daniel S. Ng
IPC分类号： H01L29/872 , H01L27/06
CPC分类号： H01L29/7813 , H01L21/823487 , H01L27/06 , H01L27/0629 , H01L29/0649 , H01L29/0653 , H01L29/0878 , H01L29/407 , H01L29/41766 , H01L29/456 , H01L29/47 , H01L29/66143 , H01L29/7806 , H01L29/872
摘要： A Schottky diode includes a semiconductor layer formed on a semiconductor substrate; first and second trenches formed in the semiconductor layer where the first and second trenches are lined with a thin dielectric layer and being filled partially with a trench conductor layer and remaining portions of the first and second trenches are filled with a first dielectric layer; and a Schottky metal layer formed on a top surface of the semiconductor layer between the first trench and the second trench. The Schottky diode is formed with the Schottky metal layer as the anode and the semiconductor layer between the first and second trenches as the cathode. The trench conductor layer in each of the first and second trenches is electrically connected to the anode of the Schottky diode. In one embodiment, the Schottky diode is formed integrated with a trench field effect transistor on the same semiconductor substrate.
摘要翻译：肖特基二极管包括形成在半导体衬底上的半导体层; 第一和第二沟槽形成在半导体层中，其中第一和第二沟槽衬有薄介电层，并部分地填充有沟槽导体层，并且第一和第二沟槽的剩余部分填充有第一介电层; 以及形成在所述第一沟槽和所述第二沟槽之间的所述半导体层的顶表面上的肖特金属层。肖特基二极管由肖特基金属层作为阳极形成，第一和第二沟槽之间的半导体层作为阴极形成。第一和第二沟槽中的每一个中的沟槽导体层电连接到肖特基二极管的阳极。在一个实施例中，肖特基二极管与同一半导体衬底上的沟槽场效应晶体管集成。

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