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1. 发明授权

US08610235B2 Trench MOSFET with integrated Schottky barrier diode 有权
标题翻译：集成肖特基势垒二极管的沟槽MOSFET
公开(公告)号：US08610235B2
公开(公告)日：2013-12-17
申请号：US13241126
申请日：2011-09-22
申请人： Daniel Calafut , Yi Su , Jongoh Kim , Hong Chang , Hamza Yilmaz , Daniel S. Ng
发明人： Daniel Calafut , Yi Su , Jongoh Kim , Hong Chang , Hamza Yilmaz , Daniel S. Ng
IPC分类号： H01L29/47
CPC分类号： H01L29/7813 , H01L21/823487 , H01L27/06 , H01L27/0629 , H01L29/0649 , H01L29/0653 , H01L29/0878 , H01L29/407 , H01L29/41766 , H01L29/456 , H01L29/47 , H01L29/66143 , H01L29/7806 , H01L29/872
摘要： A Schottky diode includes a semiconductor layer formed on a semiconductor substrate; first and second trenches formed in the semiconductor layer where the first and second trenches are lined with a thin dielectric layer and being filled partially with a trench conductor layer and remaining portions of the first and second trenches are filled with a first dielectric layer; and a Schottky metal layer formed on a top surface of the semiconductor layer between the first trench and the second trench. The Schottky diode is formed with the Schottky metal layer as the anode and the semiconductor layer between the first and second trenches as the cathode. The trench conductor layer in each of the first and second trenches is electrically connected to the anode of the Schottky diode. In one embodiment, the Schottky diode is formed integrated with a trench field effect transistor on the same semiconductor substrate.
摘要翻译：肖特基二极管包括形成在半导体衬底上的半导体层; 第一和第二沟槽形成在半导体层中，其中第一和第二沟槽衬有薄介电层，并部分地填充有沟槽导体层，并且第一和第二沟槽的剩余部分填充有第一介电层; 以及形成在所述第一沟槽和所述第二沟槽之间的所述半导体层的顶表面上的肖特金属层。肖特基二极管由肖特基金属层作为阳极形成，第一和第二沟槽之间的半导体层作为阴极形成。第一和第二沟槽中的每一个中的沟槽导体层电连接到肖特基二极管的阳极。在一个实施例中，肖特基二极管与同一半导体衬底上的沟槽场效应晶体管集成。

2. 发明申请

US20130075808A1 Trench MOSFET with Integrated Schottky Barrier Diode 有权
标题翻译：集成肖特基势垒二极管的沟槽MOSFET
公开(公告)号：US20130075808A1
公开(公告)日：2013-03-28
申请号：US13241126
申请日：2011-09-22
申请人： Daniel Calafut , Yi Su , Jongoh Kim , Hong Chang , Hamza Yilmaz , Daniel S. Ng
发明人： Daniel Calafut , Yi Su , Jongoh Kim , Hong Chang , Hamza Yilmaz , Daniel S. Ng
IPC分类号： H01L29/872 , H01L27/06
CPC分类号： H01L29/7813 , H01L21/823487 , H01L27/06 , H01L27/0629 , H01L29/0649 , H01L29/0653 , H01L29/0878 , H01L29/407 , H01L29/41766 , H01L29/456 , H01L29/47 , H01L29/66143 , H01L29/7806 , H01L29/872
摘要： A Schottky diode includes a semiconductor layer formed on a semiconductor substrate; first and second trenches formed in the semiconductor layer where the first and second trenches are lined with a thin dielectric layer and being filled partially with a trench conductor layer and remaining portions of the first and second trenches are filled with a first dielectric layer; and a Schottky metal layer formed on a top surface of the semiconductor layer between the first trench and the second trench. The Schottky diode is formed with the Schottky metal layer as the anode and the semiconductor layer between the first and second trenches as the cathode. The trench conductor layer in each of the first and second trenches is electrically connected to the anode of the Schottky diode. In one embodiment, the Schottky diode is formed integrated with a trench field effect transistor on the same semiconductor substrate.
摘要翻译：肖特基二极管包括形成在半导体衬底上的半导体层; 第一和第二沟槽形成在半导体层中，其中第一和第二沟槽衬有薄介电层，并部分地填充有沟槽导体层，并且第一和第二沟槽的剩余部分填充有第一介电层; 以及形成在所述第一沟槽和所述第二沟槽之间的所述半导体层的顶表面上的肖特金属层。肖特基二极管由肖特基金属层作为阳极形成，第一和第二沟槽之间的半导体层作为阴极形成。第一和第二沟槽中的每一个中的沟槽导体层电连接到肖特基二极管的阳极。在一个实施例中，肖特基二极管与同一半导体衬底上的沟槽场效应晶体管集成。

3. 发明授权

US07504676B2 Planar split-gate high-performance MOSFET structure and manufacturing method 有权
公开(公告)号：US07504676B2
公开(公告)日：2009-03-17
申请号：US11444853
申请日：2006-05-31
申请人： Anup Bhalla , Francois Hebert , Daniel S. Ng
发明人： Anup Bhalla , Francois Hebert , Daniel S. Ng
IPC分类号： H01L29/80
CPC分类号： H01L29/7802 , H01L21/26586 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/41766 , H01L29/42372 , H01L29/42376 , H01L29/66712 , H01L29/7828
摘要： This invention discloses an improved semiconductor power device includes a plurality of power transistor cells wherein each cell further includes a planar gate padded by a gate oxide layer disposed on top of a drift layer constituting an upper layer of a semiconductor substrate wherein the planar gate further constituting a split gate including a gap opened in a gate layer whereby the a total surface area of the gate is reduced. The transistor cell further includes a JFET (junction field effect transistor) diffusion region disposed in the drift layer below the gap of the gate layer wherein the JFET diffusion region having a higher dopant concentration than the drift region for reducing a channel resistance of the semiconductor power device. The transistor cell further includes a shallow surface doped regions disposed near a top surface of the drift layer under the gate adjacent to the JFET diffusion region wherein the shallow surface doped region having a dopant concentration lower than the JFET diffusion region and higher than the drift layer.

4. 发明授权

US08053298B2 Planar split-gate high-performance MOSFET structure and manufacturing method 有权
标题翻译：平面分闸高性能MOSFET结构及制造方法
公开(公告)号：US08053298B2
公开(公告)日：2011-11-08
申请号：US12381813
申请日：2009-03-16
申请人： Anup Bhalla , Francois Hebert , Daniel S. Ng
发明人： Anup Bhalla , Francois Hebert , Daniel S. Ng
IPC分类号： H01L21/337
CPC分类号： H01L29/7802 , H01L21/26586 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/41766 , H01L29/42372 , H01L29/42376 , H01L29/66712 , H01L29/7828
摘要： This invention discloses an improved semiconductor power device includes a plurality of power transistor cells wherein each cell further includes a planar gate padded by a gate oxide layer disposed on top of a drift layer constituting an upper layer of a semiconductor substrate wherein the planar gate further constituting a split gate including a gap opened in a gate layer whereby the a total surface area of the gate is reduced. The transistor cell further includes a JFET (junction field effect transistor) diffusion region disposed in the drift layer below the gap of the gate layer wherein the JFET diffusion region having a higher dopant concentration than the drift region for reducing a channel resistance of the semiconductor power device. The transistor cell further includes a shallow surface doped regions disposed near a top surface of the drift layer under the gate adjacent to the JFET diffusion region wherein the shallow surface doped region having a dopant concentration lower than the JFET diffusion region and higher than the drift layer.
摘要翻译：本发明公开了一种改进的半导体功率器件，包括多个功率晶体管单元，其中每个单元还包括由设置在构成半导体衬底的上层的漂移层的顶部上的栅极氧化物层填充的平面栅极，其中平面栅极进一步构成分闸门，其包括在栅极层中开口的间隙，由此栅极的总表面积减小。晶体管单元还包括设置在栅极层间隙之下的漂移层中的JFET（结场效应晶体管）扩散区，其中具有比漂移区更高的掺杂浓度的JFET扩散区用于降低半导体功率的沟道电阻设备。晶体管单元还包括在邻近JFET扩散区的栅极附近设置在漂移层的顶表面附近的浅表面掺杂区，其中掺杂浓度低于JFET扩散区并且高于漂移层的浅表面掺杂区。

5. 发明申请

US20090181503A1 Planar split-gate high-performance MOSFET structure and manufacturing method 有权
标题翻译：平面分闸高性能MOSFET结构及制造方法
公开(公告)号：US20090181503A1
公开(公告)日：2009-07-16
申请号：US12381813
申请日：2009-03-16
申请人： Anup Bhalla , Francois Hebert , Daniel S. Ng
发明人： Anup Bhalla , Francois Hebert , Daniel S. Ng
IPC分类号： H01L21/337
CPC分类号： H01L29/7802 , H01L21/26586 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/41766 , H01L29/42372 , H01L29/42376 , H01L29/66712 , H01L29/7828
摘要： This invention discloses an improved semiconductor power device includes a plurality of power transistor cells wherein each cell further includes a planar gate padded by a gate oxide layer disposed on top of a drift layer constituting an upper layer of a semiconductor substrate wherein the planar gate further constituting a split gate including a gap opened in a gate layer whereby the a total surface area of the gate is reduced. The transistor cell further includes a JFET (junction field effect transistor) diffusion region disposed in the drift layer below the gap of the gate layer wherein the JFET diffusion region having a higher dopant concentration than the drift region for reducing a channel resistance of the semiconductor power device. The transistor cell further includes a shallow surface doped regions disposed near a top surface of the drift layer under the gate adjacent to the JFET diffusion region wherein the shallow surface doped region having a dopant concentration lower than the JFET diffusion region and higher than the drift layer.
摘要翻译：本发明公开了一种改进的半导体功率器件，包括多个功率晶体管单元，其中每个单元还包括由设置在构成半导体衬底的上层的漂移层的顶部上的栅极氧化物层填充的平面栅极，其中平面栅极进一步构成分闸门，其包括在栅极层中开口的间隙，由此栅极的总表面积减小。晶体管单元还包括设置在栅极层间隙之下的漂移层中的JFET（结场效应晶体管）扩散区，其中具有比漂移区更高的掺杂浓度的JFET扩散区用于降低半导体功率的沟道电阻设备。晶体管单元还包括在邻近JFET扩散区的栅极附近设置在漂移层的顶表面附近的浅表面掺杂区，其中掺杂浓度低于JFET扩散区并且高于漂移层的浅表面掺杂区。

6. 发明申请

US20070278571A1 Planar split-gate high-performance MOSFET structure and manufacturing method 有权
标题翻译：平面分闸高性能MOSFET结构及制造方法
公开(公告)号：US20070278571A1
公开(公告)日：2007-12-06
申请号：US11444853
申请日：2006-05-31
申请人： Anup Bhalla , Francois Hebert , Daniel S. Ng
发明人： Anup Bhalla , Francois Hebert , Daniel S. Ng
IPC分类号： H01L29/94 , H01L29/76
CPC分类号： H01L29/7802 , H01L21/26586 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/41766 , H01L29/42372 , H01L29/42376 , H01L29/66712 , H01L29/7828
摘要： This invention discloses an improved semiconductor power device includes a plurality of power transistor cells wherein each cell further includes a planar gate padded by a gate oxide layer disposed on top of a drift layer constituting an upper layer of a semiconductor substrate wherein the planar gate further constituting a split gate including a gap opened in a gate layer whereby the a total surface area of the gate is reduced. The transistor cell further includes a JFET (junction field effect transistor) diffusion region disposed in the drift layer below the gap of the gate layer wherein the JFET diffusion region having a higher dopant concentration than the drift region for reducing a channel resistance of the semiconductor power device. The transistor cell further includes a shallow surface doped regions disposed near a top surface of the drift layer under the gate adjacent to the JFET diffusion region wherein the shallow surface doped region having a dopant concentration lower than the JFET diffusion region and higher than the drift layer.
摘要翻译：本发明公开了一种改进的半导体功率器件，包括多个功率晶体管单元，其中每个单元还包括由设置在构成半导体衬底的上层的漂移层的顶部上的栅极氧化物层填充的平面栅极，其中平面栅极进一步构成分闸门，其包括在栅极层中开口的间隙，由此栅极的总表面积减小。晶体管单元还包括设置在栅极层间隙之下的漂移层中的JFET（结场效应晶体管）扩散区，其中具有比漂移区更高的掺杂浓度的JFET扩散区用于降低半导体功率的沟道电阻设备。晶体管单元还包括在邻近JFET扩散区的栅极附近设置在漂移层的顶表面附近的浅表面掺杂区，其中掺杂浓度低于JFET扩散区并且高于漂移层的浅表面掺杂区。

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