专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

201. 发明申请

US20160011259A1 INTEGRATED CIRCUIT DEVICE AND METHOD THEREFOR 有权
标题翻译：集成电路设备及其方法
公开(公告)号：US20160011259A1
公开(公告)日：2016-01-14
申请号：US14330544
申请日：2014-07-14
申请人： VLADIMIR LITOVCHENKO , HEIKO AHRENS , ANDREAS ROLAND STAHL
发明人： VLADIMIR LITOVCHENKO , HEIKO AHRENS , ANDREAS ROLAND STAHL
IPC分类号： G01R31/3177 , G01R31/317
CPC分类号： G01R31/3187 , G01R31/31721 , G01R31/31727
摘要： An integrated circuit device comprising at least one self-test component arranged to execute self-testing within at least one self-test structure during a self-test execution phase of the IC device, and at least one clock control component arranged to provide at least one clock signal to the at least one self-test component at least during the self-test execution phase of the IC device. The at least one clock control component is further arranged to receive at least one indication of at least one power dissipation parameter for at least a part of the IC device, and modulate the at least one clock signal provided to the at least one self-test component based at least partly on the received at least one power dissipation parameter for at least a part of the IC device.
摘要翻译：一种集成电路装置，包括至少一个自检部件，被布置成在IC器件的自检执行阶段期间在至少一个自检结构内执行自检，以及至少一个时钟控制部件，被布置成至少提供至少在IC器件的自检执行阶段期间至少一个自检部件的一个时钟信号。所述至少一个时钟控制部件还被布置成接收至少一个IC器件的至少一部分功率耗散参数的指示，并且调制提供给所述至少一个自检的至少一个时钟信号至少部分地基于所述IC器件的至少一部分的所接收的至少一个功耗参数。

202. 发明授权

US09236795B2 Voltage generator with ramp rate control 有权
标题翻译：电压发生器，具有斜坡率控制
公开(公告)号：US09236795B2
公开(公告)日：2016-01-12
申请号：US14182702
申请日：2014-02-18
申请人： Perry H. Pelley , Michael G. Neaves
发明人： Perry H. Pelley , Michael G. Neaves
IPC分类号： G05F1/10 , H02M3/07
CPC分类号： H02M3/07 , H02M2001/0003
摘要： A charge pump system includes a comparator having a first input coupled to a first reference voltage, a second input coupled to a feedback signal and an output coupled to control operation of a voltage controlled oscillator. The feedback signal is coupled to an output of the charge pump system. An amplifier has a first input coupled to a second reference voltage, a second input coupled to the feedback signal, and an output coupled as input to the voltage controlled oscillator. A gain of the amplifier is lower than a gain of the comparator.
摘要翻译：电荷泵系统包括具有耦合到第一参考电压的第一输入的比较器，耦合到反馈信号的第二输入和耦合到控制压控振荡器的操作的输出。反馈信号耦合到电荷泵系统的输出端。放大器具有耦合到第二参考电压的第一输入，耦合到反馈信号的第二输入和耦合到压控振荡器的输入的输出。放大器的增益低于比较器的增益。

203. 发明授权

US09236472B2 Semiconductor device with integrated breakdown protection 有权
标题翻译：具有集成故障保护的半导体器件
公开(公告)号：US09236472B2
公开(公告)日：2016-01-12
申请号：US13448994
申请日：2012-04-17
申请人： Weize Chen , Hubert M. Bode , Richard J. De Souza , Patrice M. Parris
发明人： Weize Chen , Hubert M. Bode , Richard J. De Souza , Patrice M. Parris
IPC分类号： H01L29/78 , H01L29/66 , H01L29/06 , H01L29/10
CPC分类号： H01L29/7823 , H01L21/2253 , H01L29/0626 , H01L29/0653 , H01L29/0865 , H01L29/0882 , H01L29/1083 , H01L29/1087 , H01L29/1095 , H01L29/66659 , H01L29/66681 , H01L29/7824 , H01L29/7835
摘要： A device includes a semiconductor substrate having a first conductivity type, a device isolating region in the semiconductor substrate, defining an active area, and having a second conductivity type, a body region in the active area and having the first conductivity type, and a drain region in the active area and spaced from the body region to define a conduction path of the device, the drain region having the second conductivity type. The device isolating region and the body region are spaced from one another to establish a first breakdown voltage lower than a second breakdown voltage in the conduction path.
摘要翻译：一种器件包括具有第一导电类型的半导体衬底，半导体衬底中的器件隔离区，限定有源区，并具有第二导电类型，有源区中的体区，并具有第一导电类型，漏极区域，并且与身体区域间隔开以限定器件的导电路径，漏极区域具有第二导电类型。器件隔离区域和体区域彼此间隔开以建立低于导通路径中的第二击穿电压的第一击穿电压。

204. 发明授权

US09236344B2 Thin beam deposited fuse 有权
标题翻译：薄光束保险丝
公开(公告)号：US09236344B2
公开(公告)日：2016-01-12
申请号：US14570179
申请日：2014-12-15
申请人： Douglas M. Reber , Mehul D. Shroff , Edward O. Travis
发明人： Douglas M. Reber , Mehul D. Shroff , Edward O. Travis
IPC分类号： H01L29/00 , H01L23/525 , H01L23/528 , H01L23/532
CPC分类号： H01L23/5258 , H01L23/5256 , H01L23/528 , H01L23/53228 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A back-end-of-line thin ion beam deposited fuse (204) is deposited without etching to connect first and second last metal interconnect structures (110, 120) formed with last metal layers (LM) in a planar multi-layer interconnect stack to programmably connect separate first and second circuit connected to the first and second last metal interconnect structures.
摘要翻译：在没有蚀刻的情况下沉积后端行的薄离子束沉积的熔丝（204）以将在后面的金属层（LM）形成的第一和第二金属互连结构（110,120）连接在平面多层互连堆叠以可编程的方式连接连接到第一和第二金属互连结构的单独的第一和第二电路。

205. 发明申请

US20160004654A1 SYSTEM FOR MIGRATING STASH TRANSACTIONS 有权
标题翻译：移动交易系统
公开(公告)号：US20160004654A1
公开(公告)日：2016-01-07
申请号：US14324233
申请日：2014-07-06
申请人： Yashpal Dutta , Himanshu Goel , Varun Sethi
发明人： Yashpal Dutta , Himanshu Goel , Varun Sethi
IPC分类号： G06F13/28 , G06F13/42
CPC分类号： G06F13/28 , G06F3/00 , G06F9/466 , G06F9/4856 , G06F9/5088 , G06F12/00 , G06F12/1081 , G06F13/00 , G06F2212/1016
摘要： A system for migrating stash transactions includes first and second cores, an input/output memory management unit (IOMMU), an IOMMU mapping table, an input/output (I/O) device, a stash transaction migration management unit (STMMU), a queue manager and an operating system (OS) scheduler. The I/O device generates a first stash transaction request for a first data frame. The queue manager stores the first stash transaction request. When the first core executes a first thread, the queue manager stashes the first data frame to the first core by way of the IOMMU. The OS scheduler migrates the first thread from the first core to the second core and generates pre-empt notifiers. The STMMU uses the pre-empt notifiers to update the IOMMU mapping table and generate a stash replay command. The queue manager receives the stash replay command and stashes the first data frame to the second core.
摘要翻译：用于迁移存储交易的系统包括第一和第二内核，输入/输出存储器管理单元（IOMMU），IOMMU映射表，输入/输出（I / O）设备，存储交易迁移管理单元（STMMU），队列管理器和操作系统（OS）调度程序。 I / O设备为第一数据帧生成第一个存储交易请求。队列管理器存储第一个隐藏事务请求。当第一个核心执行第一个线程时，队列管理器通过IOMMU将第一个数据帧锁定到第一个内核。 OS调度程序将第一个线程从第一个内核迁移到第二个内核并生成预先通过的通知程序。 STMMU使用预先通过的通知程序来更新IOMMU映射表并生成一个存储重放命令。队列管理器接收收件重播命令并将第一个数据帧封锁到第二个核心。

206. 发明授权

US09232156B1 Video processing device and method 有权
标题翻译：视频处理装置及方法
公开(公告)号：US09232156B1
公开(公告)日：2016-01-05
申请号：US14492573
申请日：2014-09-22
申请人： Michael Andreas Staudenmaier , Stephan Herrmann , Robert Cristian Krutsch
发明人： Michael Andreas Staudenmaier , Stephan Herrmann , Robert Cristian Krutsch
IPC分类号： H04N9/74 , H04N5/265
CPC分类号： H04N5/265 , G06T1/60
摘要： A video processing device for generating an output video stream on the basis of two or more concurrent input video streams and a method thereof are described. Each input video stream comprises a sequence of input images. The output video stream comprises a sequence of output images. The video processing device generates each output image by merging a respective set of input images. The set of input images comprises one input image from each input video stream. The video processing device merges the input images in a series of merging rounds. Each merging round comprises forming an output tile by merging a set of input tiles, and writing the output tile to an output memory unit. The set of input tiles comprises one input tile from each input image of the respective set of input images. The output tiles written to the output memory unit represent the output image.
摘要翻译：描述了用于基于两个或多个并发输入视频流生成输出视频流的视频处理设备及其方法。每个输入视频流包括一系列输入图像。输出视频流包括一系列输出图像。视频处理装置通过合并各组输入图像来生成每个输出图像。该组输入图像包括来自每个输入视频流的一个输入图像。视频处理设备在一系列合并回合中合并输入图像。每个合并包括通过合并一组输入瓦片形成输出瓦片，以及将输出瓦片写入输出存储器单元。该组输入图块包括来自相应输入图像集合的每个输入图像的一个输入图块。写入输出存储单元的输出贴片表示输出图像。

207. 发明授权

US09231569B2 Variable delay and setup time flip-flop 有权
标题翻译：可变延迟和设置时间触发器
公开(公告)号：US09231569B2
公开(公告)日：2016-01-05
申请号：US13749542
申请日：2013-01-24
申请人： Alexandro Giron Allende
发明人： Alexandro Giron Allende
IPC分类号： H03K3/00 , H03K3/037
CPC分类号： H03K3/0375
摘要： An apparatus is provided. The apparatus includes a flip-flop including an input configured to receive a setup time and delay control (SDC) signal, and an output buffer including first and second conductive paths. The second conductive path is non-conductive when the SDC signal has a first value at the input and is conductive when the SDC signal has a second value at the input. The apparatus includes a propagation delay sensor configured to estimate a propagation delay of the flip-flop, and, when the estimated propagation delay exceeds a threshold, supply the SDC signal having the second value to the input of the flip-flop.
摘要翻译：提供了一种装置。该装置包括触发器，其包括被配置为接收建立时间和延迟控制（SDC）信号的输入，以及包括第一和第二导电路径的输出缓冲器。当SDC信号在输入处具有第一值时，第二导电路径不导通，并且当SDC信号在输入处具有第二值时导通。该装置包括被配置为估计触发器的传播延迟的传播延迟传感器，并且当估计的传播延迟超过阈值时，将具有第二值的SDC信号提供给触发器的输入。

208. 发明授权

US09231077B2 Method of making a logic transistor and non-volatile memory (NVM) cell 有权
标题翻译：制造逻辑晶体管和非易失性存储器（NVM）单元的方法
公开(公告)号：US09231077B2
公开(公告)日：2016-01-05
申请号：US14195299
申请日：2014-03-03
申请人： Mehul D. Shroff , Mark D. Hall
发明人： Mehul D. Shroff , Mark D. Hall
IPC分类号： H01L21/338 , H01L29/66 , H01L29/40 , H01L21/3213
CPC分类号： H01L29/66484 , H01L21/28273 , H01L21/32139 , H01L27/11534 , H01L29/401 , H01L29/42328 , H01L29/42332 , H01L29/66545 , H01L29/66825 , H01L29/66833
摘要： A method of forming a semiconductor device includes forming a first gate layer over a substrate in the NVM region and the logic region; forming an opening in the first gate layer in the NVM region; forming a charge storage layer in the opening; forming a control gate over the charge storage layer in the opening; patterning the first gate layer to form a first patterned gate layer portion over the substrate in the logic region and to form a second patterned gate layer portion over the substrate in the NVM region, wherein the second patterned gate layer portion is adjacent the control gate; forming a dielectric layer over the substrate around the first patterned gate layer portion and around the second patterned gate layer portion and the control gate, and replacing the first patterned gate layer portion with a logic gate comprising metal.
摘要翻译：形成半导体器件的方法包括在NVM区域和逻辑区域中的衬底上形成第一栅极层; 在NVM区域中的第一栅极层中形成开口; 在开口中形成电荷存储层; 在开口中的电荷存储层上形成控制栅极; 图案化第一栅极层以在逻辑区域中的衬底上形成第一图案化栅极层部分，并且在NVM区域中的衬底上形成第二图案化栅极层部分，其中第二图案化栅极层部分与控制栅极相邻; 在所述第一图案化栅极层部分周围以及所述第二图案化栅极层部分和所述控制栅极周围的所述基板上方形成介电层，并用包含金属的逻辑门代替所述第一图案化栅极层部分。

209. 发明授权

US09229767B2 Processing load with normal or fast operation mode 有权
标题翻译：处理负载正常或快速运行模式
公开(公告)号：US09229767B2
公开(公告)日：2016-01-05
申请号：US14340864
申请日：2014-07-25
申请人： Jean-Luc Robin
发明人： Jean-Luc Robin
IPC分类号： G06F9/48 , G06F1/32 , H04L1/18 , H04W52/02 , G06F9/54
CPC分类号： G06F9/48 , G06F1/3203 , G06F9/54 , H04L1/1854 , H04W52/0261 , Y02D70/00
摘要： A data processing apparatus includes a processing unit having first and second modes of operation for processing data, including receiving data packets from a sender and sending acknowledgements to the sender the second mode of operation requires more power than the first mode, and the processing unit switches between the first and second modes of operation based on a processing load; a metric module for determining a metric indicative of the processing load; an acknowledgement module for sending one acknowledgement in respect of n received data packets; and an acknowledgement configuration module for setting n to be a value m greater than a first predetermined value if the metric lies in a predetermined range that includes a value that the metric assumes when the processing unit switches between the first mode of operation and the second mode of operation, and to the first predetermined value otherwise.
摘要翻译：数据处理装置包括处理单元，该处理单元具有用于处理数据的第一和第二操作模式，包括从发送器接收数据分组，并向发送方发送确认，第二操作模式需要比第一模式更多的功率，并且处理单元切换基于处理负载在第一和第二操作模式之间; 用于确定指示处理负载的度量的度量模块; 确认模块，用于发送关于n个接收到的数据分组的一个确认; 以及确认配置模块，用于如果所述度量位于包括当所述处理单元在所述第一操作模式和所述第二模式之间切换时所述度量所采用的值的预定范围内，则将n设置为大于第一预定值的值m 的操作，否则为第一预定值。

210. 发明申请

US20150380513A1 BIPOLAR TRANSISTOR DEVICE FABRICATION METHODS 有权
标题翻译：双极晶体管器件制造方法
公开(公告)号：US20150380513A1
公开(公告)日：2015-12-31
申请号：US14844608
申请日：2015-09-03
申请人： Xin Lin , Daniel J. Blomberg , Jiang-Kai Zuo
发明人： Xin Lin , Daniel J. Blomberg , Jiang-Kai Zuo
IPC分类号： H01L29/66 , H01L21/265 , H01L21/762 , H01L29/10 , H01L21/266 , H01L29/06 , H01L29/08
CPC分类号： H01L29/6625 , H01L21/26513 , H01L21/266 , H01L21/76224 , H01L29/0649 , H01L29/08 , H01L29/0808 , H01L29/0821 , H01L29/1008 , H01L29/735
摘要： A method of fabricating a bipolar transistor device includes performing a first plurality of implantation procedures to implant dopant of a first conductivity type to form emitter and collector regions laterally spaced from one another in a semiconductor substrate, and performing a second plurality of implantation procedures to implant dopant of a second conductivity type in the semiconductor substrate to form a composite base region. The composite base region includes a base contact region, a buried region through which a buried conduction path between the emitter and collector regions is formed during operation, and a base link region electrically connecting the base contact region and the buried region. The base link region has a dopant concentration level higher than the buried region and is disposed laterally between the emitter and collector regions.
摘要翻译：一种制造双极晶体管器件的方法包括：执行第一多个注入步骤以注入第一导电类型的掺杂剂，以形成在半导体衬底中彼此横向隔开的发射极和集电极区，以及执行第二多个植入步骤以植入半导体衬底中的第二导电类型的掺杂剂以形成复合基极区域。复合基极区域包括基极接触区域，在工作期间形成发射极和集电极区域之间的掩埋传导路径的掩埋区域和电连接基极接触区域和掩埋区域的基极连接区域。基极区域的掺杂剂浓度水平高于掩埋区域，并且横向设置在发射极和集电极区域之间。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式