专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09236795B2 Voltage generator with ramp rate control 有权
标题翻译：电压发生器，具有斜坡率控制
公开(公告)号：US09236795B2
公开(公告)日：2016-01-12
申请号：US14182702
申请日：2014-02-18
申请人： Perry H. Pelley , Michael G. Neaves
发明人： Perry H. Pelley , Michael G. Neaves
IPC分类号： G05F1/10 , H02M3/07
CPC分类号： H02M3/07 , H02M2001/0003
摘要： A charge pump system includes a comparator having a first input coupled to a first reference voltage, a second input coupled to a feedback signal and an output coupled to control operation of a voltage controlled oscillator. The feedback signal is coupled to an output of the charge pump system. An amplifier has a first input coupled to a second reference voltage, a second input coupled to the feedback signal, and an output coupled as input to the voltage controlled oscillator. A gain of the amplifier is lower than a gain of the comparator.
摘要翻译：电荷泵系统包括具有耦合到第一参考电压的第一输入的比较器，耦合到反馈信号的第二输入和耦合到控制压控振荡器的操作的输出。反馈信号耦合到电荷泵系统的输出端。放大器具有耦合到第二参考电压的第一输入，耦合到反馈信号的第二输入和耦合到压控振荡器的输入的输出。放大器的增益低于比较器的增益。

2. 发明申请

US20150236584A1 VOLTAGE GENERATOR WITH RAMP RATE CONTROL 有权
标题翻译：具有RAV控制的电压发生器
公开(公告)号：US20150236584A1
公开(公告)日：2015-08-20
申请号：US14182702
申请日：2014-02-18
申请人： Perry H. Pelley , Michael G. Neaves
发明人： Perry H. Pelley , Michael G. Neaves
IPC分类号： H02M3/07
CPC分类号： H02M3/07 , H02M2001/0003
摘要： A charge pump system includes a comparator having a first input coupled to a first reference voltage, a second input coupled to a feedback signal and an output coupled to control operation of a voltage controlled oscillator. The feedback signal is coupled to an output of the charge pump system. An amplifier has a first input coupled to a second reference voltage, a second input coupled to the feedback signal, and an output coupled as input to the voltage controlled oscillator. A gain of the amplifier is lower than a gain of the comparator.
摘要翻译：电荷泵系统包括具有耦合到第一参考电压的第一输入的比较器，耦合到反馈信号的第二输入和耦合到控制压控振荡器的操作的输出。反馈信号耦合到电荷泵系统的输出端。放大器具有耦合到第二参考电压的第一输入，耦合到反馈信号的第二输入和耦合到压控振荡器的输入的输出。放大器的增益低于比较器的增益。

3. 发明授权

US08917136B1 Charge pump system and method of operation 有权
标题翻译：电荷泵系统及操作方法
公开(公告)号：US08917136B1
公开(公告)日：2014-12-23
申请号：US14151886
申请日：2014-01-10
申请人： Perry H. Pelley , Michael G. Neaves , Ravindraraj Ramaraju
发明人： Perry H. Pelley , Michael G. Neaves , Ravindraraj Ramaraju
IPC分类号： G05F1/10 , H02M3/07
CPC分类号： H02M3/07 , H02M1/36
摘要： A charge pump system includes a charge pump, a switchable impedance, a comparator, and a capacitor. The switchable impedance has an input coupled to the output of the charge pump. The comparator has a first input coupled to the output of the switchable impedance, a second input coupled to a reference, and an output coupled to the input of the charge pump. The capacitor has a first terminal coupled to the output of the charge pump and a second terminal coupled to the first input of the comparator. The switchable impedance causes a first impedance between the first and second terminals of the capacitor during a start-up operation of the charge pump system and a second impedance between the first and second terminals of the capacitor during a steady-state operation of the charge pump system, wherein the first impedance is lower than the second impedance.
摘要翻译：电荷泵系统包括电荷泵，可切换阻抗，比较器和电容器。可切换阻抗具有耦合到电荷泵的输出的输入。比较器具有耦合到可切换阻抗的输出的第一输入，耦合到基准的第二输入和耦合到电荷泵的输入的输出。电容器具有耦合到电荷泵的输出的第一端子和耦合到比较器的第一输入端的第二端子。可切换阻抗在电荷泵系统的启动操作期间引起电容器的第一和第二端子之间的第一阻抗，以及在电荷泵的稳态操作期间电容器的第一和第二端子之间的第二阻抗系统，其中第一阻抗低于第二阻抗。

4. 发明授权

US09672938B2 Memory with redundancy 有权
公开(公告)号：US09672938B2
公开(公告)日：2017-06-06
申请号：US14258730
申请日：2014-04-22
申请人： George P. Hoekstra , Perry H. Pelley , Ravindraraj Ramaraju
发明人： George P. Hoekstra , Perry H. Pelley , Ravindraraj Ramaraju
IPC分类号： G11C7/00 , G11C29/44 , G11C29/00 , G11C29/12
CPC分类号： G11C29/44 , G11C29/12 , G11C29/83
摘要： Structures for substituting single bits in an array may include a first array having a plurality of word lines, and for each of the plurality of word lines a memory operable to store a bit substitution column value, and a first data output line operable to communicate the bit substitution column value to a write data shifter. The bit substitution column value may be associated with a bit substitution column in a second array, and the write data shifter may be operable to substitute the bit by shifting data to a redundancy column in the first array.

5. 发明申请

US20150244375A1 TEMPERATURE THRESHOLD CIRCUIT WITH HYSTERESIS 有权
标题翻译：具有迟滞的温度阈值电路
公开(公告)号：US20150244375A1
公开(公告)日：2015-08-27
申请号：US14191684
申请日：2014-02-27
申请人： Perry H. Pelley , George P. Hoekstra , Ravindraraj Ramaraju
发明人： Perry H. Pelley , George P. Hoekstra , Ravindraraj Ramaraju
IPC分类号： H03K21/10 , G01K7/00
CPC分类号： H03K21/10 , G01K1/028 , G01K3/005 , G01K7/32 , G01K13/002 , H03K21/38
摘要： A circuit for determining a threshold indication of temperature with respect to a threshold temperature. The circuit includes a timer circuit and a temperature sensor circuit having an counter whose output has a relationship to temperature. At the end of a period determined by the timer circuit, a comparator circuit compares the count of the counter with an indication of the threshold temperature to determine a state of the threshold indication. In response to a change in state of the threshold indication, the circuit changes one of the count time or the counter output's relationship to temperature to provide a hysteresis for the threshold indication.
摘要翻译：一种用于确定相对于阈值温度的温度阈值指示的电路。电路包括定时器电路和具有计数器的温度传感器电路，其计数器的输出与温度有关。在由定时器电路确定的周期结束时，比较器电路将计数器的计数与阈值温度的指示进行比较，以确定阈值指示的状态。响应于阈值指示的状态改变，电路将计数时间或计数器输出与温度的关系改变，以提供阈值指示的滞后。

6. 发明授权

US09111634B2 Methods and structures for multiport memory devices 有权
标题翻译：多端口存储器件的方法和结构
公开(公告)号：US09111634B2
公开(公告)日：2015-08-18
申请号：US13548843
申请日：2012-07-13
申请人： Perry H. Pelley , James D. Burnett
发明人： Perry H. Pelley , James D. Burnett
IPC分类号： H01L23/522 , G11C11/412 , G11C7/18 , G11C7/02 , G11C5/06 , G11C8/16 , H01L21/8228
CPC分类号： H01L27/11 , G11C5/063 , G11C7/02 , G11C7/18 , G11C8/16 , G11C11/412 , H01L21/768 , H01L21/8228 , H01L23/5226 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A memory device includes a storage unit formed using a substrate, a true bit line BL0 for carrying a bit of data, and a complementary bit line for carrying the bit of data carried by the first true bit line in complementary form. The true bit line is coupled to the storage unit and runs laterally over the substrate. The true bit line and the complementary bit line are adjacent to each other and are vertically stacked above the substrate.
摘要翻译：存储器件包括使用衬底形成的存储单元，用于承载数据位的真位线BL0以及用于承载第一真位位线所携带的数据位的互补位线的互补位线。真正的位线耦合到存储单元并横向延伸到衬底上。真位线和互补位线彼此相邻并且垂直地堆叠在衬底上。

7. 发明授权

US09099475B2 Techniques for reducing inductance in through-die vias of an electronic assembly 有权
标题翻译：降低电子组件通孔的电感的技术
公开(公告)号：US09099475B2
公开(公告)日：2015-08-04
申请号：US13611076
申请日：2012-09-12
申请人： Michael B. McShane , Kevin J. Hess , Perry H. Pelley , Tab A. Stephens
发明人： Michael B. McShane , Kevin J. Hess , Perry H. Pelley , Tab A. Stephens
IPC分类号： H05K1/00 , H05K7/00 , G02B6/12 , H01L23/02 , H01L23/48 , G11C5/06 , H01L23/538 , H01L25/04 , H01L25/065 , H01L23/00
CPC分类号： H01L23/48 , H01L23/538 , H01L24/16 , H01L24/24 , H01L24/32 , H01L24/73 , H01L24/82 , H01L25/04 , H01L25/0657 , H01L2224/131 , H01L2224/16146 , H01L2224/24146 , H01L2224/245 , H01L2224/2518 , H01L2224/32135 , H01L2224/73217 , H01L2224/73259 , H01L2224/8203 , H01L2224/82101 , H01L2224/83 , H01L2224/9202 , H01L2224/92144 , H01L2224/94 , H01L2224/97 , H01L2225/06541 , H01L2924/00014 , H01L2924/01079 , H01L2924/01029 , H01L2924/01013 , H01L2224/81 , H01L2924/014
摘要： An electronic assembly includes a processor die assembly, a first die assembly, and a second die assembly. The first die assembly is positioned on a first side of the processor die assembly. The second die assembly is positioned on a second side of the processor die assembly opposite the first side of the processor die assembly. Through-die vias couple the first and second die assemblies to the processor die assembly.
摘要翻译：电子组件包括处理器模具组件，第一模具组件和第二模具组件。第一模具组件定位在处理器模具组件的第一侧上。第二模具组件位于处理器模具组件的与处理器模具组件的第一侧相对的第二侧。通孔将第一和第二模具组件耦合到处理器模具组件。

8. 发明申请

US20140321185A1 FOUR PORT MEMORY WITH MULTIPLE CORES 有权
标题翻译：四端口存储器与多个CORES
公开(公告)号：US20140321185A1
公开(公告)日：2014-10-30
申请号：US13873998
申请日：2013-04-30
申请人： Perry H. Pelley , Peter J. Wilson
发明人： Perry H. Pelley , Peter J. Wilson
IPC分类号： G11C5/02 , G11C5/06
CPC分类号： G11C5/025 , G11C5/02 , G11C7/1075 , G11C8/16
摘要： A memory cluster includes a first block, a second block, a third block, and a fourth block arranged to have a center hole, wherein the first, second, third, and fourth blocks are each have a first port, a second port, a third port, and a fourth port. A first core is in the center hole coupled to the first port of each of the first, second, third, and fourth blocks. A second core is in the center hole coupled to the second port of each of the first, second, third, and fourth blocks. A third core is in the center hole coupled to the third port of each of the first, second, third, and fourth blocks. A fourth core in the center hole coupled to the fourth port of each of the first, second, third, and fourth blocks.
摘要翻译：存储器簇包括布置成具有中心孔的第一块，第二块，第三块和第四块，其中第一块，第二块，第三块和第四块每个都具有第一端口，第二端口，第三个港口和第四个港口。第一芯在中心孔中，耦合到第一，第二，第三和第四块中的每一个的第一端口。第二芯在与第一，第二，第三和第四块中的每一个的第二端口连接的中心孔中。第三芯在中心孔中，连接到第一，第二，第三和第四块中的每一个的第三端口。中心孔中的第四个核心耦合到第一，第二，第三和第四块中的每一个的第四端口。

9. 发明授权

US08861289B2 Multiport memory with matching address control 有权
标题翻译：具有匹配地址控制的多端口存储器
公开(公告)号：US08861289B2
公开(公告)日：2014-10-14
申请号：US13740868
申请日：2013-01-14
申请人： Perry H. Pelley
发明人： Perry H. Pelley
IPC分类号： G11C7/00 , G11C8/16 , G11C7/10
CPC分类号： G11C8/16 , G11C7/00 , G11C7/10 , G11C11/412 , G11C11/413
摘要： In a multiple port SRAM, a first bit cell is coupled to first and second word lines and a first and second bit line pair. A second bit cell is coupled to the first and second word lines and a third and fourth bit line pair. A first data line pair is coupled to the first bit line pair via first switching logic and to the third bit line pair via second switching logic, and a second data line pair is coupled to the second bit line pair via third switching logic and to the fourth bit line pair via fourth switching logic. If a match exists between at least portions of a first and second access address, a state of the third and forth switching logic is set such that the second bit line pair and the fourth bit line pair remains decoupled from the second data line pair.
摘要翻译：在多端口SRAM中，第一位单元耦合到第一和第二字线以及第一和第二位线对。第二位单元耦合到第一和第二字线以及第三和第四位线对。第一数据线对经由第一开关逻辑经由第一开关逻辑耦合到第一位线对，并经由第二开关逻辑耦合到第三位线对，并且第二数据线对经由第三开关逻辑耦合到第二位线对，并且耦合到第第四位线对经由第四切换逻辑。如果在第一和第二访问地址的至少部分之间存在匹配，则设置第三和第四切换逻辑的状态使得第二位线对和第四位线对保持与第二数据线对解耦。

10. 发明授权

US08861243B1 Four port memory with multiple cores 有权
标题翻译：具有多个内核的四端口内存
公开(公告)号：US08861243B1
公开(公告)日：2014-10-14
申请号：US13873998
申请日：2013-04-30
申请人： Perry H. Pelley , Peter J. Wilson
发明人： Perry H. Pelley , Peter J. Wilson
IPC分类号： G11C5/02 , G11C5/06
CPC分类号： G11C5/025 , G11C5/02 , G11C7/1075 , G11C8/16
摘要： A memory cluster includes a first block, a second block, a third block, and a fourth block arranged to have a center hole, wherein the first, second, third, and fourth blocks are each have a first port, a second port, a third port, and a fourth port. A first core is in the center hole coupled to the first port of each of the first, second, third, and fourth blocks. A second core is in the center hole coupled to the second port of each of the first, second, third, and fourth blocks. A third core is in the center hole coupled to the third port of each of the first, second, third, and fourth blocks. A fourth core in the center hole coupled to the fourth port of each of the first, second, third, and fourth blocks.
摘要翻译：存储器簇包括布置成具有中心孔的第一块，第二块，第三块和第四块，其中第一块，第二块，第三块和第四块每个都具有第一端口，第二端口，第三个港口和第四个港口。第一芯在中心孔中，耦合到第一，第二，第三和第四块中的每一个的第一端口。第二芯在与第一，第二，第三和第四块中的每一个的第二端口连接的中心孔中。第三芯在中心孔中，连接到第一，第二，第三和第四块中的每一个的第三端口。中心孔中的第四个核心耦合到第一，第二，第三和第四块中的每一个的第四端口。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式