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11. 发明申请

US20120072704A1 "OR" BIT MATRIX MULTIPLY VECTOR INSTRUCTION 审中-公开
标题翻译： “OR”位矩阵乘法器指令
公开(公告)号：US20120072704A1
公开(公告)日：2012-03-22
申请号：US13020358
申请日：2011-02-03
申请人： Timothy J. Johnson , Gregory J. Faanes
发明人： Timothy J. Johnson , Gregory J. Faanes
IPC分类号： G06F9/305
CPC分类号： G06F17/16 , G06F7/724 , G06F9/30021 , G06F9/30029 , G06F9/30036
摘要： A processor is operable to execute a bit matrix multiply instruction. In further examples, the processor is operable to perform a vector bit matrix multiply instruction, and is a part of a computerized system.
摘要翻译：处理器可操作以执行位矩阵乘法指令。在另外的示例中，处理器可操作以执行向量比特矩阵乘法指令，并且是计算机化系统的一部分。

12. 发明申请

US20120030451A1 PARALLEL AND LONG ADAPTIVE INSTRUCTION SET ARCHITECTURE 审中-公开
标题翻译：并行和长期适应性指导设置架构
公开(公告)号：US20120030451A1
公开(公告)日：2012-02-02
申请号：US12855981
申请日：2010-08-13
申请人： Fong PONG , Kwong-Tak CHUI , Chun NING , Patrick LAU
发明人： Fong PONG , Kwong-Tak CHUI , Chun NING , Patrick LAU
IPC分类号： G06F9/30 , H03M13/09 , G06F11/10 , G06F9/305
CPC分类号： H03M13/096 , G06F9/30007 , G06F9/30018 , G06F9/30021 , G06F9/30029 , G06F9/30032 , G06F9/30043 , G06F9/30072 , G06F9/3867 , G06F9/3895 , H03M13/09
摘要： An Parallel and Long Adaptive Instruction Set Architecture (PALADIN) is provided to optimize packet processing. The Instruction Set Architecture (ISA) includes instructions such as aggregate comparison, comparison OR, comparison AND and bitwise instructions. The ISA also includes dedicated packet processing instructions such as hash, predicate, select, checksum and time to live adjust, move header left, post, move header left/right and load/store header/status.
摘要翻译：提供并行和长度自适应指令集架构（PALADIN）来优化数据包处理。指令集架构（ISA）包括诸如聚合比较，比较OR，比较AND和按位指令之类的指令。 ISA还包括专用的数据包处理指令，例如散列，谓词，选择，校验和和时间进行调整，向左移动头，向左/向右移动标题，并加载/存储标题/状态。

13. 发明申请

US20120030448A1 SINGLE INSTRUCTION MULTIPLE DATE (SIMD) PROCESSOR HAVING A PLURALITY OF PROCESSING ELEMENTS INTERCONNECTED BY A RING BUS 审中-公开
标题翻译：具有多个处理元件的单个指令多个日期（SIMD）处理器由环形总线互连
公开(公告)号：US20120030448A1
公开(公告)日：2012-02-02
申请号：US13203809
申请日：2009-09-25
申请人： Hanno Lieske
发明人： Hanno Lieske
IPC分类号： G06F9/30 , G06F9/315 , G06F9/305
CPC分类号： G06F15/8015 , G06F15/163 , G06F15/17337 , H04N5/44 , H04N19/107 , H04N19/436 , H04N19/44 , H04N19/61 , H04N19/86
摘要： A single instruction multiple data (SIMD) processor having a plurality of processing elements and including: a splitting unit for splitting an address of the read-only parameter data in the data memory into a first part and a second part at a bit position corresponding to the number of the processor elements; and a comparing unit for comparing the number of shifting, on a ring bus, of the read-only parameter data, which is taken from the internal memory at the address in accordance with the first part, with a difference between an own processor element position and a portion of the global address of the read-only parameter data to be accessed, the portion designating a position in the ring of the processor element in which the read-only parameter data to be accessed is stored and corresponding to the second part, to cause the other processor elements to take the read-only parameter data.
摘要翻译：一种具有多个处理元件的单指令多数据（SIMD）处理器，包括：分割单元，用于将数据存储器中的只读参数数据的地址分割成与第一部分和第二部分相对应的比特位置处理器元件的数量; 以及比较单元，用于比较在环形总线上从根据第一部分的地址处的内部存储器获取的只读参数数据与自身处理器单元位置之间的差异以及要访问的只读参数数据的全局地址的一部分，指定处理器元件的环中的位置的部分，其中存储要访问的只读参数数据并对应于第二部分，以使其他处理器元件采用只读参数数据。

14. 发明申请

US20110314263A1 INSTRUCTIONS FOR PERFORMING AN OPERATION ON TWO OPERANDS AND SUBSEQUENTLY STORING AN ORIGINAL VALUE OF OPERAND 审中-公开
标题翻译：执行两个操作的操作说明，以及随后存储操作的原始值
公开(公告)号：US20110314263A1
公开(公告)日：2011-12-22
申请号：US12820768
申请日：2010-06-22
申请人： Dan F. Greiner , Marcel Mitran , Timothy J. Slegel
发明人： Dan F. Greiner , Marcel Mitran , Timothy J. Slegel
IPC分类号： G06F9/302 , G06F9/305
CPC分类号： G06F9/30145 , G06F9/3001 , G06F9/30029 , G06F9/3004 , G06F9/30087 , G06F9/30167
摘要： An arithmetic/logical instruction is executed having interlocked memory operands. when executed obtains a second operand from a location in memory, and saves a temporary copy of the second operand, the execution performs an arithmetic or logical operation based on the second operand and a third operand and stores the result in the memory location of the second operand, and subsequently stores the temporary copy in a first register.
摘要翻译：执行具有互锁的存储器操作数的算术/逻辑指令。当执行从存储器中的位置获得第二操作数并且保存第二操作数的临时副本时，执行基于第二操作数和第三操作数执行算术或逻辑操作，并将结果存储在第二操作数的存储位置中操作数，然后将临时副本存储在第一个寄存器中。

15. 发明申请

US20110035570A1 MICROPROCESSOR WITH ALU INTEGRATED INTO STORE UNIT 有权
标题翻译：微处理器与ALU集成到存储单元
公开(公告)号：US20110035570A1
公开(公告)日：2011-02-10
申请号：US12609193
申请日：2009-10-30
申请人： Gerard M. Col , Colin Eddy , Rodney E. Hooker
发明人： Gerard M. Col , Colin Eddy , Rodney E. Hooker
IPC分类号： G06F9/30 , G06F12/08 , G06F9/302 , G06F9/305
CPC分类号： G06F9/3875 , G06F9/3001 , G06F9/3004 , G06F9/30043 , G06F9/30145 , G06F9/3017 , G06F9/3893 , G06F12/0875
摘要： A superscalar pipelined microprocessor includes a register set defined by an instruction set architecture of the microprocessor, execution units, and a store unit, coupled to the cache memory and distinct from the other execution units of the microprocessor. The store unit comprises an ALU. The store unit receives an instruction that specifies a source register of the register set and an operation to be performed on a source operand to generate a result. The store unit reads the source operand from the source register. The ALU performs the operation on the source operand to generate the result, rather than forwarding the source operand to any of the other execution units of the microprocessor to perform the operation on the source operand to generate the result. The store unit operatively writes the result to the cache memory.
摘要翻译：超标量流水线微处理器包括由微处理器的指令集架构定义的寄存器组，执行单元和存储单元，其耦合到高速缓冲存储器并且与微处理器的其他执行单元不同。存储单元包括ALU。存储单元接收指定寄存器组的源寄存器和要对源操作数执行的操作以产生结果的指令。存储单元从源寄存器读取源操作数。 ALU对源操作数执行操作以生成结果，而不是将源操作数转发到微处理器的任何其他执行单元，以对源操作数执行操作以生成结果。存储单元可操作地将结果写入缓存存储器。

16. 发明申请

US20100223444A1 METHOD FOR PERFORMING PLURALITY OF BIT OPERATIONS AND A DEVICE HAVING PLURALITY OF BIT OPERATIONS CAPABILITIES 有权
标题翻译：执行双工操作的多样性的方法和具有多重位操作能力的设备
公开(公告)号：US20100223444A1
公开(公告)日：2010-09-02
申请号：US12377351
申请日：2006-08-18
申请人： Eran Glickman , Evgeni Ginzburg , Noam Sheffer
发明人： Eran Glickman , Evgeni Ginzburg , Noam Sheffer
IPC分类号： G06F9/30 , G06F9/44 , G06F9/302 , G06F9/305
CPC分类号： G06F9/30018 , G06F9/3001
摘要： A method and a device having a plurality of bit operations capability, the device includes: a first and a second registers and an instruction fetch circuit, and an arithmetic logic unit adapted to: calculate, during a first clock cycle, a position value representative of a position, within a first information vector, of a first bit of information that has a first value; and to multiply the position value by a multiplication factor to provide a first result and to alter the value of the first bit to a second value to provide an updated information vector, during the first clock cycle.
摘要翻译：一种具有多个位操作能力的方法和装置，所述装置包括：第一和第二寄存器和指令获取电路，以及算术逻辑单元，适于：在第一时钟周期期间，计算代表在第一信息向量内的具有第一值的第一位信息的位置; 并且在第一时钟周期期间将位置值乘以乘法因子以提供第一结果并将第一位的值改变为第二值以提供更新的信息向量。

17. 发明授权

US07752424B2 Null value checking instruction 有权
标题翻译：空值检查指令
公开(公告)号：US07752424B2
公开(公告)日：2010-07-06
申请号：US11889058
申请日：2007-08-08
申请人： Rodolph Gérard Jacques Ascanio Jean-Denis Perfetta
发明人： Rodolph Gérard Jacques Ascanio Jean-Denis Perfetta
IPC分类号： G06F9/305
CPC分类号： G06F9/30021 , G06F9/30058 , G06F9/30134
摘要： A processor 2 is provided with the ability to execute program instructions in the form of Java bytecodes including a dedicated null checking instruction. The null checking instruction reads the top of stack value, compares this with a null value and jumps to an exception handling routine if the top of stack value equals the null value, otherwise the next program instruction is executed.
摘要翻译：处理器2具有执行包括专用空检查指令的Java字节码形式的程序指令的能力。空检查指令读取堆栈值的顶部，将其与空值进行比较，如果堆栈值的顶部值等于空值，则跳转到异常处理例程，否则执行下一个程序指令。

18. 发明申请

US20100138774A1 SYSTEM AND METHOD FOR PROCESSING FLOW CYTOMETRY DATA 审中-公开
标题翻译：用于处理流动细胞计数数据的系统和方法
公开(公告)号：US20100138774A1
公开(公告)日：2010-06-03
申请号：US12447532
申请日：2007-10-30
申请人： Nicholas Daryl Crosbie , Vittorio Cordioli
发明人： Nicholas Daryl Crosbie , Vittorio Cordioli
IPC分类号： G06F9/305 , G06F3/048
CPC分类号： G01N35/00722 , G01N2015/008 , G01N2015/1006 , G01N2015/1402 , G01N2035/00891
摘要： A computer-implemented method for processing multivariate data, comprising: inputting or receiving an alphanumeric expression comprising at least one process pointer, indicative of a gating process, a Boolean process or an external process; parsing the expression; executing the process indicated by the process pointer on multivariate data in a data file; and outputting output data comprising the multivariate data processed according to the expression.
摘要翻译：一种用于处理多变量数据的计算机实现的方法，包括：输入或接收包括指示门控过程，布尔过程或外部过程的至少一个过程指针的字母数字表达; 解析表达式; 对数据文件中的多变量数据执行由过程指针指示的过程; 以及输出包括根据表达式处理的多变量数据的输出数据。

19. 发明申请

US20090249041A1 SYSTEM AND METHOD FOR REDUCING POWER CONSUMPTION IN A DEVICE USING REGISTER FILES 有权
标题翻译：使用寄存器文件在设备中降低功耗的系统和方法
公开(公告)号：US20090249041A1
公开(公告)日：2009-10-01
申请号：US12057685
申请日：2008-03-28
申请人： Satish Damaraju , Scott Siers , Omar Malik
发明人： Satish Damaraju , Scott Siers , Omar Malik
IPC分类号： G06F1/04 , G06F9/305
CPC分类号： G06F9/30141
摘要： A device and method for reducing the power consumption of an electronic device using register file with bypass mechanism. The width of a pulse controlling the word write operation may be extended twice as long so that the extended portion substantially overlaps a following word read pulse. The extension of the pulse width of the read operation may enable lowering the Vcc Min value for the electronic device and thus may lower the power consumption of the device.
摘要翻译：一种使用具有旁路机构的寄存器文件降低电子装置的功耗的装置和方法。控制字写入操作的脉冲的宽度可以延长两倍，使得延伸部分基本上与接续字读取脉冲重叠。读取操作的脉冲宽度的扩展可以使电子设备的Vcc最小值降低，从而可能降低设备的功耗。

20. 发明申请

US20090222393A1 EFFICIENT DECISION PROCEDURE FOR BOUNDED INTEGER NON-LINEAR OPERATIONS USING SMT(LIA) 有权
标题翻译：使用SMT（LIA）的边界整数非线性运算的有效决策程序
公开(公告)号：US20090222393A1
公开(公告)日：2009-09-03
申请号：US12331325
申请日：2008-12-09
申请人： Malay K. Ganai
发明人： Malay K. Ganai
IPC分类号： G06N5/02 , G06F9/305 , G06F7/57
CPC分类号： G06F17/11
摘要： Systems and methods are disclosed for deciding a satisfiability problem with linear and non-linear operations by: encoding non-linear integer operations into encoded linear operations with Boolean constraints by Booleaning and linearizing, combining the linear and encoded linear operations into a formula, solving the satisifiability of the formula using a solver, wherein the encoding and solving includes at least one of following: a. Booleanizing one of the non-linear operands by bit-wise structural decomposition b. Linearizing a non-linear operator by selectively choosing one of the operands for Booleanization c. Solving using an incremental lazy bounding refinement (LBR) procedure without re-encoding formula, and verifying the linear and non-linear operations in a computer software.
摘要翻译：公开了用于通过以下方式来确定线性和非线性操作的可满足性问题的系统和方法：通过布莱恩和线性化将非线性整数运算编码为具有布尔约束的编码线性运算，将线性和编码线性运算组合成公式，使用求解器的公式的令人满意的，其中编码和求解包括以下中的至少一个：a。通过逐位结构分解布尔化非线性操作数之一b。通过选择一个布尔化操作数来对非线性运算符进行线性化c。使用增量懒惰边界细化（LBR）过程解决，而无需重新编码公式，并验证计算机软件中的线性和非线性操作。

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