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1. 发明授权

US08356202B2 System and method for reducing power consumption in a device using register files 有权
标题翻译：使用寄存器文件降低设备功耗的系统和方法
公开(公告)号：US08356202B2
公开(公告)日：2013-01-15
申请号：US12057685
申请日：2008-03-28
申请人： Satish Damaraju , Scott Siers , Omar Malik
发明人： Satish Damaraju , Scott Siers , Omar Malik
IPC分类号： G06F1/04 , G06F1/26 , G11C7/10
CPC分类号： G06F9/30141
摘要： A device and method for reducing the power consumption of an electronic device using register file with bypass mechanism. The width of a pulse controlling the word write operation may be extended twice as long so that the extended portion substantially overlaps a following word read pulse. The extension of the pulse width of the read operation may enable lowering the Vcc Min value for the electronic device and thus may lower the power consumption of the device.
摘要翻译：一种使用具有旁路机构的寄存器文件降低电子装置的功耗的装置和方法。控制字写入操作的脉冲的宽度可以延长两倍，使得延伸部分基本上与接续字读取脉冲重叠。读取操作的脉冲宽度的扩展可以使电子设备的Vcc最小值降低，从而可能降低设备的功耗。

2. 发明申请

US20090249041A1 SYSTEM AND METHOD FOR REDUCING POWER CONSUMPTION IN A DEVICE USING REGISTER FILES 有权
标题翻译：使用寄存器文件在设备中降低功耗的系统和方法
公开(公告)号：US20090249041A1
公开(公告)日：2009-10-01
申请号：US12057685
申请日：2008-03-28
申请人： Satish Damaraju , Scott Siers , Omar Malik
发明人： Satish Damaraju , Scott Siers , Omar Malik
IPC分类号： G06F1/04 , G06F9/305
CPC分类号： G06F9/30141
摘要： A device and method for reducing the power consumption of an electronic device using register file with bypass mechanism. The width of a pulse controlling the word write operation may be extended twice as long so that the extended portion substantially overlaps a following word read pulse. The extension of the pulse width of the read operation may enable lowering the Vcc Min value for the electronic device and thus may lower the power consumption of the device.
摘要翻译：一种使用具有旁路机构的寄存器文件降低电子装置的功耗的装置和方法。控制字写入操作的脉冲的宽度可以延长两倍，使得延伸部分基本上与接续字读取脉冲重叠。读取操作的脉冲宽度的扩展可以使电子设备的Vcc最小值降低，从而可能降低设备的功耗。

3. 发明授权

US09490807B2 Power reducing logic and non-destructive latch circuits and applications 有权
公开(公告)号：US09490807B2
公开(公告)日：2016-11-08
申请号：US13467171
申请日：2012-05-09
申请人： Hon Shing Lau , Scott Siers , Ruchira Liyanage
发明人： Hon Shing Lau , Scott Siers , Ruchira Liyanage
IPC分类号： H03K19/096 , H03K19/00
CPC分类号： H03K19/0016
摘要： In some embodiments, a logic circuit is provided that has a plurality of gates with gate inputs. Also provided is one or more latch circuits coupled to the logic circuit to provide operational data when in an operational mode and to cause at least some of the gate inputs to be at values resulting in reduced leakage during a sleep mode. Additionally provided are embodiments of non-destructive latch circuits, which may be used to implement the latch circuits just discussed. Other embodiments are disclosed and/or claimed herein.

4. 发明申请

US20050144423A1 Methods and apparatus for address generation in processors 有权
标题翻译：处理器中地址生成的方法和设备
公开(公告)号：US20050144423A1
公开(公告)日：2005-06-30
申请号：US10747764
申请日：2003-12-29
申请人： Rajesh Patel , Robert Farrell , James Phillips , Belliappa Kuttanna , Scott Siers , T.W. Griffith
发明人： Rajesh Patel , Robert Farrell , James Phillips , Belliappa Kuttanna , Scott Siers , T.W. Griffith
IPC分类号： G06F9/355 , G06F9/38 , G06F12/06
CPC分类号： G06F9/342 , G06F9/355 , G06F9/3842 , G06F9/3861
摘要： Methods and apparatus to generate addresses in processors are disclosed. An example address generator disclosed herein includes an adder to add a first address component and a second address component to generate an address, a correction indicator to indicate if the address is correct, and a control input to modify an operation of the adder.
摘要翻译：公开了在处理器中产生地址的方法和装置。本文公开的示例性地址生成器包括：加法器，用于添加第一地址分量和第二地址分量以产生地址;校正指示符，用于指示地址是否正确;以及控制输入，用于修改加法器的操作。

5. 发明申请

US20120223741A1 POWER REDUCING LOGIC AND NON-DESTRUCTIVE LATCH CIRCUITS AND APPLICATIONS 有权
标题翻译：减少电力和非破坏性电缆及其应用
公开(公告)号：US20120223741A1
公开(公告)日：2012-09-06
申请号：US13467171
申请日：2012-05-09
申请人： Hon Shing Lau , Scott Siers , Ruchira Liyanage
发明人： Hon Shing Lau , Scott Siers , Ruchira Liyanage
IPC分类号： H03K19/00
CPC分类号： H03K19/0016
摘要： In some embodiments, a logic circuit is provided that has a plurality of gates with gate inputs. Also provided is one or more latch circuits coupled to the logic circuit to provide operational data when in an operational mode and to cause at least some of the gate inputs to be at values resulting in reduced leakage during a sleep mode. Additionally provided are embodiments of non-destructive latch circuits, which may be used to implement the latch circuits just discussed. Other embodiments are disclosed and/or claimed herein.
摘要翻译：在一些实施例中，提供了具有多个具有栅极输入的栅极的逻辑电路。还提供了一个或多个锁存电路，其耦合到逻辑电路以在处于操作模式时提供操作数据，并且使至少一些栅极输入处于导致睡眠模式期间减少的泄漏的值。另外提供了非破坏性锁存电路的实施例，其可以用于实现刚刚讨论的锁存电路。在此公开和/或要求保护的其它实施例。

6. 发明授权

US06035318A Booth multiplier for handling variable width operands 失效
标题翻译：用于处理可变宽度操作数的展位乘数
公开(公告)号：US06035318A
公开(公告)日：2000-03-07
申请号：US50993
申请日：1998-03-31
申请人： Mohammad Abdallah , Scott Siers
发明人： Mohammad Abdallah , Scott Siers
IPC分类号： G06F7/52 , G06F7/38
CPC分类号： G06F7/5338 , G06F2207/382 , G06F2207/3828
摘要： A circuit for generating partial products for variable width multiplication operations is provided. According to an embodiment of the present invention, the circuit includes a plurality of partial product selector groups, each partial product selector group includes a plurality of partial product selector circuits. Each partial product selector circuit receives a portion of a multiplicand as an input and outputs a partial product. The circuit also includes a plurality of Booth encoders. At least one of the Booth encoders is coupled to each partial product selector group. Each Booth encoder receives as an input a portion of a wide multiplier and outputs a Booth encoded value to at least a portion of a partial product selector group. The circuit further includes an override circuit coupled to one or more of the partial product selector circuits. The override circuit is operable to control one or more of the partial product selector circuits to output a zero to thereby avoid unwanted cross-products when performing multiple smaller multiplications using the same circuit.
摘要翻译：提供了用于产生用于可变宽度乘法运算的部分乘积的电路。根据本发明的实施例，电路包括多个部分乘积选择器组，每个部分乘积选择器组包括多个部分乘积选择器电路。每个部分积选择器电路接收被乘数的一部分作为输入并输出部分乘积。电路还包括多个布斯编码器。至少一个布斯编码器耦合到每个部分产品选择器组。每个布斯编码器作为输入接收宽乘法器的一部分，并将布斯编码值输出到部分乘积选择器组的至少一部分。电路还包括耦合到一个或多个部分积选择器电路的超控电路。超控电路可操作以控制一个或多个部分乘积选择器电路输出零，从而在使用相同电路执行多个更小的乘法时避免不必要的交叉产物。

7. 发明授权

US08305112B2 Power reducing logic and non-destructive latch circuits and applications 有权
标题翻译：降压逻辑和非破坏性锁存电路和应用
公开(公告)号：US08305112B2
公开(公告)日：2012-11-06
申请号：US12847248
申请日：2010-07-30
申请人： Hon Shing Lau , Scott Siers , Ruchira Liyanage
发明人： Hon Shing Lau , Scott Siers , Ruchira Liyanage
IPC分类号： H03K19/096
CPC分类号： H03K19/0016
摘要： In some embodiments, a logic circuit is provided that has a plurality of gates with gate inputs. Also provided is one or more latch circuits coupled to the logic circuit to provide operational data when in an operational mode and to cause at least some of the gate inputs to be at values resulting in reduced leakage during a sleep mode. Additionally provided are embodiments of non-destructive latch circuits, which may be used to implement the latch circuits just discussed. Other embodiments are disclosed and/or claimed herein.
摘要翻译：在一些实施例中，提供了具有多个具有栅极输入的栅极的逻辑电路。还提供了一个或多个锁存电路，其耦合到逻辑电路以在处于操作模式时提供操作数据，并且使至少一些栅极输入处于导致睡眠模式期间减少的泄漏的值。另外提供了非破坏性锁存电路的实施例，其可以用于实现刚刚讨论的锁存电路。在此公开和/或要求保护的其它实施例。

8. 发明申请

US20070103201A1 Power reducing logic and non-destructive latch circuits and applications 有权
标题翻译：降压逻辑和非破坏性锁存电路和应用
公开(公告)号：US20070103201A1
公开(公告)日：2007-05-10
申请号：US11270912
申请日：2005-11-10
申请人： Hon Lau , Scott Siers , Ruchira Liyanage
发明人： Hon Lau , Scott Siers , Ruchira Liyanage
IPC分类号： H03K19/00
CPC分类号： H03K19/0016
摘要： In some embodiments, a logic circuit is provided that has a plurality of gates with gate inputs. Also provided is one or more latch circuits coupled to the logic circuit to provide operational data when in an operational mode and to cause at least some of the gate inputs to be at values resulting in reduced leakage during a sleep mode. Additionally provided are embodiments of non-destructive latch circuits, which may be used to implement the latch circuits just discussed. Other embodiments are disclosed and/or claimed herein.
摘要翻译：在一些实施例中，提供了具有多个具有栅极输入的栅极的逻辑电路。还提供了一个或多个锁存电路，其耦合到逻辑电路以在处于操作模式时提供操作数据，并且使至少一些栅极输入处于导致睡眠模式期间减少的泄漏的值。另外提供了非破坏性锁存电路的实施例，其可以用于实现刚刚讨论的锁存电路。在此公开和/或要求保护的其它实施例。

9. 发明授权

US08421502B2 Power reducing logic and non-destructive latch circuits and applications 有权
标题翻译：降压逻辑和非破坏性锁存电路和应用
公开(公告)号：US08421502B2
公开(公告)日：2013-04-16
申请号：US11270912
申请日：2005-11-10
申请人： Hon Shing Lau , Scott Siers , Ruchira Liyanage
发明人： Hon Shing Lau , Scott Siers , Ruchira Liyanage
IPC分类号： H03K19/00
CPC分类号： H03K19/0016
摘要： In some embodiments, a logic circuit is provided that has a plurality of gates with gate inputs. Also provided is one or more latch circuits coupled to the logic circuit to provide operational data when in an operational mode and to cause at least some of the gate inputs to be at values resulting in reduced leakage during a sleep mode. Additionally provided are embodiments of non-destructive latch circuits, which may be used to implement the latch circuits just discussed. Other embodiments are disclosed and/or claimed herein.
摘要翻译：在一些实施例中，提供了具有多个具有栅极输入的栅极的逻辑电路。还提供了一个或多个锁存电路，其耦合到逻辑电路以在处于操作模式时提供操作数据，并且使至少一些栅极输入处于导致睡眠模式期间减少的泄漏的值。另外提供了非破坏性锁存电路的实施例，其可以用于实现刚刚讨论的锁存电路。在此公开和/或要求保护的其它实施例。

10. 发明申请

US20100289528A1 POWER REDUCING LOGIC AND NON-DESTRUCTIVE LATCH CIRCUITS AND APPLICATIONS 有权
标题翻译：减少电力和非破坏性电缆及其应用
公开(公告)号：US20100289528A1
公开(公告)日：2010-11-18
申请号：US12847248
申请日：2010-07-30
申请人： Hon Shing Lau , Scott Siers , Ruchira Liyanage
发明人： Hon Shing Lau , Scott Siers , Ruchira Liyanage
IPC分类号： H03K19/00
CPC分类号： H03K19/0016
摘要： In some embodiments, a logic circuit is provided that has a plurality of gates with gate inputs. Also provided is one or more latch circuits coupled to the logic circuit to provide operational data when in an operational mode and to cause at least some of the gate inputs to be at values resulting in reduced leakage during a sleep mode. Additionally provided are embodiments of non-destructive latch circuits, which may be used to implement the latch circuits just discussed. Other embodiments are disclosed and/or claimed herein.
摘要翻译：在一些实施例中，提供了具有多个具有栅极输入的栅极的逻辑电路。还提供了一个或多个锁存电路，其耦合到逻辑电路以在处于操作模式时提供操作数据，并且使至少一些栅极输入处于导致睡眠模式期间减少的泄漏的值。另外提供了非破坏性锁存电路的实施例，其可以用于实现刚刚讨论的锁存电路。在此公开和/或要求保护的其它实施例。

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