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1. 发明授权

US08909905B2 Method for performing plurality of bit operations and a device having plurality of bit operations capabilities 有权
标题翻译：用于执行多个比特操作的方法和具有多个比特操作能力的设备
公开(公告)号：US08909905B2
公开(公告)日：2014-12-09
申请号：US12377351
申请日：2006-08-18
申请人： Eran Glickman , Evgeni Ginzburg , Noam Sheffer
发明人： Eran Glickman , Evgeni Ginzburg , Noam Sheffer
IPC分类号： G06F15/00 , G06F7/38 , G06F9/00 , G06F9/44 , G06F9/30
CPC分类号： G06F9/30018 , G06F9/3001
摘要： A method and a device having a plurality of bit operations capability, the device includes: a first and a second registers and an instruction fetch circuit, and an arithmetic logic unit adapted to: calculate, during a first clock cycle, a position value representative of a position, within a first information vector, of a first bit of information that has a first value; and to multiply the position value by a multiplication factor to provide a first result and to alter the value of the first bit to a second value to provide an updated information vector, during the first clock cycle.
摘要翻译：一种具有多个位操作能力的方法和装置，所述装置包括：第一和第二寄存器和指令获取电路，以及算术逻辑单元，适于：在第一时钟周期期间，计算代表在第一信息向量内的具有第一值的第一位信息的位置; 并且在第一时钟周期期间将位置值乘以乘法因子以提供第一结果并将第一位的值改变为第二值以提供更新的信息向量。

2. 发明申请

US20100223444A1 METHOD FOR PERFORMING PLURALITY OF BIT OPERATIONS AND A DEVICE HAVING PLURALITY OF BIT OPERATIONS CAPABILITIES 有权
标题翻译：执行双工操作的多样性的方法和具有多重位操作能力的设备
公开(公告)号：US20100223444A1
公开(公告)日：2010-09-02
申请号：US12377351
申请日：2006-08-18
申请人： Eran Glickman , Evgeni Ginzburg , Noam Sheffer
发明人： Eran Glickman , Evgeni Ginzburg , Noam Sheffer
IPC分类号： G06F9/30 , G06F9/44 , G06F9/302 , G06F9/305
CPC分类号： G06F9/30018 , G06F9/3001
摘要： A method and a device having a plurality of bit operations capability, the device includes: a first and a second registers and an instruction fetch circuit, and an arithmetic logic unit adapted to: calculate, during a first clock cycle, a position value representative of a position, within a first information vector, of a first bit of information that has a first value; and to multiply the position value by a multiplication factor to provide a first result and to alter the value of the first bit to a second value to provide an updated information vector, during the first clock cycle.
摘要翻译：一种具有多个位操作能力的方法和装置，所述装置包括：第一和第二寄存器和指令获取电路，以及算术逻辑单元，适于：在第一时钟周期期间，计算代表在第一信息向量内的具有第一值的第一位信息的位置; 并且在第一时钟周期期间将位置值乘以乘法因子以提供第一结果并将第一位的值改变为第二值以提供更新的信息向量。

3. 发明授权

US09678531B2 Methods and apparatus for adaptive time keeping for multiple timers 有权
公开(公告)号：US09678531B2
公开(公告)日：2017-06-13
申请号：US14180449
申请日：2014-02-14
申请人： Ron Bar , Evgeni Ginzburg , Eran Glickman
发明人： Ron Bar , Evgeni Ginzburg , Eran Glickman
IPC分类号： G06F1/14 , G06F1/04 , G06F9/48
CPC分类号： G06F1/14 , G06F1/04 , G06F9/4825 , G06F9/4881
摘要： A timer distribution module supports multiple timers and comprises: a command decoder arranged to determine expiration times of a plurality of timers; and a timer link list distribution adapter, LLDA, operably coupled to the command decoder. The LLDA is arranged to: receive a time reference from a master clock; receive timer data from the command decoder wherein the timer data comprises at least one timer expiration link list; construct a plurality of timer link lists based on at least one of: the timer expiration link list, at least one configurable timing barrier; dynamically split the link list timer data into a plurality of granularities based on the timer expiration link list; and output the dynamically split link list timer data.

4. 发明申请

US20090274138A1 METHOD FOR TRANSMITTING DATA AND A DEVICE HAVING DATA TRANSMISSION CAPABILITIES 有权
标题翻译：发送数据的方法和具有数据传输能力的设备
公开(公告)号：US20090274138A1
公开(公告)日：2009-11-05
申请号：US12302227
申请日：2006-05-29
申请人： Eran Glickman , Erez Parnes , Noam Sheffer
发明人： Eran Glickman , Erez Parnes , Noam Sheffer
IPC分类号： H04J3/00
CPC分类号： H04J3/1605 , H04L49/90
摘要： A method for transmitting data, the method includes scanning at least a first memory unit to retrieve data segments associated with multiple TDM channels, in response to a definition of multiple TDM time frames, each TDM time frame includes multiple time slots; sending the retrieved data segments to an array of line shifters; multiplexing data segments provided from the array of line shifters, in response to the definition, such as to provide in a parallel manner multiple data segments to multiple TDM lines; and transmitting a group of time division multiples data frames over a group of TDM lines
摘要翻译：一种用于发送数据的方法，所述方法包括扫描至少第一存储器单元以响应于多个TDM时间帧的定义来检索与多个TDM信道相关联的数据段，每个TDM时间帧包括多个时隙; 将检索的数据段发送到行移位器阵列; 响应于定义，复用从线移位器阵列提供的数据段，例如以多个TDM线并行方式提供多个数据段; 以及在一组TDM线上传送一组时分多个数据帧

5. 发明授权

US08238333B2 Method for transmitting data and a device having data transmission capabilities 有权
标题翻译：用于发送数据的方法和具有数据传输能力的设备
公开(公告)号：US08238333B2
公开(公告)日：2012-08-07
申请号：US12302227
申请日：2006-05-29
申请人： Eran Glickman , Erez Parnes , Noam Sheffer
发明人： Eran Glickman , Erez Parnes , Noam Sheffer
IPC分类号： H04Q11/00
CPC分类号： H04J3/1605 , H04L49/90
摘要： A method for transmitting data, the method includes scanning at least a first memory unit to retrieve data segments associated with multiple TDM channels, in response to a definition of multiple TDM time frames, each TDM time frame includes multiple time slots; sending the retrieved data segments to an array of line shifters; multiplexing data segments provided from the array of line shifters, in response to the definition, such as to provide in a parallel manner multiple data segments to multiple TDM lines; and transmitting a group of time division multiples data frames over a group of TDM lines.
摘要翻译：一种用于发送数据的方法，所述方法包括扫描至少第一存储器单元以响应于多个TDM时间帧的定义来检索与多个TDM信道相关联的数据段，每个TDM时间帧包括多个时隙; 将检索的数据段发送到行移位器阵列; 响应于定义，复用从线移位器阵列提供的数据段，例如以多个TDM线并行方式提供多个数据段; 以及在一组TDM线上传送一组时分多个数据帧。

6. 发明申请

US20080235462A1 Device Having a Low Latency Single Port Memory Unit and a Method for Writing Multiple Data Segments to a Single Port Memory Unit 审中-公开
标题翻译：具有低延迟单端口存储器单元的设备和用于将多个数据段写入单个端口存储器单元的方法
公开(公告)号：US20080235462A1
公开(公告)日：2008-09-25
申请号：US12067592
申请日：2005-09-20
申请人： Eran Glickman , Adriano Leszkowicz , Noam Sheffer
发明人： Eran Glickman , Adriano Leszkowicz , Noam Sheffer
IPC分类号： G06F12/00
CPC分类号： G06F13/1673 , G06F13/161
摘要： A method and a device. The device includes a single port memory unit that includes multiple memory regions, whereas each memory region is adapted to receive multiple data segments in parallel; whereas the single port memory unit receives a memory clock signal; characterized by including access logic adapted to receive multiple data segment write requests from multiple data sources; to write, during a first memory clock cycle, multiple data segments to a certain memory region in response to an availability of the certain memory region; to temporarily store rejected data segments; to write, during a second memory clock cycle, at least the rejected data segments, to another memory region.
摘要翻译：一种方法和装置。该设备包括包括多个存储器区域的单个端口存储器单元，而每个存储器区域适于并行地接收多个数据段; 而单端口存储单元接收存储器时钟信号; 其特征在于包括适于从多个数据源接收多个数据段写入请求的访问逻辑; 在第一存储器时钟周期期间，响应于所述特定存储器区域的可用性将多个数据段写入特定存储器区域; 临时存储被拒绝的数据段; 在第二存储器时钟周期期间将至少被拒绝的数据段写入另一个存储器区域。

7. 发明授权

US09661577B2 Power management module and method therefor 有权
公开(公告)号：US09661577B2
公开(公告)日：2017-05-23
申请号：US14505538
申请日：2014-10-03
申请人： Amir David Modan , Ron-Michael Bar , Eran Glickman
发明人： Amir David Modan , Ron-Michael Bar , Eran Glickman
IPC分类号： G08C17/00 , H04W52/02
CPC分类号： H04W52/0258 , H04W52/0235 , H04W52/028 , Y02D70/00
摘要： A power management module comprising a client monitoring component arranged to monitor idle periods for a client component, and derive at least one idle period characteristic value for the client component based at least partly on the monitoring of the idle periods therefore. The power management module further comprises a power mode control component arranged to receive an indication of the client component entering an idle state, cause the client component to be put into a reduced power mode upon expiry of a first period of time, and cause the client component to be brought out of the reduced power mode upon expiry of a second period of time. At least one of the first and second periods of time is configured based at least partly on the idle period characteristic value(s) derived by the client monitoring component for the client component.

8. 发明授权

US08458364B2 Method for receiving and processing frames and a device having frame receiving and processing capabilities 有权
标题翻译：用于接收和处理帧的方法和具有帧接收和处理能力的设备
公开(公告)号：US08458364B2
公开(公告)日：2013-06-04
申请号：US12375795
申请日：2006-08-02
申请人： Yaron Alankry , Eran Glickman , Erez Parnes , Daniel Rozovsky
发明人： Yaron Alankry , Eran Glickman , Erez Parnes , Daniel Rozovsky
IPC分类号： G06F15/16 , G04F1/00
CPC分类号： H04J3/0697 , H04J3/0667
摘要： A device having frame receiving and processing capabilities and a method for receiving and processing frames. The method includes: receiving a frame; associating a frame timestamp with the frame; storing the frame and the associated timestamp at a certain buffer out of a group of buffers; generating a valid timing information frame indicator if the received frame is a valid timing information frame; and storing the valid timing information frame indicator at a certain buffer descriptor associated with the certain buffer.
摘要翻译：具有帧接收和处理能力的设备以及用于接收和处理帧的方法。该方法包括：接收帧; 将帧时间戳与帧相关联; 将帧和相关联的时间戳存储在一组缓冲器之外的某个缓冲器处; 如果接收到的帧是有效的定时信息帧，则生成有效的定时信息帧指示符; 以及将所述有效定时信息帧指示符存储在与所述特定缓冲器相关联的特定缓冲器描述符处。

9. 发明授权

US08452553B2 Device and method for testing a circuit 有权
标题翻译：用于测试电路的装置和方法
公开(公告)号：US08452553B2
公开(公告)日：2013-05-28
申请号：US12516319
申请日：2006-11-30
申请人： Eran Glickman , Yaron Alankry , Erez Arbel-Meirovich , Erez Parnes
发明人： Eran Glickman , Yaron Alankry , Erez Arbel-Meirovich , Erez Parnes
IPC分类号： G01R31/00
CPC分类号： G06F11/2236
摘要： A device and a method. The device includes: (i) a processor, connected to the receiver, (ii) an interface adapted to receive a test vector and to output a test response, the test vector includes a first group of signals that include idle signals and at least one information frame and a second group of signals that include timing signals and data signals; and (iii) a receiver, connected to the interface. The receiver is adapted to receive the first group of signals and filter out the idle signals and at least one instruction frame delimiters to provide at least one instruction. The device is adapted to send the at least one instruction to at least one instruction buffer. The processor is adapted to execute at least one instruction stored in the at least one instruction buffer and to respond to the second group of signals such as to provide test responses.
摘要翻译：一种设备和方法。该设备包括：（i）连接到接收器的处理器，（ii）适于接收测试向量并输出测试响应的接口，测试向量包括第一组信号，包括空闲信号和至少一个信息帧和包括定时信号和数据信号的第二组信号; 和（iii）连接到接口的接收器。接收器适于接收第一组信号并滤除空闲信号和至少一个指令帧分隔符以提供至少一个指令。该设备适于将至少一个指令发送到至少一个指令缓冲器。处理器适于执行存储在至少一个指令缓冲器中的至少一个指令，并且响应于第二组信号，以便提供测试响应。

10. 发明授权

US09841780B2 Apparatus and method for producing a report including a subset of a plurality of active timers based on a query to accurate quality of service based on the report 有权
公开(公告)号：US09841780B2
公开(公告)日：2017-12-12
申请号：US14324352
申请日：2014-07-07
申请人： Ron-Michael Bar , Eran Glickman , Amir David Modan
发明人： Ron-Michael Bar , Eran Glickman , Amir David Modan
IPC分类号： G06F1/04 , G06F1/14 , G06F17/30 , H04L1/18 , G06F9/44
CPC分类号： G06F1/14 , G06F9/451 , G06F17/30979 , H04L1/1883
摘要： An apparatus including: an input interface configured to enable user configuration of a future time window; and a report interface configured to produce a report relating to a first sub-set of a plurality of active timers that expire at programmed future points in time, wherein the first sub-set of the plurality of active timers expire during the user-configured future time window.

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