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1. 发明授权

US09645822B2 Conditional store instructions in an out-of-order execution microprocessor 有权
公开(公告)号：US09645822B2
公开(公告)日：2017-05-09
申请号：US14007097
申请日：2012-04-06
申请人： G. Glenn Henry , Terry Parks , Rodney E. Hooker , Gerard M. Col , Colin Eddy
发明人： G. Glenn Henry , Terry Parks , Rodney E. Hooker , Gerard M. Col , Colin Eddy
IPC分类号： G06F9/30
CPC分类号： G06F9/3017 , G06F9/30076 , G06F9/30123 , G06F9/30174 , G06F9/30189 , G06F9/30196
摘要： An instruction translator translates a conditional store instruction (specifying data register, base register, and offset register of the register file) into at least two microinstructions. An out-of-order execution pipeline executes the microinstructions. To execute a first microinstruction, an execution unit receives a base value and an offset from the register file and generates a first result as a function of the base value and offset. The first result specifies the memory location address. To execute a second microinstruction, an execution unit receives the first result and writes the first result to an allocated entry in the store queue if the condition flags satisfy the condition (the store queue subsequently writes the data to the memory location specified by the address), and otherwise kills the allocated store queue entry so that the store queue does not write the data to the memory location specified by the address.

2. 发明申请

US20140122843A1 CONDITIONAL STORE INSTRUCTIONS IN AN OUT-OF-ORDER EXECUTION MICROPROCESSOR 有权
标题翻译：不合格执行微处理器的条件存储指令
公开(公告)号：US20140122843A1
公开(公告)日：2014-05-01
申请号：US14007097
申请日：2012-04-06
申请人： G. Glenn Henry , Terry Parks , Rodney E. Hooker , Gerard M. Col , Colin Eddy
发明人： G. Glenn Henry , Terry Parks , Rodney E. Hooker , Gerard M. Col , Colin Eddy
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3017 , G06F9/30076 , G06F9/30123 , G06F9/30174 , G06F9/30189 , G06F9/30196
摘要： An instruction translator translates a conditional store instruction (specifying data register, base register, and offset register of the register file) into at least two microinstructions. An out-of-order execution pipeline executes the microinstructions. To execute a first microinstruction, an execution unit receives a base value and an offset from the register file and generates a first result as a function of the base value and offset. The first result specifies the memory location address. To execute a second microinstruction, an execution unit receives the first result and writes the first result to an allocated entry in the store queue if the condition flags satisfy the condition (the store queue subsequently writes the data to the memory location specified by the address), and otherwise kills the allocated store queue entry so that the store queue does not write the data to the memory location specified by the address.
摘要翻译：指令翻译器将条件存储指令（指定寄存器文件的指定数据寄存器，基址寄存器和偏移寄存器）转换为至少两个微指令。无序执行管线执行微指令。为了执行第一微指令，执行单元从寄存器文件接收基值和偏移量，并且产生作为基值和偏移量的函数的第一结果。第一个结果指定内存位置地址。为了执行第二微指令，如果条件标志满足条件（存储队列随后将数据写入由地址指定的存储器位置），则执行单元接收第一结果并将第一结果写入存储队列中的已分配条目，，否则将杀死所分配的存储队列条目，使得存储队列不将数据写入由地址指定的存储器位置。

3. 发明授权

US08392693B2 Fast REP STOS using grabline operations 有权
标题翻译：快速REP STOS使用抓取操作
公开(公告)号：US08392693B2
公开(公告)日：2013-03-05
申请号：US12781210
申请日：2010-05-17
申请人： G. Glenn Henry , Colin Eddy , Rodney E. Hooker
发明人： G. Glenn Henry , Colin Eddy , Rodney E. Hooker
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00
CPC分类号： G06F9/30043 , G06F9/30047 , G06F9/383 , G06F9/3834 , G06F9/3859 , G06F9/3865
摘要： A microprocessor includes a cache memory and a grabline instruction. The grabline instruction specifies a memory address that implicates a cache line of the memory. The grabline instruction instructs the microprocessor to initiate a zero-beat read-invalidate transaction on the bus to obtain ownership of the cache line. The microprocessor foregoes initiating the transaction on the bus when executing the grabline instruction if the microprocessor determines that a store to the cache line would cause an exception.
摘要翻译：微处理器包括高速缓冲存储器和获取指令。该grabline指令指定一个内存地址，暗示内存的高速缓存行。获取指令指示微处理器在总线上启动零跳读取无效事务以获得高速缓存行的所有权。如果微处理器确定到高速缓存行的存储将导致异常，则微处理器在执行抓取指令时放弃在总线上启动事务。

4. 发明授权

US08301842B2 Efficient pseudo-LRU for colliding accesses 有权
标题翻译：有效的伪LRU用于冲突访问
公开(公告)号：US08301842B2
公开(公告)日：2012-10-30
申请号：US12830588
申请日：2010-07-06
申请人： Colin Eddy , Rodney E. Hooker
发明人： Colin Eddy , Rodney E. Hooker
IPC分类号： G06F12/00
CPC分类号： G06F12/0864 , G06F12/123 , G06F12/128
摘要： An apparatus for allocating entries in a set associative cache memory includes an array that provides a first pseudo-least-recently-used (PLRU) vector in response to a first allocation request from a first functional unit. The first PLRU vector specifies a first entry from a set of the cache memory specified by the first allocation request. The first vector is a tree of bits comprising a plurality of levels. Toggling logic receives the first vector and toggles predetermined bits thereof to generate a second PLRU vector in response to a second allocation request from a second functional unit generated concurrently with the first allocation request and specifying the same set of the cache memory specified by the first allocation request. The second vector specifies a second entry different from the first entry from the same set. The predetermined bits comprise bits of a predetermined one of the levels of the tree.
摘要翻译：用于在集合关联高速缓冲存储器中分配条目的装置包括响应于来自第一功能单元的第一分配请求而提供第一伪最近最近使用（PLRU）向量的阵列。第一个PLRU向量指定由第一个分配请求指定的一组缓存中的第一个条目。第一向量是包括多个级别的比特树。切换逻辑接收第一向量并切换其预定比特以响应于来自与第一分配请求同时生成的第二功能单元的第二分配请求生成第二PLRU向量，并且指定由第一分配指定的高速缓冲存储器的相同集合请求。第二个向量指定与同一集合中的第一条目不同的第二条目。预定比特包括树的预定的一个级别的比特。

5. 发明授权

US08069340B2 Microprocessor with microarchitecture for efficiently executing read/modify/write memory operand instructions 有权
标题翻译：具有微架构的微处理器，用于高效执行读/写/写存储器操作数指令
公开(公告)号：US08069340B2
公开(公告)日：2011-11-29
申请号：US12100616
申请日：2008-04-10
申请人： Rodney E. Hooker , Gerard M. Col , Colin Eddy
发明人： Rodney E. Hooker , Gerard M. Col , Colin Eddy
IPC分类号： G06F9/30
CPC分类号： G06F9/3004 , G06F9/30087 , G06F9/3017 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3855
摘要： A microprocessor instruction translator translates a macroinstruction into three microinstructions to perform a read/modify/write operation on a memory operand. A first microinstruction instructs the microprocessor to calculate a source address and to load the memory operand into the microprocessor from memory at the source address and to calculate a destination address. The second microinstruction instructs the microprocessor to perform an arithmetic or logical operation on the loaded memory operand to generate a result. The third microinstruction instructs the microprocessor to write the result to memory at the destination address calculated by the first microinstruction. A first execution unit receives the first microinstruction and responsively calculates the source address and loads the memory operand into the microprocessor from memory at the source address. A second execution unit also receives the first microinstruction and calculates the destination address. The first and second execution units are distinct execution units within the microprocessor.
摘要翻译：微处理器指令转换器将宏指令转换成三个微指令以对存储器操作数执行读/修改/写操作。第一微指令指示微处理器计算源地址，并将存储器操作数从源地址的存储器加载到微处理器中并计算目的地地址。第二微指令指示微处理器对加载的存储器操作数执行算术或逻辑运算以产生结果。第三个微指令指示微处理器将结果写入由第一个微指令计算的目标地址的存储器。第一执行单元接收第一微指令并且响应地计算源地址并且将来自地址的存储器的存储器操作数加载到微处理器中。第二执行单元还接收第一微指令并计算目的地址。第一和第二执行单元是微处理器内不同的执行单元。

6. 发明申请

US20110055530A1 FAST REP STOS USING GRABLINE OPERATIONS 有权
标题翻译：快速回复使用格式操作
公开(公告)号：US20110055530A1
公开(公告)日：2011-03-03
申请号：US12781210
申请日：2010-05-17
申请人： G. Glenn Henry , Colin Eddy , Rodney E. Hooker
发明人： G. Glenn Henry , Colin Eddy , Rodney E. Hooker
IPC分类号： G06F9/38 , G06F12/08 , G06F9/312
CPC分类号： G06F9/30043 , G06F9/30047 , G06F9/383 , G06F9/3834 , G06F9/3859 , G06F9/3865
摘要： A microprocessor includes a cache memory and a grabline instruction. The grabline instruction specifies a memory address that implicates a cache line of the memory. The grabline instruction instructs the microprocessor to initiate a zero-beat read-invalidate transaction on the bus to obtain ownership of the cache line. The microprocessor foregoes initiating the transaction on the bus when executing the grabline instruction if the microprocessor determines that a store to the cache line would cause an exception.
摘要翻译：微处理器包括高速缓冲存储器和获取指令。该grabline指令指定一个内存地址，暗示内存的高速缓存行。获取指令指示微处理器在总线上启动零跳读取无效事务以获得高速缓存行的所有权。如果微处理器确定到高速缓存行的存储将导致异常，则微处理器在执行抓取指令时放弃在总线上启动事务。

7. 发明申请

US20110055485A1 EFFICIENT PSEUDO-LRU FOR COLLIDING ACCESSES 有权
标题翻译：有效的PSEUDO-LRU用于胶接接入
公开(公告)号：US20110055485A1
公开(公告)日：2011-03-03
申请号：US12830588
申请日：2010-07-06
申请人： Colin Eddy , Rodney E. Hooker
发明人： Colin Eddy , Rodney E. Hooker
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0864 , G06F12/123 , G06F12/128
摘要： An apparatus for allocating entries in a set associative cache memory includes an array that provides a first pseudo-least-recently-used (PLRU) vector in response to a first allocation request from a first functional unit. The first PLRU vector specifies a first entry from a set of the cache memory specified by the first allocation request. The first vector is a tree of bits comprising a plurality of levels. Toggling logic receives the first vector and toggles predetermined bits thereof to generate a second PLRU vector in response to a second allocation request from a second functional unit generated concurrently with the first allocation request and specifying the same set of the cache memory specified by the first allocation request. The second vector specifies a second entry different from the first entry from the same set. The predetermined bits comprise bits of a predetermined one of the levels of the tree.
摘要翻译：用于在集合关联高速缓冲存储器中分配条目的装置包括响应于来自第一功能单元的第一分配请求而提供第一伪最近最近使用（PLRU）向量的阵列。第一个PLRU向量指定由第一个分配请求指定的一组缓存中的第一个条目。第一向量是包括多个级别的比特树。切换逻辑接收第一向量并且切换其预定比特以响应于来自与第一分配请求同时生成的第二功能单元的第二分配请求生成第二PLRU向量，并且指定由第一分配指定的高速缓冲存储器的相同集合请求。第二个向量指定与同一集合中的第一条目不同的第二条目。预定比特包括树的预定的一个级别的比特。

8. 发明申请

US20110010501A1 EFFICIENT DATA PREFETCHING IN THE PRESENCE OF LOAD HITS 有权
标题翻译：有效的数据预处理在负载的存在
公开(公告)号：US20110010501A1
公开(公告)日：2011-01-13
申请号：US12763938
申请日：2010-04-20
申请人： Clinton Thomas Glover , Colin Eddy , Rodney E. Hooker , Albert J. Loper
发明人： Clinton Thomas Glover , Colin Eddy , Rodney E. Hooker , Albert J. Loper
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0862 , G06F12/0859 , G06F12/0897 , G06F2212/6022
摘要： A BIU prioritizes L1 requests above L2 requests. The L2 generates a first request to the BIU and detects the generation of a snoop request and L1 request to the same cache line. The L2 determines whether a bus transaction to fulfill the first request may be retried and, if so, generates a miss, and otherwise generates a hit. Alternatively, the L2 detects the L1 generated a request to the L2 for the same line and responsively requests the BIU to refrain from performing a transaction on the bus to fulfill the first request if the BIU has not yet been granted the bus. Alternatively, a prefetch cache and the L2 allow the same line to be simultaneously present. If an L1 request hits in both the L2 and in the prefetch cache, the prefetch cache invalidates its copy of the line and the L2 provides the line to the L1.
摘要翻译： BIU将L1请求优先于L2请求。 L2产生对BIU的第一个请求，并检测到窥探请求和L1请求到同一个高速缓存行的生成。 L2确定是否可以重试履行第一请求的总线事务，如果是，则产生未命中，否则生成命中。或者，L2检测到L1产生对同一行的L2的请求，并且如果BIU尚未被授予总线，则响应地请求BIU在总线上不执行交易以执行第一请求。或者，预取高速缓存和L2允许同时存在同一行。如果L1请求都在L2和预取缓存中同时进行，则预取缓存使其副本无效，并且L2向L1提供该行。

9. 发明申请

US20100306475A1 DATA CACHE WITH MODIFIED BIT ARRAY 有权
标题翻译：数据缓存与修改的位阵列
公开(公告)号：US20100306475A1
公开(公告)日：2010-12-02
申请号：US12472845
申请日：2009-05-27
申请人： Rodney E. Hooker , Colin Eddy , G. Glenn Henry
发明人： Rodney E. Hooker , Colin Eddy , G. Glenn Henry
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0831 , G06F9/30043 , G06F9/30047
摘要： A cache memory system includes a first array of storage elements each configured to store a cache line, a second array of storage elements corresponding to the first array of storage elements each configured to store a first partial status of the cache line in the corresponding storage element of the first array, and a third array of storage elements corresponding to the first array of storage elements each configured to store a second partial status of the cache line in the corresponding storage element of the first array. The second partial status indicates whether or not the cache line has been modified. When the cache memory system modifies the cache line within a storage element of the first array, it writes only the second partial status in the corresponding storage element of the third array to indicate that the cache line has been modified but refrains from writing the first partial status in the corresponding storage element of the second array. The cache memory system reads both the first partial status and the second partial status to determine the full status.
摘要翻译：高速缓冲存储器系统包括：第一阵列的存储元件，每个存储元件被配置为存储高速缓存行;对应于第一存储元件阵列的存储元件的第二阵列，每个存储元件阵列被配置为将高速缓存行的第一部分状态存储在相应的存储元件中以及与所述第一阵列存储元件相对应的存储元件的第三阵列，每个存储元件被配置为将所述高速缓存线的第二部分状态存储在所述第一阵列的相应存储元件中。第二部分状态指示高速缓存行是否已被修改。当高速缓冲存储器系统修改第一阵列的存储元件内的高速缓存线时，它仅将第二部分状态写入第三阵列的相应存储元件中，以指示高速缓存线已被修改，但是避免写入第一部分状态在第二个阵列的相应的存储元素中。缓存存储器系统读取第一部分状态和第二部分状态以确定完整状态。

10. 发明申请

US20100011188A1 MICROPROCESSOR THAT PERFORMS SPECULATIVE TABLEWALKS 有权
标题翻译： MICROPROCESSOR表现出结果表
公开(公告)号：US20100011188A1
公开(公告)日：2010-01-14
申请号：US12172729
申请日：2008-07-14
申请人： Colin Eddy , Rodney E. Hooker
发明人： Colin Eddy , Rodney E. Hooker
IPC分类号： G06F9/26
CPC分类号： G06F12/10 , G06F9/383 , G06F9/3842 , G06F2212/654
摘要： A microprocessor performs a speculative page tablewalk. The microprocessor includes a tablewalk engine that determines whether at least one of a predetermined set of conditions exists with respect to characteristics of the page of memory whose physical address specified by a memory access instruction is missing in the TLB, performs operations of the tablewalk in an out-of-order manner with respect to the execution of unretired program instructions older than the memory access instruction while none of the predetermined set of conditions exists, and waits to perform the operations of the tablewalk until the microprocessor has retired all program instructions older than the memory access instruction when at least one of the predetermined set of conditions exists. The predetermined set of conditions may include the tablewalk needing to load information from a strongly-ordered page, update page mapping information, or access a global page.
摘要翻译：微处理器执行投机页面行进。该微处理器包括一台行进引擎，其确定相对于存储器访问指令所指定的物理地址的存储器页面的特性，存在预定的一组条件中的至少一个，在TLB中执行台式机的操作相对于执行比存储器存取指令更早的程序指令执行，而不存在预定的一组条件，并且等待执行台式机的操作，直到微处理器已经退出所有程序指令当存在预定的一组条件中的至少一个时，存储器访问指令。预定的条件集合可以包括需要从强排序页面加载信息的行进台，更新页面映射信息或访问全局页面。

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