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1. 发明授权

US07519771B1 System and method for processing memory instructions using a forced order queue 有权
标题翻译：使用强制排序队列处理存储器指令的系统和方法
公开(公告)号：US07519771B1
公开(公告)日：2009-04-14
申请号：US10643577
申请日：2003-08-18
申请人： Gregory J. Faanes , Eric P. Lundberg , Steven L. Scott , Robert J. Baird
发明人： Gregory J. Faanes , Eric P. Lundberg , Steven L. Scott , Robert J. Baird
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F9/3004 , G06F9/30087 , G06F9/383 , G06F9/3834 , G06F12/0859
摘要： A novel system and method for processing memory instructions. One embodiment of the invention provides a method for processing a memory instruction. In this embodiment, the method includes obtaining a memory request; storing the memory request in an Initial Request Queue (IRQ); and processing the memory request from the IRQ by a cache controller, wherein processing includes: identifying a type of the memory request, and processing the memory request in both a local cache and an Force Order Queue (FOQ), wherein processing includes determining if a portion of an address associated with the memory request matches one or more partial addresses in the FOQ and, if the memory request misses in the cache and the address does not match one or more partial addresses in the FOQ, adding the memory request to the FOQ and allocating a cache line in the local cache corresponding to the local cache miss.
摘要翻译：一种用于处理存储器指令的新型系统和方法。本发明的一个实施例提供了一种用于处理存储器指令的方法。在本实施例中，该方法包括获取存储器请求; 将所述存储器请求存储在初始请求队列（IRQ）中; 以及由缓存控制器处理来自IRQ的存储器请求，其中处理包括：识别存储器请求的类型，以及在本地高速缓存和强制排队队列（FOQ）中处理存储器请求，其中处理包括确定是否与存储器请求相关联的地址的一部分匹配FOQ中的一个或多个部分地址，并且如果存储器请求在高速缓存中丢失并且该地址与FOQ中的一个或多个部分地址不匹配，则将存储器请求添加到FOQ 以及在对应于本地高速缓存未命中的本地高速缓存中分配高速缓存行。

2. 发明授权

US07334110B1 Decoupled scalar/vector computer architecture system and method 有权
标题翻译：去耦标量/矢量计算机架构系统及方法
公开(公告)号：US07334110B1
公开(公告)日：2008-02-19
申请号：US10643586
申请日：2003-08-18
申请人： Gregory J. Faanes , Steven L. Scott , Eric P. Lundberg , William T. Moore, Jr. , Timothy J. Johnson
发明人： Gregory J. Faanes , Steven L. Scott , Eric P. Lundberg , William T. Moore, Jr. , Timothy J. Johnson
IPC分类号： G06F9/38
CPC分类号： G06F9/3885 , G06F9/30036 , G06F9/30145 , G06F9/3802 , G06F9/383 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3853 , G06F9/3857 , G06F9/3861 , G06F9/3867
摘要： In a computer system having a scalar processing unit and a vector processing unit, wherein the vector processing unit includes a vector dispatch unit, a system and method of decoupling operation of the scalar processing unit from that of the vector processing unit, the method comprising sending a vector instruction from the scalar processing unit to the vector dispatch unit, wherein sending includes marking the vector instruction as complete if the vector instruction is not a vector memory instruction and if the vector instruction does not require scalar operands, reading a scalar operand, wherein reading includes transferring the scalar operand from the scalar processing unit to the vector dispatch unit, predispatching the vector instruction within the vector dispatch unit if the vector instruction is scalar committed, dispatching the predispatched vector instruction if all required operands are ready, and executing the dispatched vector instruction as a function of the scalar operand.
摘要翻译：在具有标量处理单元和向量处理单元的计算机系统中，其中矢量处理单元包括矢量调度单元，将标量处理单元与矢量处理单元的操作分离的系统和方法，所述方法包括发送从标量处理单元到矢量调度单元的向量指令，其中如果向量指令不是向量存储器指令，并且如果该向量指令不需要标量操作数，读取标量操作数，则发送包括将该向量指令标记为完成，其中，读取包括将标量操作数从标量处理单元传送到向量调度单元，如果向量指令是标量提交的，则在向量调度单元内预分配向量指令，如果所有需要的操作数都准备就调度预分配向量指令，并执行调度向量指令作为标量操作数的函数。

3. 发明授权

US08601236B2 Configurable vector length computer processor 有权
标题翻译：可配置向量长度计算机处理器
公开(公告)号：US08601236B2
公开(公告)日：2013-12-03
申请号：US13409033
申请日：2012-02-29
申请人： Gregory J. Faanes , Eric P. Lundberg , Abdulla Bataineh , Timothy J. Johnson , Michael Parker , James Robert Kohn , Steven L. Scott , Robert Alverson
发明人： Gregory J. Faanes , Eric P. Lundberg , Abdulla Bataineh , Timothy J. Johnson , Michael Parker , James Robert Kohn , Steven L. Scott , Robert Alverson
IPC分类号： G06F15/00
CPC分类号： G06F15/8053
摘要： A processor core, comprises one or more vector units operable to change between a fine-grained vector mode having a shorter maximum vector length and a coarse-grained vector mode having a longer maximum vector length. Changing vector modes comprises halting all instruction stream execution in the core, flushing one or more registers in a register space, reconfiguring one or more vector registers in the register space, and restarting instruction execution in the core.
摘要翻译：处理器核心包括一个或多个向量单元，其可操作以在具有较短最大向量长度的细粒子矢量模式和具有较长最大向量长度的粗粒矢量模式之间进行切换。更改向量模式包括停止核心中的所有指令流执行，刷新寄存器空间中的一个或多个寄存器，重新配置寄存器空间中的一个或多个向量寄存器，以及重新启动核心中的指令执行。

4. 发明申请

US20100115236A1 HIERARCHICAL SHARED SEMAPHORE REGISTERS 审中-公开
标题翻译：分层分析仪
公开(公告)号：US20100115236A1
公开(公告)日：2010-05-06
申请号：US12263305
申请日：2008-10-31
申请人： Abdulla Bataineh , James Robert Kohn , Eric P. Lundberg , Timothy J. Johnson , Thomas L. Court , Gregory J. Faanes , Steven L. Scott
发明人： Abdulla Bataineh , James Robert Kohn , Eric P. Lundberg , Timothy J. Johnson , Thomas L. Court , Gregory J. Faanes , Steven L. Scott
IPC分类号： G06F15/76 , G06F9/06
CPC分类号： G06F9/30101 , G06F9/52
摘要： A multiprocessor computer system having a plurality of processing elements comprises one or more core-level hierarchical shared semaphore registers, wherein each core-level hierarchical shared semaphore register is coupled to a different processor core. Each hierarchical shared semaphore register is writable to each of a plurality of streams executing on the coupled processor core. One or more chip-level hierarchical shared semaphore registers are also coupled to plurality of processor cores, each chip-level hierarchical shared semaphore register writable to each of the plurality of processor cores.
摘要翻译：具有多个处理元件的多处理器计算机系统包括一个或多个核心级别分层共享信号量寄存器，其中每个核心级别分层共享信号量寄存器耦合到不同的处理器核心。每个分层共享信号量寄存器对于在耦合的处理器核上执行的多个流中的每一个是可写的。一个或多个芯片级别分层共享信号量寄存器也耦合到多个处理器核，每个芯片级分级共享信号量寄存器可写入多个处理器核心中的每一个。

5. 发明申请

US20090138680A1 VECTOR ATOMIC MEMORY OPERATIONS 审中-公开
标题翻译：矢量原子记忆操作
公开(公告)号：US20090138680A1
公开(公告)日：2009-05-28
申请号：US11946490
申请日：2007-11-28
申请人： Timothy J. Johnson , Gregory J. Faanes
发明人： Timothy J. Johnson , Gregory J. Faanes
IPC分类号： G06F9/30
CPC分类号： G06F9/3001 , G06F9/30029 , G06F9/3004 , G06F9/30087 , G06F9/3861
摘要： A processor is operable to execute one or more vector atomic memory operations. A further embodiment provides support for atomic memory operations in a memory manger, which is operable to process atomic memory operations and to return a completion notification or a result.
摘要翻译：处理器可操作以执行一个或多个向量原子存储器操作。另一实施例提供对存储器管理器中的原子存储器操作的支持，其可操作以处理原子存储器操作并返回完成通知或结果。

6. 发明授权

US06665774B2 Vector and scalar data cache for a vector multiprocessor 有权
公开(公告)号：US06665774B2
公开(公告)日：2003-12-16
申请号：US09981380
申请日：2001-10-16
申请人： Gregory J. Faanes , Eric P. Lundberg
发明人： Gregory J. Faanes , Eric P. Lundberg
IPC分类号： G06F1200
CPC分类号： G06F15/8076 , G06F9/3004 , G06F9/3013 , G06F9/30138 , G06F12/0857 , G06F12/0859 , G06F12/0862 , G06F12/0888
摘要： A common scalar/vector data cache apparatus and method for a scalar/vector computer. One aspect of the present invention provides a computer system including a memory. The memory includes a plurality of sections. The computer system also includes a scalar/vector processor coupled to the memory using a plurality of separate address busses and a plurality of separate read-data busses wherein at least one of the sections of the memory is associated with each address bus and at least one of the sections of the memory is associated with each read-data bus. The processor further includes a plurality of scalar registers and a plurality of vector registers and operating on instructions which provide a reference address to a data word. The processor includes a scalar/vector cache unit that includes a cache array, and a FIFO unit that tracks (a.) an address in the cache array to which a read-data value will be placed when the read-data value is returned from the memory, and (b.) a destination code that specifies which of the scalar registers and vector registers into which the read-data value is to be loaded when the read-data value is returned from the memory.

7. 发明授权

US06496902B1 Vector and scalar data cache for a vector multiprocessor 有权
公开(公告)号：US06496902B1
公开(公告)日：2002-12-17
申请号：US09223853
申请日：1998-12-31
申请人： Gregory J. Faanes , Eric P. Lundberg
发明人： Gregory J. Faanes , Eric P. Lundberg
IPC分类号： G06F12100
CPC分类号： G06F15/8076 , G06F9/3004 , G06F9/3013 , G06F9/30138 , G06F12/0857 , G06F12/0859 , G06F12/0862 , G06F12/0888
摘要： A common scalar/vector data cache apparatus and method for a scalar/vector computer. One aspect of the present invention provides a computer system including a memory. The memory includes a plurality of sections. The computer system also includes a scalar/vector processor coupled to the memory using a plurality of separate address busses and a plurality of separate read-data busses wherein at least one of the sections of the memory is associated with each address bus and at least one of the sections of the memory is associated with each read-data bus. The processor further includes a plurality of scalar registers and a plurality of vector registers and operating on instructions which provide a reference address to a data word. The processor includes a scalar/vector cache unit that includes a cache array, and a FIFO unit that tracks (a.) an address in the cache array to which a read-data value will be placed when the read-data value is returned from the memory, and (b.) a destination code that specifies which of the scalar registers and vector registers into which the read-data value is to be loaded when the read-data value is returned from the memory.

8. 发明授权

US08307194B1 Relaxed memory consistency model 有权
标题翻译：轻松记忆一致性模型
公开(公告)号：US08307194B1
公开(公告)日：2012-11-06
申请号：US10643754
申请日：2003-08-18
申请人： Steven L. Scott , Gregory J. Faanes , Brick Stephenson , William T. Moore, Jr. , James R. Kohn
发明人： Steven L. Scott , Gregory J. Faanes , Brick Stephenson , William T. Moore, Jr. , James R. Kohn
IPC分类号： G06F9/30
CPC分类号： G06F9/3834 , G06F9/30018 , G06F9/30036 , G06F9/3004 , G06F9/30087 , G06F9/30094 , G06F9/34 , G06F9/3455 , G06F9/3824 , G06F9/3836 , G06F9/3861 , G06F9/52 , G06F9/522 , G06F12/0817 , G06F12/0855 , G06F12/0862 , G06F12/1027
摘要： A method and apparatus to provide specifiable ordering between and among vector and scalar operations within a single streaming processor (SSP) via a local synchronization (Lsync) instruction that operates within a relaxed memory consistency model. Various aspects of that relaxed memory consistency model are described. Further, a combined memory synchronization and barrier synchronization (Msync) for a multistreaming processor (MSP) system is described. Also, a global synchronization (Gsync) instruction provides synchronization even outside a single MSP system is described. Advantageously, the pipeline or queue of pending memory requests does not need to be drained before the synchronization operation, nor is it required to refrain from determining addresses for and inserting subsequent memory accesses into the pipeline.
摘要翻译：一种通过在松弛存储器一致性模型中操作的本地同步（Lsync）指令在单个流处理器（SSP）内的向量和标量运算之间和之间提供可指定排序的方法和装置。描述了该松弛记忆一致性模型的各个方面。此外，描述了用于多流处理器（MSP）系统的组合的存储器同步和屏障同步（Msync）。而且，描述了全局同步（Gsync）指令，即使在单个MSP系统外也提供同步。有利的是，在同步操作之前不需要排出未完成的存储器请求的流水线或队列，也不需要避免为后续存储器访问确定地址并将其插入流水线。

9. 发明授权

US07743223B2 Decoupling of write address from its associated write data in a store to a shared memory in a multiprocessor system 有权
标题翻译：将写入地址从存储中的相关写入数据解耦到多处理器系统中的共享存储器
公开(公告)号：US07743223B2
公开(公告)日：2010-06-22
申请号：US10643742
申请日：2003-08-18
申请人： Steven L. Scott , Gregory J. Faanes
发明人： Steven L. Scott , Gregory J. Faanes
IPC分类号： G06F13/00
CPC分类号： G06F13/1621 , G06F12/084
摘要： In a computer system having a plurality of processors connected to a shared memory, a system and method of decoupling an address from write data in a store to the shared memory. A write request address is generated for a memory write, wherein the write request address points to a memory location in shared memory. A write request is issued to the shared memory, wherein the write request includes the write request address. The write request address is noted in the shared memory and addresses in subsequent load and store requests are compared in share memory to the write request address. The write data is transferred to the shared memory and matched, within the shared memory, to the write request address. The write data is then stored into the shared memory as a function of the write request address.
摘要翻译：在具有连接到共享存储器的多个处理器的计算机系统中，将地址与存储器中的写入数据分离到共享存储器的系统和方法。为存储器写入生成写请求地址，其中写请求地址指向共享存储器中的存储器位置。向共享存储器发出写请求，其中写请求包括写请求地址。在共享存储器中记录写入请求地址，并将后续加载和存储请求中的地址在共享存储器中与写入请求地址进行比较。写入数据被传送到共享存储器，并在共享存储器内匹配写入请求地址。写入数据随着写请求地址的存储而被存储到共享存储器中。

10. 发明申请

US20100115234A1 CONFIGURABLE VECTOR LENGTH COMPUTER PROCESSOR 审中-公开
标题翻译：可配置矢量长度计算机处理器
公开(公告)号：US20100115234A1
公开(公告)日：2010-05-06
申请号：US12263302
申请日：2008-10-31
申请人： Gregory J. Faanes , Eric P. Lundberg , Abdulla Bataineh , Timothy J. Johnson , Michael Parker , James Robert Kohn , Steven L. Scott , Robert Alverson
发明人： Gregory J. Faanes , Eric P. Lundberg , Abdulla Bataineh , Timothy J. Johnson , Michael Parker , James Robert Kohn , Steven L. Scott , Robert Alverson
IPC分类号： G06F15/76 , G06F9/06
CPC分类号： G06F15/8053
摘要： A processor core, comprises one or more vector units operable to change between a fine-grained vector mode having a shorter maximum vector length and a coarse-grained vector mode having a longer maximum vector length. Changing vector modes comprises halting all instruction stream execution in the core, flushing one or more registers in a register space, reconfiguring one or more vector registers in the register space, and restarting instruction execution in the core.
摘要翻译：处理器核心包括一个或多个向量单元，其可操作以在具有较短最大向量长度的细粒子矢量模式和具有较长最大向量长度的粗粒矢量模式之间进行切换。更改向量模式包括停止核心中的所有指令流执行，刷新寄存器空间中的一个或多个寄存器，重新配置寄存器空间中的一个或多个向量寄存器，以及重新启动核心中的指令执行。

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