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11. 发明授权

US09348795B1 Programmable device using fixed and configurable logic to implement floating-point rounding 有权
标题翻译：可编程器件使用固定和可配置的逻辑来实现浮点舍入
公开(公告)号：US09348795B1
公开(公告)日：2016-05-24
申请号：US13934421
申请日：2013-07-03
申请人： Altera Corporation
发明人： Martin Langhammer
IPC分类号： G06F17/10 , G06F7/499 , G06F7/49
CPC分类号： G06F7/499 , G06F7/483 , G06F7/49947
摘要： A configurable specialized processing block includes a first floating-point arithmetic operator stage, a second floating-point arithmetic operator stage, and configurable interconnect within the configurable specialized processing block for routing signals into and out of each of the first and second floating-point arithmetic operator stages. In some embodiments, the configurable interconnect may be configurable to route a plurality of block inputs to inputs of the first floating-point arithmetic operator stage, at least one of the block inputs to an input of the second floating-point arithmetic operator stage, output of the first floating-point arithmetic operator stage to an input of the second floating-point arithmetic operator stage, at least one of the block inputs to a direct-connect output to another such block, output of the first floating-point arithmetic operator stage to the direct-connect output, and a direct-connect input from another such block to an input of the second floating-point arithmetic operator stage.
摘要翻译：可配置的专用处理块包括第一浮点算术运算器级，第二浮点算术运算级和可配置专用处理块内的可配置互连，用于将信号输入和输出到第一和第二浮点运算操作员阶段。在一些实施例中，可配置互连可以被配置为将多个块输入路由到第一浮点运算器级的输入，至少一个块输入到第二浮点运算器级的输入，输出所述第一浮点算术运算器级的输入到所述第二浮点算术运算器级的输入，所述块输入中的至少一个直接连接到另一个所述块的输出，所述第一浮点算术运算级的输出到直接连接输出，以及从另一个这样的块到第二个浮点算术运算阶段的输入的直接连接输入。

12. 发明授权

US09098332B1 Specialized processing block with fixed- and floating-point structures 有权
标题翻译：具有固定和浮点结构的专用处理块
公开(公告)号：US09098332B1
公开(公告)日：2015-08-04
申请号：US13486255
申请日：2012-06-01
申请人： Martin Langhammer
发明人： Martin Langhammer
IPC分类号： G06F7/48 , G06F7/49 , G06F9/30 , G06F7/499 , G06F7/485
CPC分类号： G06F7/49947 , G06F7/483 , G06F7/485 , G06F7/49936 , G06F7/49957 , G06F7/5324 , G06F7/5443 , G06F9/30014 , G06F2207/3824
摘要： Circuitry for performing arithmetic operations on a plurality of inputs efficiently performs both fixed-point operations and floating-point operations. Each of at least first and second respective operator circuits operates on a respective subplurality of the plurality of inputs. Other circuitry selectively interconnects the respective operator circuits so that they can operate together or separately, according to user selection, on selected ones of (a) the full plurality of inputs, (b) individual ones of the respective subpluralities of the plurality of inputs, or (c) combinations of portions of the respective subpluralities of the plurality of inputs. At least one of the respective operator circuits includes circuits for simultaneously computing multiple different results and for selecting among the multiple different results based on an output of another one of the respective operator circuits. One or more of the multiple different results are selectably usable to perform both fixed-point operations and floating-point operations.
摘要翻译：用于对多个输入执行算术运算的电路有效地执行定点运算和浮点运算。至少第一和第二相应运算符电路中的每一个基于多个输入的相应子结构运行。其他电路选择性地互连相应的操作者电路，使得它们可以根据用户选择在一个或多个（a）整个多个输入中的选定的一个上进行操作或分开，（b）多个输入的各个子视图中的各个，或（c）多个输入的各个子视图的部分的组合。各个运算器电路中的至少一个包括用于同时计算多个不同结果的电路，并且用于基于相应运算符电路中另一个的输出在多个不同结果之间进行选择。多个不同结果中的一个或多个可选择地可用于执行定点操作和浮点运算。

13. 发明授权

US08975922B2 Method and apparatus for simultaneous processing of multiple functions 有权
标题翻译：用于同时处理多种功能的方法和装置
公开(公告)号：US08975922B2
公开(公告)日：2015-03-10
申请号：US13235188
申请日：2011-09-16
申请人： Adrian Stoica , Radu Andrei , David Zhu , Mohammad Mehdi Mojarradi , Tuan A. Vo
发明人： Adrian Stoica , Radu Andrei , David Zhu , Mohammad Mehdi Mojarradi , Tuan A. Vo
IPC分类号： H03K19/094 , G06F7/00 , G06F7/49 , H03K19/00
CPC分类号： H03K19/0002 , G06F7/00 , G06F7/49 , H03K19/08
摘要： Electronic logic gates that operate using N logic state levels, where N is greater than 2, and methods of operating such gates. The electronic logic gates operate according to truth tables. At least two input signals each having a logic state that can range over more than two logic states are provided to the logic gates. The logic gates each provide an output signal that can have one of N logic states. Examples of gates described include NAND/NAND gates having two inputs A and B and NAND/NAND gates having three inputs A, B, and C, where A, B and C can take any of four logic states. Systems using such gates are described, and their operation illustrated. Optical logic gates that operate using N logic state levels are also described.
摘要翻译：使用N个大于2的N逻辑状态电平进行操作的电子逻辑门，以及操作这些门的方法。电子逻辑门根据真值表进行操作。至少两个具有可超过两个以上逻辑状态的逻辑状态的输入信号被提供给逻辑门。每个逻辑门提供可以具有N个逻辑状态之一的输出信号。所描述的门的示例包括具有两个输入A和B的NAND / NAND门和具有三个输入A，B和C的NAND / NAND门，其中A，B和C可以采取四种逻辑状态中的任一种。描述使用这种门的系统，并且说明它们的操作。还描述了使用N个逻辑状态级操作的光逻辑门。

14. 发明授权

US6104642A Method and apparatus for 1 of 4 register file design 有权
标题翻译： 1/4寄存器文件设计方法和装置
公开(公告)号：US6104642A
公开(公告)日：2000-08-15
申请号：US207806
申请日：1998-12-09
申请人： James S. Blomgren , Terence M. Potter , Michael R. Seningen , Stephen C. Horne
发明人： James S. Blomgren , Terence M. Potter , Michael R. Seningen , Stephen C. Horne
IPC分类号： G06F1/08 , G06F5/01 , G06F7/02 , G06F7/49 , G06F7/50 , G06F7/544 , G06F17/50 , G11C8/00 , G11C8/10 , G11C8/16 , G11C8/18 , G11C11/418 , G11C11/419 , G11C11/56 , G11C19/00 , H03K19/00 , H03K19/003 , H03K19/08 , H03K19/096 , H03K19/21 , G11C7/00
CPC分类号： G06F7/5443 , G06F1/08 , G06F17/5045 , G06F5/015 , G06F7/02 , G06F7/026 , G06F7/49 , G11C11/418 , G11C11/419 , G11C11/56 , G11C19/00 , G11C8/00 , G11C8/10 , G11C8/16 , G11C8/18 , H03K19/0002 , H03K19/00346 , H03K19/00361 , H03K19/00384 , H03K19/0813 , H03K19/0963 , H03K19/215 , G06F2207/3824 , G06F7/483 , G06F7/508 , G11C7/1006
摘要： The present invention is a method and apparatus for a register cell that is configured to store information. The cell includes a multiplexer that is configurable to select various inputs when the multiplexer is in various states. The multiplexer is configurable to select a first input when the multiplexer is in a first state, and to select a second input when the multiplexer is in a second state. The multiplexer is further configured to provide storage data, the first input being configured to receive data from outside the cell. An output element, such as a second multiplexer, is configured to receive a word enable. The output of the first multiplexer is delayed in a delay element, and is provided as one of the inputs to the first multiplexer.
摘要翻译：本发明是一种用于存储信息的寄存器单元的方法和装置。该单元包括多路复用器，其可配置为当多路复用器处于不同状态时选择各种输入。多路复用器可配置为当多路复用器处于第一状态时选择第一输入，并且当多路复用器处于第二状态时选择第二输入。复用器还被配置为提供存储数据，第一输入被配置为从单元外部接收数据。诸如第二多路复用器的输出元件被配置为接收字使能。第一多路复用器的输出在延迟元件中延迟，并且被提供为第一多路复用器的输入之一。

15. 发明授权

US5699287A Method and device for adding and subtracting thermometer coded data 失效
标题翻译：加减温度计编码数据的方法和装置
公开(公告)号：US5699287A
公开(公告)日：1997-12-16
申请号：US954133
申请日：1992-09-30
申请人： Fuk Ho P. Ng , Shivaling S. Mahant-Shetti
发明人： Fuk Ho P. Ng , Shivaling S. Mahant-Shetti
IPC分类号： G06F7/02 , G06F7/49 , G06F7/50 , G06F7/544
CPC分类号： G06F7/50 , G06F7/544 , G06F2207/5442
摘要： For subtracting two thermometer coded words each having a most significant byte (MSB) and a least significant byte (LSB), a check is made to see if a borrowing condition exists. A first borrowing condition exists if word B MSB is greater than word A MSB (12) and word A LSB is greater than word B LSB (14). In such a case a borrow (16) must take place on word B MSB. A second borrowing condition exists when word A MSB is greater than word B MSB (18) and word B LSB is greater than word A LSB (20). In this instance a borrow (22) must take place on word A MSB through a shift right function. After borrowing occurs, a subtraction process (24) takes place by exclusive-or'ing word A and B MSBs. The result is reconstructed (26) through a shift right process into proper thermometer code format. If a borrowing condition exists, an appropriate LSB is translated (28, 30) before an LSB subtraction process (32) takes the resulting word A and word B LSBs and exclusively-or's them together. The result is reconstructed (34) through a shift right rotate left process to place the LSB in proper thermometer code format. For addition, the first word is reversed (302) and added to the second word by an exclusive-or process. The result is inverted (306) and reconstructed (308) into proper thermometer code format. A carry (311) check is made and the reconstructed output is adjusted (310) whenever a carry condition exists. A further MSB adjustment (312) is made when the carry causes an overflow in the MSB result.
摘要翻译：为了减去每个具有最高有效字节（MSB）和最低有效字节（LSB）的两个温度计编码字，检查是否存在借用条件。如果字B MSB大于字A MSB（12），字A LSB大于字B LSB（14），则存在第一个借用条件。在这种情况下，借用（16）必须在B字母MSB上进行。当字A MSB大于字B MSB（18），字B LSB大于字A LSB（20）时，存在第二个借用条件。在这种情况下，借口（22）必须通过转移权函数在单词A MSB上进行。在借用发生之后，通过排除或者使用字A和B的MSB来进行减法处理（24）。结果通过正确的转换重建（26）到适当的温度计代码格式。如果存在借用条件，则在LSB减法处理（32）将所得到的字A和字B LSB作为LSB之前，将它们排列在一起之前，转换适当的LSB（28,30）。通过右移旋转左进程重建（34）结果，将LSB置于适当的温度计代码格式。另外，第一个单词是反向的（302），并通过一个独占或者进程添加到第二个单词中。结果反转（306）并重建（308）成适当的温度计代码格式。进行进位（311）检查，并且每当存在进位条件时重建输出被调整（310）。当进位导致MSB结果中的溢出时，进一步进行MSB调整（312）。

16. 发明授权

US5644639A Device for carrying out a division 失效
标题翻译：用于执行划分的装置
公开(公告)号：US5644639A
公开(公告)日：1997-07-01
申请号：US614921
申请日：1996-03-11
申请人： Robert Naciri , Jean P. Bournas
发明人： Robert Naciri , Jean P. Bournas
IPC分类号： G06F7/493 , G06F7/52 , G06F7/535 , G06F7/537 , G06F7/72 , H04L9/30 , G06F7/49 , G06K19/073
CPC分类号： G06F7/535 , G06F7/72 , G06F7/723
摘要： This device is designed for carrying out a division of a dividend A formed by "m" words with a base "b" by a divisor D. It comprises an active memory (2), a multiplication member which forms part of a calculation unit (8) provided with a first input (x.sub.i) for "x" words of a multiplicand and with a second input (A.sub.i) for "y" words of a multiplier. Accumulating means are provided for adding to locations of the memory (2) a multiple of a quantity db.sub.k.multidot. b.sup.j worked out by the said multiplication member, as well as testing means for providing an indication of the zero value of a separator S in the said location, and for activating the cumulation means until the testing means provide the said indication, as well as decrementation means for decrementing the value J at each indication. The remainder of the division is present in the last locations, and the quotient in the first ones.
摘要翻译：该设备被设计用于通过除数D对由“m”个字与基本“b”形成的除数A进行除法。其包括有源存储器（2），形成计算单元的一部分的乘法部件 8）具有被乘数的“x”个字的第一输入（xi）和乘法器的“y”个字的第二输入（Ai）。提供累加装置，用于将存储器（2）的位置添加到由所述乘法部件计算的数量dbkxbj的倍数，以及用于在所述位置提供分离器S的零值的指示的测试装置，并且用于激活累积装置，直到测试装置提供所述指示，以及用于在每个指示下递减值J的递减装置。剩余部分存在于最后的位置，第一个位置的商数。

17. 发明授权

US5644253A Multiple-valued logic circuit 失效
标题翻译：多值逻辑电路
公开(公告)号：US5644253A
公开(公告)日：1997-07-01
申请号：US618420
申请日：1996-03-08
申请人： Motomu Takatsu
发明人： Motomu Takatsu
IPC分类号： G06F7/49 , H03K17/735
CPC分类号： G06F7/49
摘要： There are provided n operation circuits in a multiple-valued logic circuit which receives plural multiple-valued input logic signals corresponding to respective numeral values and outputs a multiple-valued output logic signal corresponding to a sum of the respective numeral values. The kth operation circuit includes multiple-input comparators generating carry signals, and multiple-input amplifiers performing weighted linear voltage adding operations on input signals at the kth digit, carry signals of the input signals at the kth digit, and carry signals from the (k-1)th digit where k is 0, 1, 2, . . . , n-1. The multiple-input amplifier has a feedback circuit having a capacitance. The multiple-input comparator and the multiple-input amplifier are connected to corresponding input signals through capacitances. A voltage gain of the multiple-input amplifier is based on a ratio of the capacitance through which the input signal is applied and the capacitance of the feedback circuit.
摘要翻译：在多值逻辑电路中提供n个操作电路，其接收与各个数值对应的多个多值输入逻辑信号，并输出与各个数值相加的多值输出逻辑信号。第k个运算电路包括产生进位信号的多输入比较器，对第k个数字的输入信号执行加权线性电压相加运算的多输入放大器输入第k个数字上的输入信号的信号，并传送来自（k -1）个数字，其中k是0,1,2。。。，n-1。多输入放大器具有具有电容的反馈电路。多输入比较器和多输入放大器通过电容连接到相应的输入信号。多输入放大器的电压增益基于施加输入信号的电容与反馈电路的电容之比。

18. 发明授权

US5587668A Semiconductor devices utilizing neuron MOS transistors 失效
标题翻译：利用神经元MOS晶体管的半导体器件
公开(公告)号：US5587668A
公开(公告)日：1996-12-24
申请号：US119157
申请日：1993-09-20
申请人： Tadashi Shibata , Tadahiro Ohmi
发明人： Tadashi Shibata , Tadahiro Ohmi
IPC分类号： G06F7/49 , G06F7/50 , G06F7/501 , G06N3/063 , G11C11/56 , G11C16/04 , G11C27/00 , H01L29/788 , H03K19/0944 , H03K19/017
CPC分类号： G06F7/5013 , G06F7/49 , G06N3/0635 , G11C11/5621 , G11C16/0408 , G11C27/005 , H01L29/7881 , H03K19/0944 , G06F2207/482 , G06F2207/4826 , G11C11/54 , G11C2211/5611
摘要： A semiconductor device by which a circuit having the same functions as those of the conventional circuit is realized with a very small number of elements, and complex logical functions can be designed simply, and further, its layout is also possible. A semiconductor device made up of at least one neuron MOS transistor having a gate electrode provided in a potentially floating state in a portion for isolating a source and drain region via a first insulation film, and plural control electrodes which are capacitively coupled to the floating gate electrode via a second insulation film, is characterized in that the first signal is inputted to a first control gate electrode of the first neuron MOS transistor, the first signal is inputted to a first inverter comprising one or more stages, and the output of the first inverter is inputted to a second control gate electrode which is one of the plural control gate electrodes other than the first control gate electrode.
摘要翻译： PCT No.PCT / JP92 / 00347 Sec。 371日期：1993年9月20日 102（e）1993年9月20日PCT 1993年3月21日PCT公布。公开号WO92 / 16971 日期：1992年10月1日具有与现有电路相同功能的电路的半导体器件通过非常少的元件实现，并且可以简单地设计复杂的逻辑功能，此外，其布局也是可能的。一种由至少一个神经元MOS晶体管组成的半导体器件，所述至少一个神经元MOS晶体管具有经由第一绝缘膜隔离源极和漏极区域的部分中以潜在浮动状态设置的栅电极，以及电容耦合到浮置栅极的多个控制电极电极经由第二绝缘膜，其特征在于，第一信号被输入到第一神经元MOS晶体管的第一控制栅电极，第一信号被输入到包括一级或多级的第一反相器，第一信号的输出反相器被输入到除了第一控制栅电极之外的多个控制栅电极之一的第二控制栅电极。

19. 发明授权

US5483477A Multiplying circuit and microcomputer including the same 失效
标题翻译：乘法电路和微机包括相同
公开(公告)号：US5483477A
公开(公告)日：1996-01-09
申请号：US205457
申请日：1994-03-04
申请人： Fumiki Sato , Kouichi Fujita
发明人： Fumiki Sato , Kouichi Fujita
IPC分类号： G06F7/49 , G06F7/48 , G06F7/52 , G06F7/533 , G06F7/00 , G06F15/00
CPC分类号： G06F7/5338 , G06F7/4824
摘要： A multiplying circuit wherein an adder 7 outputs a value "0" in which both of a positive part and a negative part of a number with a redundant code are "1", and at a last cycle of the multiplication cycles, the finish detecting circuit 13 detects finishing of multiplication cycles by detecting that "1" exists in a portion storing a positive part of a number with a redundant code of the third bit from the lowest bit of the second latch 8 and in a portion storing a negative part of the same at the same time. In such a construction, a counter circuit for counting multiplication cycles according to the Booth algorithm utilizing a number with a redundant code can be omitted. Accordingly, the number of transistors is reduced and the circuit configuration becomes simple.
摘要翻译：乘法电路，其中加法器7输出其中具有冗余代码的数字的正部分和负部分都为“1”的值“0”，并且在乘法周期的最后一个周期，完成检测电路 13检测乘法周期的完成，通过检测在存储来自第二锁存器8的最低位的第三位的冗余代码的数字的正部分中存储的部分中存在“1”，并且存储负同一时间。在这种结构中，可以省略利用具有冗余码的数量的根据布斯算法进行乘法周期计数的计数器电路。因此，晶体管的数量减少，电路结构变得简单。

20. 发明授权

US5467298A Multivalued adder having capability of sharing plural multivalued signals 失效
标题翻译：多值加法器具有共享多个多值信号的能力
公开(公告)号：US5467298A
公开(公告)日：1995-11-14
申请号：US155828
申请日：1993-11-23
申请人： Yukihiro Yoshida
发明人： Yukihiro Yoshida
IPC分类号： G06F7/50 , G06F7/49 , G06F7/501 , H03K19/20 , G06F7/00
CPC分类号： G06F7/49
摘要： A multivalued adder for processing addition of a first data and a second data, which are one of binary logic and multivalued logic, includes a first and second input circuit. The first input circuit includes parallel inputs for binary logic and multivalued logic, and receives the first data. The first input circuit also outputs a first set of bit data representing the first data. Similarly, the second input circuit includes parallel inputs for binary logic and multivalued logic, and receives the second data. The second input circuit also outputs a second set of bit data representing the second data. An adding circuit, connected to the first and said second input circuits, adds the second set of bit data and the first set of bit data. An output circuit, connected to the adding circuit, converts the output of the adding circuit into data in binary logic and multivalued logic, in parallel, and outputs converted data in binary logic and multivalued logic, in parallel.
摘要翻译：用于处理作为二进制逻辑和多值逻辑之一的第一数据和第二数据的相加的多值加法器包括第一和第二输入电路。第一输入电路包括用于二进制逻辑和多值逻辑的并行输入，并接收第一数据。第一输入电路还输出表示第一数据的第一组位数据。类似地，第二输入电路包括用于二进制逻辑和多值逻辑的并行输入，并且接收第二数据。第二输入电路还输出表示第二数据的第二组位数据。连接到第一和第二输入电路的加法电路将第二组位数据和第一组位数据相加。连接到加法电路的输出电路并联地将加法电路的输出转换成二进制逻辑和多值逻辑的数据，并且并行输出二进制逻辑和多值逻辑中的转换数据。

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