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11. 发明授权

US5430399A Reset logic circuit and method 失效
标题翻译：复位逻辑电路和方法
公开(公告)号：US5430399A
公开(公告)日：1995-07-04
申请号：US49063
申请日：1993-04-19
申请人： Dennis L. Wendell
发明人： Dennis L. Wendell
IPC分类号： H03K19/017 , H03K3/355 , H03K5/13 , H03K19/0948 , H03K19/20 , H03K3/26
CPC分类号： H03K5/133 , H03K3/355
摘要： A high speed inverter circuit is disclosed. The inverter has a quiescent state, a set state for receiving an input pulse and generating a set pulse in response thereto, a reset stage in which a delayed version of the same input pulse is used to reset the inverter, and a recovery state for preparing the inverter for the arrival of a new input pulse. The inverter has an extremely fast switching speed because virtually all of the available energy of the input signal is used to set the inverter. The inverter may be used in an inverter chain for rapidly propagating electrical signals.
摘要翻译：公开了一种高速逆变电路。逆变器具有静止状态，用于接收输入脉冲并响应于此产生设定脉冲的设定状态，使用相同输入脉冲的延迟版本来复位逆变器的复位阶段，以及用于准备逆变器为新的输入脉冲到达。变频器具有非常快的开关速度，因为输入信号的几乎所有的可用能量用于设置变频器。逆变器可用于逆变器链，用于快速传播电信号。

12. 发明授权

US3855483A Memory system incorporating a memory cell and timing means on a single semiconductor substrate 失效
标题翻译：在单个半导体基板上记录存储单元和定时装置的存储器系统
公开(公告)号：US3855483A
公开(公告)日：1974-12-17
申请号：US34156573
申请日：1973-03-15
申请人： INTEL CORP
发明人： KARP J , REGITZ W
IPC分类号： G11C11/405 , G11C11/4076 , H03K3/355 , H03K17/00
CPC分类号： H03K3/355 , G11C11/405 , G11C11/4076
摘要： A memory system is disclosed wherein the system may be controlled by providing a single clock signal to an array of memory cells on a monolithic semiconductor substrate. The substrate includes a timing generator means and compensating means which compensates for fabrication variances.
摘要翻译：公开了一种存储器系统，其中可以通过向单片半导体衬底上的存储器单元阵列提供单个时钟信号来控制系统。衬底包括定时发生器装置和补偿装置，其补偿制造方差。

13. 发明授权

US3584311A Multivibrator circuit with means to prevent false triggering from supply voltage fluctuations 失效
标题翻译：具有防止从电源电压波动引起的错误触发的手段电路
公开(公告)号：US3584311A
公开(公告)日：1971-06-08
申请号：US3584311D
申请日：1969-02-13
申请人： GREGORY L SCHAFFER
发明人： SCHAFFER GREGORY L
IPC分类号： H03K3/284 , H03K3/355 , H03K3/10 , H03K1/18
CPC分类号： H03K3/355 , H03K3/284
摘要： A one-shot multivibrator that produces long duration output pulses in which there is immunity against false triggering caused by power supply fluctuation or noises. The immunity against false triggering from power supply noises is achieve by a constant current source which provides a constant current independent of fluctuations in the supply voltage for isolating the power supply noise from the timing circuit of the one-shot multivibrator.

14. 发明授权

US3522454A Pulse control circuit 失效
标题翻译：脉冲控制电路
公开(公告)号：US3522454A
公开(公告)日：1970-08-04
申请号：US3522454D
申请日：1968-07-08
申请人： NORTHERN ELECTRIC CO
发明人： GILMOUR WAYNE D
IPC分类号： H03K3/355 , H03K5/15 , H03K1/18
CPC分类号： H03K5/15 , H03K3/355

15. 发明授权

US09172357B2 Pulse generator circuit 有权
标题翻译：脉冲发生器电路
公开(公告)号：US09172357B2
公开(公告)日：2015-10-27
申请号：US14276488
申请日：2014-05-13
申请人： Palo Alto Research Center Incorporated
发明人： David Eric Schwartz
IPC分类号： H03K3/00 , H03K3/012 , H03K3/355 , H03K5/04
CPC分类号： H03K3/012 , H03K3/355 , H03K5/04
摘要： A pulse generator circuit is disclosed that is optimized for printed, solution-processed thin film transistor processing. In certain embodiments, the circuit comprises dual thin film transistors that operate as a diode and resistor, respectively. Optionally, a third thin film transistor may be provided to operate as a pass transistor in response to an enable signal. The elements of the circuit are configured such that a rising pulse on an input node triggers an output pulse on an output node in the manner of a monostable multivibrator.
摘要翻译：公开了针对印刷，溶液处理的薄膜晶体管处理优化的脉冲发生器电路。在某些实施例中，电路包括分别作为二极管和电阻器工作的双薄膜晶体管。可选地，可以提供第三薄膜晶体管以响应于使能信号而作为传输晶体管工作。电路的元件被配置为使得输入节点上的上升脉冲以单稳态多谐振荡器的方式触发输出节点上的输出脉冲。

16. 发明授权

US5731724A Power short pulse generator having an input delay and a feedback delay in generating the output pulse 失效
标题翻译：电源短脉冲发生器具有输入延迟和产生输出脉冲的反馈延迟
公开(公告)号：US5731724A
公开(公告)日：1998-03-24
申请号：US638920
申请日：1996-04-25
申请人： Gennady Ivanovich Grishakov , Igor Vladimirovich Tarasov
发明人： Gennady Ivanovich Grishakov , Igor Vladimirovich Tarasov
IPC分类号： H03K3/033 , H03K3/355
CPC分类号： H03K3/355 , H03K3/033
摘要： A power short pulse generator for generating a pulse on a rising edge and falling edge of an input signal according to the present invention comprises an input node for receiving the input signal and an output node for supplying an output signal. A first pulldown circuit and a second pulldown circuit are connected in series between the output node and a first supply voltage potential, the first pulldown circuit and the second pulldown circuit each having an input. A third pulldown circuit and a fourth pulldown circuit are connected in series between the output node and the first supply voltage potential, the third pulldown circuit and the fourth pulldown circuit each having an input. A pullup circuit is connected between the output node and a second supply voltage potential, the pullup circuit having an input. A leakage current circuit is connected between the output node and the second supply voltage potential. A feedback delay circuit has a feedback circuit input connected to the output node and a feedback circuit output connected to the input of the pullup circuit. A first input delay circuit is connected between the input node and the input of the first pulldown circuit and the second pulldown circuit. A second input delay circuit is connected between the input node and the input of the third pulldown circuit and the fourth pulldown circuit.
摘要翻译：根据本发明的用于在输入信号的上升沿和下降沿产生脉冲的电源短脉冲发生器包括用于接收输入信号的输入节点和用于提供输出信号的输出节点。第一下拉电路和第二下拉电路串联连接在输出节点和第一电源电压电位之间，第一下拉电路和第二下拉电路各自具有输入。第三下拉电路和第四下拉电路串联连接在输出节点和第一电源电压电位之间，第三下拉电路和第四下拉电路各自具有输入。上拉电路连接在输出节点和第二电源电压电位之间，上拉电路具有输入。漏电流电路连接在输出节点和第二电源电压之间。反馈延迟电路具有连接到输出节点的反馈电路输入和连接到上拉电路的输入的反馈电路输出。第一输入延迟电路连接在输入节点与第一下拉电路和第二下拉电路的输入端之间。第二输入延迟电路连接在输入节点和第三下拉电路和第四下拉电路的输入之间。

17. 发明授权

US5309034A Timer circuit for stretching the duration of an input pulse 失效
标题翻译：用于延长输入脉冲持续时间的定时器电路
公开(公告)号：US5309034A
公开(公告)日：1994-05-03
申请号：US148531
申请日：1993-11-08
申请人： Kenji Ishibashi
发明人： Kenji Ishibashi
IPC分类号： H03K3/017 , H03K3/033 , H03K3/355 , H03K5/04 , H03K5/13 , H03K17/28
CPC分类号： H03K3/033 , H03K3/355 , H03K5/04 , H03K5/13
摘要： A timer circuit is provided including a self-holding circuit that includes a reset delay circuit for delaying an input pulse by a prescribed time. The output of the self-holding circuit is caused to fall by the rising edge of the input pulse and to rise by the falling edge of the input pulse or the rising edge of a pulse fed back through the reset delay circuit whichever occurs last. Since the pulse duration can be stretched up to a length equal to the reset delay time by the action of the self-holding circuit, the possibility of the input pulse being split through a pulse stretching circuit is eliminated.
摘要翻译：提供了一种定时器电路，其包括自保持电路，该自保持电路包括用于将输入脉冲延迟预定时间的复位延迟电路。使自保持电路的输出下降到输入脉冲的上升沿，并且通过输入脉冲的下降沿或通过复位延迟电路反馈的脉冲的上升沿（以较高者为准）上升。由于脉冲持续时间可以通过自保持电路的作用而被拉伸到等于复位延迟时间的长度，因此消除了通过脉冲拉伸电路分离的输入脉冲的可能性。

18. 发明授权

US5051613B1 失效
公开(公告)号：US5051613B1
公开(公告)日：1992-11-17
申请号：US53310090
申请日：1990-06-04
申请人： JOHN M HOUSER JR , OLIVER G LOUGHNER
发明人： JOHN M HOUSER JR , OLIVER G LOUGHNER
IPC分类号： H03K17/06 , H03K17/687 , H03K3/02 , H03K3/033 , H03K3/355
CPC分类号： H03K17/687 , H03K17/06

19. 发明授权

US4710904A Constant pulse width generator including transition detectors 失效
标题翻译：恒定脉宽发生器，包括转换探测器
公开(公告)号：US4710904A
公开(公告)日：1987-12-01
申请号：US767873
申请日：1985-08-21
申请人： Atsushi Suzuki
发明人： Atsushi Suzuki
IPC分类号： G11C11/41 , H03K3/033 , H03K3/355 , G11C7/00
CPC分类号： H03K3/033 , H03K3/355
摘要： A semiconductor circuit for generating a pulse with a constant pulse width regardless of the pulse widths of the input signals, including a pulse-width fixing circuit for latching the output signal of a gate circuit when an input signal received by the gate circuit changes. The pulse width fixing circuit unlatches the gate circuit a predetermined time after the latching.
摘要翻译：一种半导体电路，用于产生具有恒定脉冲宽度的脉冲，而不管输入信号的脉冲宽度，包括用于当由门电路接收的输入信号改变时锁存门电路的输出信号的脉冲宽度固定电路。脉冲宽度固定电路在锁存之后的预定时间内打开门电路。

20. 发明授权

US4707626A Internal time-out circuit for CMOS dynamic RAM 失效
标题翻译： CMOS动态RAM的内部超时电路
公开(公告)号：US4707626A
公开(公告)日：1987-11-17
申请号：US634897
申请日：1984-07-26
申请人： Shinji Inoue
发明人： Shinji Inoue
IPC分类号： G11C11/407 , G11C11/34 , H03K3/355 , H03K5/13 , H03K3/284 , H03K5/153 , H03K17/30 , H03K19/094
CPC分类号： H03K3/355
摘要： A delay circuit for internal clock generation in a dynamic RAM uses a one-shot multivibrator composed of a pair of cross-coupled CMOS NOR gates with a RC delay circuit in the coupling path between the output of one NOR gate and the input of the other. The RC delay circuit uses an MOS transistor as the resistor, with the gate of this device connected to the supply voltage, so the resistance varies with changes in the supply. A CMOS inverter stage in the delay circuit has its input connected across the capacitor of the RC delay, so the trip point will vary with threshold voltage. In a dynamic RAM, this circuit may be used to establish the critical timing between write and read mode.
摘要翻译：用于动态RAM中内部时钟产生的延迟电路使用由一对交叉耦合的CMOS或非门组成的单稳态多谐振荡器，其中一个或非门的输出与另一个或非门的输入之间的耦合路径中具有RC延迟电路。 RC延迟电路使用MOS晶体管作为电阻，该器件的栅极连接到电源电压，因此电阻随电源的变化而变化。延迟电路中的CMOS反相器级的输入端连接在RC延迟的电容器两端，因此跳变点将随阈值电压而变化。在动态RAM中，该电路可用于建立写入和读取模式之间的关键定时。

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