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11. 发明授权

US09407282B2 Analog-to-digital converter 有权
标题翻译：模数转换器
公开(公告)号：US09407282B2
公开(公告)日：2016-08-02
申请号：US14357786
申请日：2012-10-11
申请人： Telefonaktiebolaget L M Ericsson (publ)
发明人： Martin Anderson , Lars Sundström
IPC分类号： H04B1/38 , H03M3/00 , H04B1/16 , H04W88/02 , H04W88/08
CPC分类号： H03M3/396 , H03M3/374 , H03M3/436 , H03M3/454 , H03M3/458 , H03M3/464 , H04B1/16 , H04W88/02 , H04W88/08
摘要： A continuous-time ΔΣ-ADC (1) is disclosed. It comprises a sampled quantizer (5) arranged to generate samples y(n) of a digital output signal of the ΔΣ-ADC (1) at sample instants nT, where n is an integer sequence index and T is a sampling period, based on an analog input signal to the quantizer (5). Furthermore, the ΔΣ-ADC (1) comprises one or more DACs (10a-b), each arranged to generate an analog feedback signal based on the samples of the digital output signal generated by the sampled quantizer (5). Moreover, the ΔΣ-ADC (1) comprises a continuous-time analog network (20) arranged to generate the analog input signal to the quantizer (5) based on the feedback signal(s) from the one or more DACs (10a-b) and an analog input signal to the ΔΣ-ADC (1). At least one DAC (10b) of the one or more DACs (10b) comprises two switched-capacitor DACs (40, 50) arranged to operate on the same input but with a mutual delay in time. A corresponding radio receiver circuit (100), a corresponding intergrated circuit (200), and a corresponding radio communication apparatus (300, 400) are also disclosed.
摘要翻译：公开了连续时间ΔΣ-ADC（1）。它包括一个采样量化器（5），被配置为在采样时刻nT产生ΔΣ-ADC（1）的数字输出信号的样本y（n），其中n是整数序列索引，T是采样周期，基于到量化器（5）的模拟输入信号。此外，ΔΣ-ADC（1）包括一个或多个DAC（10a-b），每个DAC（10a-b）被布置为基于由采样量化器（5）生成的数字输出信号的采样来产生模拟反馈信号。此外，ΔΣ-ADC（1）包括连续时间模拟网络（20），其被布置为基于来自所述一个或多个DAC（10a-b）的反馈信号来产生到量化器（5）的模拟输入信号）和到ΔΣ-ADC（1）的模拟输入信号。所述一个或多个DAC（10b）中的至少一个DAC（10b）包括两个开关电容器DAC（40,50），其布置成在相同的输入上进行操作，但在时间上相互延迟。还公开了相应的无线电接收器电路（100），相应的集成电路（200）和相应的无线电通信装置（300,400）。

12. 发明申请

US20160013805A1 DELTA-SIGMA MODULATOR AND COMMUNICATION DEVICE 有权
标题翻译： DELTA-SIGMA调制器和通信设备
公开(公告)号：US20160013805A1
公开(公告)日：2016-01-14
申请号：US14768288
申请日：2014-02-27
申请人： SUMITOMO ELECTRIC INDUSTRIES, LTD.
发明人： Takashi MAEHATA
IPC分类号： H03M3/00
CPC分类号： H03M3/422 , H03M3/32 , H03M3/396 , H03M3/402 , H03M3/43
摘要： A delta-sigma modulator capable of outputting an output signal including a plurality of signals having different frequencies. The delta-sigma modulator includes: a plurality of input ports to which a plurality of input signals having different frequencies are inputted, respectively; a plurality of loop filters provided corresponding to the plurality of input ports, respectively; an adder configured to add outputs of the plurality of loop filters; and a quantizer configured to quantize an output of the adder. The plurality of loop filters each receive the input signal inputted to the corresponding input port and a feedback signal of an output of the quantizer. The plurality of loop filters each have a characteristic of stopping noise in the vicinity of a frequency of the input signal inputted to the corresponding input port.
摘要翻译：能够输出包括具有不同频率的多个信号的输出信号的Δ-Σ调制器。 Δ-Σ调制器包括：分别输入多个具有不同频率的输入信号的多个输入端口; 分别与所述多个输入端口对应地设置的多个环路滤波器; 加法器，被配置为添加所述多个环路滤波器的输出; 以及量化器，被配置为量化加法器的输出。多个环路滤波器各自接收输入到相应输入端口的输入信号和量化器的输出的反馈信号。多个环路滤波器各自具有在输入到相应的输入端口的输入信号的频率附近停止噪声的特性。

13. 发明授权

US09231613B2 Idle tone dispersion device and frequency measurement device 有权
标题翻译：空闲音分离装置和频率测量装置
公开(公告)号：US09231613B2
公开(公告)日：2016-01-05
申请号：US14712087
申请日：2015-05-14
申请人： Seiko Epson Corporation
发明人： Masayoshi Todorokihara
IPC分类号： H03M3/00
CPC分类号： H03M3/346 , G01R23/12 , H03M3/30 , H03M3/324 , H03M3/396 , H03M3/466 , H03M3/472
摘要： An idle tone dispersion device includes n FDSM (1) to FDSM (n), a phase adjustment unit which relatively adjusts a phase between a measured signal and a reference signal such that a phase of an idle tone is completely different, and generates and supplies n sets of output measured signals and output reference signals to each of the n FDSM (1) to FDSM (n), and an adder which adds output data of the n FDSM (1) to FDSM (n) and outputs a frequency delta-sigma modulation signal.
摘要翻译：空闲色散分散装置包括nFDSM（1）至FDSM（n），相位调整单元，其相对调节测量信号和参考信号之间的相位，使得空闲音调的相位完全不同，并产生和提供 n个输出测量信号和输出参考信号到n FDSM（1）至FDSM（n）中的每一个，以及将n个FDSM（1）的输出数据加到FDSM（n）的加法器，并输出频率Δ- Σ调制信号。

14. 发明申请

US20130082766A1 DUAL MODE SIGMA DELTA ANALOG TO DIGITAL CONVERTER AND CIRCUIT USING THE SAME 有权
标题翻译：双模式SIGMA DELTA模拟到数字转换器和使用它的电路
公开(公告)号：US20130082766A1
公开(公告)日：2013-04-04
申请号：US13252981
申请日：2011-10-04
申请人： Yi-Lung CHEN
发明人： Yi-Lung CHEN
IPC分类号： H04B1/10 , H03M3/02
CPC分类号： H03M3/396 , H04B1/30
摘要： The present invention provides a dual mode sigma delta analog to digital converter (ADC), which only in one hardware implementation, used for low IF and near zero IF receiver. The dual mode sigma delta ADC comprises a first switched-capacitor integrator; a second switched-capacitor integrator; a quantizer; a feedback circuit and a mode device. By switching the mode device on or off, one could easily change the configuration of the disclosed ADC to decide the receiving signal falling in low-IF or near zero IF.
摘要翻译：本发明提供了一种仅在一个硬件实现中用于低IF和近零IF接收机的双模Σ-Δ模数转换器（ADC）。双模Σ-ΔADC包括第一开关电容积分器; 第二开关电容器积分器; 量化器反馈电路和模式设备。通过打开或关闭模式设备，可以轻松地改变所公开的ADC的配置，以确定接收信号落入低IF或接近零IF。

15. 发明授权

US06362762B1 Multiple mode analog-to-digital converter employing a single quantizer 有权
标题翻译：采用单个量化器的多模式模数转换器
公开(公告)号：US06362762B1
公开(公告)日：2002-03-26
申请号：US09645072
申请日：2000-08-23
申请人： Henrik T. Jensen , Gopal Raghavan
发明人： Henrik T. Jensen , Gopal Raghavan
IPC分类号： H03M300
CPC分类号： H03M3/396 , H03M3/428 , H03M3/448 , H03M3/454
摘要： Several delta-sigma modulator circuits and a single quantizer provide analog-to-digital conversion for multiple frequency bands. A wideband mode is provided by coupling an analog signal to be digitized directly to a quantizer. Narrowband modes are provided by switching the analog signal to be digitized into one of several delta-sigma modulator circuits. Noise shaping and filtering by the delta-sigma modulator circuits result in improved signal-to-noise-and-distortion performance and increased resolution. Performance is further enhanced by feeding back multiple bits output by the quantizer to the delta-sigma modulator circuits. The delta-sigma modulator circuits can be either continuous time or discrete time delta sigma modulators.
摘要翻译：几个Δ-Σ调制器电路和单个量化器为多个频带提供模数转换。通过将要直接数字化的模拟信号耦合到量化器来提供宽带模式。通过将要数字化的模拟信号切换成几个Δ-Σ调制器电路之一来提供窄带模式。由Δ-Σ调制器电路进行的噪声整形和滤波导致改善的信噪比和失真性能并提高分辨率。通过将由量化器输出的多个比特反馈到Δ-Σ调制器电路，进一步增强了性能。 Δ-Σ调制器电路可以是连续时间或离散时间ΔΣ调制器。

16. 发明授权

US06232901B1 High performance sigma-delta-sigma low-pass/band-pass modulator based analog-to-digital and digital-to-analog converter 有权
标题翻译：高性能Σ-Δ-sigma低通/带通调制器的模数和数模转换器
公开(公告)号：US06232901B1
公开(公告)日：2001-05-15
申请号：US09384002
申请日：1999-08-26
申请人： Duane L. Abbey
发明人： Duane L. Abbey
IPC分类号： H03M302
CPC分类号： H03M7/3017 , H03M3/396 , H03M3/43 , H03M3/45 , H03M3/454 , H03M7/304
摘要： A sigma-delta low-pass/band-pass based modulator for analog-to-digital converters includes at least one or more tunable band-pass filter stages. The filter stages are configured arrays with one or more parallel filter stages arranged as a group, and with one or more groups in cascade. The input signal is provided to all filter stages in the first group, and the outputs of the last group are combined and provided to the output processing elements. The output processing elements provide the signal conversion to the converter output, as well as the inverse conversion of the output signal to form the feedback signal or signals. All filter stages receive a feedback signal from the output processing elements. Each of the tunable band-pass filter stages is independently tunable to a respective predetermined frequency. At least one of the filter stages can be configured to support low-pass operation in conjunction with band-pass operation for increased low-pass signal bandwidth. The modulator can also be configured as digital-to-analog converters or as digital resolution reducers.
摘要翻译：用于模数转换器的Σ-Δ低通/带通调制器包括至少一个或多个可调谐带通滤波器级。过滤器级是配置有一个或多个并联过滤器级的阵列，并且具有一个或多个级联的组。将输入信号提供给第一组中的所有滤波器级，并且将最后一组的输出组合并提供给输出处理元件。输出处理元件提供到转换器输出的信号转换，以及输出信号的反向转换以形成反馈信号。所有滤波器级从输出处理元件接收反馈信号。可调谐带通滤波器级中的每一个独立地可调谐到相应的预定频率。滤波器级中的至少一个可以被配置为支持带通操作的低通操作，以增加低通信号带宽。调制器也可以配置为数模转换器或数字分辨率降低器。

17. 发明授权

US5345406A Bandpass sigma delta converter suitable for multiple protocols 失效
标题翻译：带通Σ-Δ转换器适用于多种协议
公开(公告)号：US5345406A
公开(公告)日：1994-09-06
申请号：US935018
申请日：1992-08-25
申请人： Tim A. Williams
发明人： Tim A. Williams
IPC分类号： H03M3/02 , G06F15/31
CPC分类号： H03M3/396 , H03M3/418
摘要： Improved integration and simplified construction of direct conversion receivers is achieved by providing selectivity in the early stages of a sigma delta converter to reject adjacent channel signals and thereby allow greater dynamic range for the desired input signals. A bandpass sigma delta converter is taught which is suitable for use with signals having multiple protocols. In a first stage, an aliased input signal is applied to two filters having desired and preferably programmable filter characteristics which provide selectivity to the input signal. A third filter is utilized having a programmable center frequency, which receives as an input signal the sum of the filtered input signal plus the quantization noise of the first stage. This provides a first intermediate output signal of desired selectivity. Quantization noise of the first stage is also applied to a second filter stage which provides a second intermediate output signal having a first component related to the quantization noise of the first stage, and a second component which is the shaped quantization noise of the second stage. The first and second intermediate output signals are combined in order to provide a desired output signal in which the original input signal has been filtered to provide a desired selectivity and converted to a digital signal while the quantization noise of the first stage has been cancelled, and the quantization noise of the second stage has been shaped by a desired function and converted to a digital signal independent of the input signal shaping.
摘要翻译：通过在Σ-Δ转换器的早期阶段提供选择性来抑制相邻信道信号，从而允许所需输入信号的更大的动态范围来实现改进的直接转换接收机的集成和简化结构。教导了一种适用于具有多个协议的信号的带通Σ-Δ转换器。在第一阶段，将混叠的输入信号施加到具有期望且优选地可编程滤波器特性的两个滤波器，这对滤波器输入信号提供选择性。使用具有可编程中心频率的第三滤波器，其接收滤波输入信号加上第一级的量化噪声作为输入信号的和。这提供了所需选择性的第一中间输出信号。第一级的量化噪声也被施加到第二滤波器级，该第二滤波器级提供具有与第一级的量化噪声相关的第一分量的第二中间输出信号和作为第二级的成形量化噪声的第二分量。第一和第二中间输出信号被组合以提供期望的输出信号，其中原始输入信号已被滤波以提供期望的选择性并且在第一级的量化噪声已经被取消的同时被转换成数字信号，并且第二级的量化噪声已经通过期望的功能整形，并且转换成独立于输入信号整形的数字信号。

18. 发明授权

US09838030B1 Apparatuses and methods for sample-rate conversion 有权
公开(公告)号：US09838030B1
公开(公告)日：2017-12-05
申请号：US15478395
申请日：2017-04-04
申请人： Syntropy Systems, LLC
发明人： Christopher Pagnanelli
IPC分类号： H03M3/00
CPC分类号： H03M3/38 , H03M3/344 , H03M3/396 , H03M3/41
摘要： Provided are, among other things, systems, apparatuses methods and techniques for automatically adjusting the noise-transfer-function of a modulator which is designed to attenuate the level of unwanted noise and/or distortion in a particular frequency band, without similarly attenuating the level of a desired signal in the same frequency band. One such apparatus includes a processing block for generating and injecting an explicit reference signal, and a processing block for detecting the amplitude of that reference signal.

19. 发明申请

US20170111057A1 METHOD AND APPARATUS FOR ADJUSTING A BANDWIDTH OF A SIGMA DELTA CONVERTER 有权
公开(公告)号：US20170111057A1
公开(公告)日：2017-04-20
申请号：US14887024
申请日：2015-10-19
申请人： MOTOROLA SOLUTIONS, INC.
发明人： Joshua E. Dorevitch
IPC分类号： H03M3/00 , H04B1/16
CPC分类号： H03M3/51 , H03M3/344 , H03M3/376 , H03M3/396 , H03M3/424 , H03M3/50 , H04B1/16
摘要： A method and apparatus for adjusting a bandwidth of a sigma delta converter by adjusting a reference voltage provided to the sigma delta converter. The apparatus includes a switched capacitor digital-to-analog converter in the feedback loop of the sigma delta modulator. The sigma delta modulator determines the bandwidth mode of the converter and adjusts the reference voltage to deliver high performance functionality. In one embodiment, a multi-bit digital signal is received by the digital-to-analog converter. The reference voltage is provided to multiple capacitive circuits of the digital-to-analog converter and the capacitive circuits are activated and deactivated based on the multi-bit digital signal. The digital-to-analog converter, thus, provides a feedback analog signal using dynamic element matching.

20. 发明申请

US20160134301A1 DELTA-SIGMA MODULATOR HAVING TRANSCONDUCTOR NETWORK FOR DYNAMICALLY TUNING LOOP FILTER COEFFICIENTS 有权
标题翻译：具有用于动态调谐环路滤波器系数的交叉网络的DELTA-SIGMA调制器
公开(公告)号：US20160134301A1
公开(公告)日：2016-05-12
申请号：US14537836
申请日：2014-11-10
申请人： ANALOG DEVICES GLOBAL
发明人： Hongxing Li , NIALL KEVIN KEARNEY , KEITH O'DONOGHUE
IPC分类号： H03M3/00 , H03H11/04
CPC分类号： H03H11/0422 , H03M3/396 , H03M3/422 , H03M3/438 , H03M3/458
摘要： A dynamically tunable transconductor includes a voltage-to-current converter stage for generating a current signal based on a voltage signal; and a current scaling stage for scaling the current signal by a scaling factor to achieve a particular transconductance. Current scaling stage includes a coarse tune mechanism having an associated coarse tune step and a fine tune mechanism having an associated fine tune step, where the scaling factor is a ratio of the coarse tune step to the fine tune step. A delta-sigma modulator can implement the transconductor to generate loop filter coefficients by dynamically tuning the transconductance to achieve a particular resistance.
摘要翻译：一种动态可调谐的跨导体包括用于基于电压信号产生电流信号的电压 - 电流转换器级; 以及用于按比例因子缩放当前信号以实现特定跨导的电流缩放级。当前缩放级包括具有相关联的粗调步骤的粗调机构和具有相关联的微调步骤的微调机构，其中缩放因子是粗调步骤与微调步骤的比率。 Δ-Σ调制器可以通过动态调谐跨导来实现跨导体来产生环路滤波器系数以实现特定的电阻。

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