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1. 发明公开

US20230195151A1 VOLTAGE REGULATION USING A DELTA-SIGMA MODULATOR, DEVICE AND METHOD 审中-公开
公开(公告)号：US20230195151A1
公开(公告)日：2023-06-22
申请号：US18048163
申请日：2022-10-20
申请人： NXP B.V.
发明人： Christian Vincent Sorace , Ludovic Oddoart , Fabien Boitard , Nicolas Patrick Vantalon
IPC分类号： G05F1/575 , H03M3/00
CPC分类号： G05F1/575 , H03M3/428
摘要： It is described a voltage regulator device (100), comprising:

i) a power device (150), configured to receive an input signal (151) and to produce a corresponding output signal (152);
ii) a comparator device (110), coupled via a feedback path (140) to the power device (150), and configured to receive the output signal (152) as a feedback signal (141), and to produce a compared feedback signal (112); and
iii) a digital modulation device (120), arranged between the comparator device (110) and the power device (150), and configured to digitally modulate the compared feedback signal (112), and to provide the digitally modulated signal (121) to the power device (150), wherein the digital modulation device (120) comprises:
iiia) a delta-sigma (122),
iiib) a quantizer (124), and
iiic) a feedforward path (128), configured to feedforward the compared feedback signal (112) beyond the delta-sigma (122).

2. 发明申请

US20120194370A1 SIGMA-DELTA CONVERTER SYSTEM AND METHOD 有权
标题翻译： SIGMA-DELTA转换器系统和方法
公开(公告)号：US20120194370A1
公开(公告)日：2012-08-02
申请号：US13305607
申请日：2011-11-28
申请人： Giri NK Rangan , Roger Levinson , John M. Caruso
发明人： Giri NK Rangan , Roger Levinson , John M. Caruso
IPC分类号： H03M3/00
CPC分类号： H03M3/32 , H03M3/02 , H03M3/30 , H03M3/428 , H03M3/452
摘要： A sigma-delta converter may include a filter coupled to a first summation circuit and a second summation circuit. A multi bit quantizer may be coupled to the second summation circuit. A single bit digital-to-analog converter (DAC) may be included that defines a feedback path between the multi-bit quantizer and the first summation circuit. A feed-forward coefficient circuit defining a feed forward path between the first summation circuit and the second summation circuit may be included.
摘要翻译： Σ-Δ转换器可以包括耦合到第一求和电路和第二求和电路的滤波器。多位量化器可以耦合到第二求和电路。可以包括定义多位量化器和第一求和电路之间的反馈路径的单位数模转换器（DAC）。可以包括限定第一求和电路和第二求和电路之间的前馈路径的前馈系数电路。

3. 发明授权

US08223051B2 Multi-bit sigma-delta modulator with reduced number of bits in feedback path 失效
标题翻译：反馈路径中位数减少的多位Σ-Δ调制器
公开(公告)号：US08223051B2
公开(公告)日：2012-07-17
申请号：US12812072
申请日：2008-12-30
申请人： Robert H. M. Van Veldhoven
发明人： Robert H. M. Van Veldhoven
IPC分类号： H03M3/00
CPC分类号： H03M3/428 , H03M3/452 , H03M7/302
摘要： A sigma-delta modulator (200) for an ADC, passes an input signal to a loop filter (20), then to a multi-bit quantizer (30) of the modulator (200). An output of the quantizer (30) is passed to a digital filter (50), and a feedback signal is passed back to the loop filter (20), the feedback signal having fewer bits than are produced by the multi-bit quantizer (30). No separate feedback loop for the digital filter (50) is used, so as to reduce the need to adjust the loop filter for stable operation. The digital filter (50) can have an order greater than one in the passband of the sigma-delta modulator (200).
摘要翻译：用于ADC的Σ-Δ调制器（200）将输入信号传递到环路滤波器（20），然后传送到调制器（200）的多位量化器（30）。量化器（30）的输出被传递到数字滤波器（50），并且反馈信号被传回到环路滤波器（20），反馈信号具有比由多位量化器（30 ）。没有使用数字滤波器（50）的单独的反馈回路，以减少调整环路滤波器的稳定运行的需要。数字滤波器（50）可以在Σ-Δ调制器（200）的通带中具有大于1的量级。

4. 发明授权

US07212587B2 Apparatus for reducing DC offset in a receiver 有权
标题翻译：用于减少接收机中的DC偏移的装置
公开(公告)号：US07212587B2
公开(公告)日：2007-05-01
申请号：US10343540
申请日：2001-07-16
申请人： Nadim Khlat , Francois Dorel
发明人： Nadim Khlat , Francois Dorel
IPC分类号： H04L25/06
CPC分类号： H04L25/063 , H03F1/304 , H03F2200/375 , H03M3/428 , H03M3/456 , H03M3/494
摘要： Apparatus for reducing DC offset in a signal path of a conversion system comprising a front end circuit for providing an input signal having an a DC offset; an amplifier system coupled to the front end circuit to receive and amplify the input signal; a multi-bit sigma delta modulator for receiving the input signal from the amplifier system and providing a first bit quantizer; a DC adapt circuit coupled to the sigma delta modulator for receiving the first bit quantizer from the sigma delta modulator and for providing an operation to reduce DC offset; a digital to analog converter (DAC) coupled to the digital DC adapt circuit to provide an analog signal representative of the DC offset correction to the input of the amplifier system, wherein the digital DC adapt circuit and the DAC form a feedback path originating at the first bit of the multi bit sigma delta modulator to the input of the amplifier system.
摘要翻译：用于减小转换系统的信号路径中的DC偏移的装置，包括用于提供具有DC偏移的输入信号的前端电路; 耦合到前端电路以接收和放大输入信号的放大器系统; 多位Σ-Δ调制器，用于从放大器系统接收输入信号并提供第一位量化器; 耦合到所述Σ-Δ调制器的DC适配电路，用于从所述Σ-Δ调制器接收所述第一位量化器并提供减少DC偏移的操作; 耦合到所述数字DC适配器电路的数模转换器（DAC），以向所述放大器系统的输入提供表示所述DC偏移校正的模拟信号，其中所述数字DC适配电路和所述DAC形成源自所述放大器系统的反馈路径多位Σ-Δ调制器的第一位到放大器系统的输入端。

5. 发明申请

US20040071238A1 Apparatus for reducing dc offset in a receiver 失效
标题翻译：用于减少接收机中直流偏移的装置
公开(公告)号：US20040071238A1
公开(公告)日：2004-04-15
申请号：US10343540
申请日：2003-05-12
发明人： Nadim Khlat , Francois Dorel
IPC分类号： H04L001/00 , H03D001/04
CPC分类号： H04L25/063 , H03F1/304 , H03F2200/375 , H03M3/428 , H03M3/456 , H03M3/494
摘要： Apparatus for reducing DC offset in a signal path of a conversion system comprising a front end circuit for providing an input signal having an a DC offset; an amplifier system coupled to the front end circuit to receive and amplify the input signal; a multi-bit sigma delta modulator for receiving the input signal from the amplifier system and providing a first bit quantizer; a DC adapt circuit coupled to the sigma delta modulator for receiving the first bit quantizer from the sigma delta modulator and for providing an operation to reduce DC offset; a digital to analog converter (DAC) coupled to the digital DC adapt circuit to provide an analog signal representative of the DC offset correction to the input of the amplifier system, wherein the digital DC adapt circuit and the DAC form a feedback path originating at the first bit of the multi bit sigma delta modulator to the input of the amplifier system.
摘要翻译：用于减小转换系统的信号路径中的DC偏移的装置，包括用于提供具有DC偏移的输入信号的前端电路; 耦合到前端电路以接收和放大输入信号的放大器系统; 多位Σ-Δ调制器，用于从放大器系统接收输入信号并提供第一位量化器; 耦合到所述Σ-Δ调制器的DC适配电路，用于从所述Σ-Δ调制器接收所述第一位量化器并提供减少DC偏移的操作; 耦合到所述数字DC适配器电路的数模转换器（DAC），以向所述放大器系统的输入提供表示所述DC偏移校正的模拟信号，其中所述数字DC适配电路和所述DAC形成源自所述放大器系统的反馈路径多位Σ-Δ调制器的第一位到放大器系统的输入端。

6. 发明授权

US06441759B1 Multi-bit &Dgr;&Sgr; modulator having linear output 有权
标题翻译：具有线性输出的多位DELTASIGMA调制器
公开(公告)号：US06441759B1
公开(公告)日：2002-08-27
申请号：US09651744
申请日：2000-08-30
申请人： Gopal Raghavan , Henrik T. Jensen
发明人： Gopal Raghavan , Henrik T. Jensen
IPC分类号： H03M300
CPC分类号： H03M3/428 , H03M3/436
摘要： An apparatus and method of improving linearity of a multi bit &Dgr;&Sgr; modulator in which the output of a multi-bit quantizer of a &Dgr;&Sgr; modulator is connected in a feedback loop to a converter where output is a higher frequency single bit data stream which is supplied to a 1-bit digital to analog converter whose output is fed back to the quantizer to provide linearity of the output of the &Dgr;&Sgr; modulator.
摘要翻译：一种提高多位DELTASIGMA调制器的线性度的装置和方法，其中DELTASIGMA调制器的多位量化器的输出在反馈环路中连接到转换器，其中输出是较高频率的单位数据流，其被提供给 1位数模转换器，其输出反馈给量化器，以提供DELTASIGMA调制器输出的线性。

7. 发明授权

US06424279B1 Sigma-delta analog-to-digital converter using mixed-mode integrator 失效
标题翻译：使用混合模式积分器的Sigma-delta模数转换器
公开(公告)号：US06424279B1
公开(公告)日：2002-07-23
申请号：US09598625
申请日：2000-06-21
申请人： Beomsup Kim , Taehoon Kim
发明人： Beomsup Kim , Taehoon Kim
IPC分类号： H03M300
CPC分类号： H03M3/362 , H03M3/428 , H03M3/454
摘要： The present invention relates to a sigma-delta analog-to-digital converter using a mixed mode integrator composed of an analog integrator and a digital integrator, which can prevent the performance degradation due to the saturation of an integrator of the overload of a quantizer. A sigma-delta analog-to-digital converter having an anti-aliasing filter, a sample and hold circuit, a sigma-delta modulator and a decimation filter comprises an overload estimating unit for judging the saturation or overload of an analog integrator; a mixed mode integrator which has the analog integrator and a digital integrator composed of a digital adder and a digital storing unit and integrates the output of the overload estimating unit in analog or digitally; and a quantization unit for converting the output of the mixed mode integrator to a digital signal.
摘要翻译：本发明涉及一种使用由模拟积分器和数字积分器组成的混合模式积分器的Σ-Δ模数转换器，其可以防止由于量化器的过载的积分器的饱和引起的性能劣化。具有抗混叠滤波器，采样和保持电路，Σ-Δ调制器和抽取滤波器的Σ-Δ模数转换器包括用于判断模拟积分器的饱和或过载的过载估计单元; 具有模拟积分器的混合模式积分器和由数字加法器和数字存储单元组成的数字积分器，并且以模拟或数字方式对过载估计单元的输出进行积分; 以及用于将混合模式积分器的输出转换为数字信号的量化单元。

8. 发明申请

US20170194984A1 VCO-BASED CONTINUOUS-TIME SIGMA DELTA MODULATOR EQUIPPED WITH TRUNCATION CIRCUIT AND PHASE-DOMAIN EXCESS LOOP DELAY COMPENSATION 审中-公开
公开(公告)号：US20170194984A1
公开(公告)日：2017-07-06
申请号：US15461502
申请日：2017-03-17
申请人： MEDIATEK INC.
发明人： Sheng-Jui Huang , Michael A. Ashburn, JR. , Divya Kesharwani , Nathan Egan
IPC分类号： H03M3/00
CPC分类号： H03M3/37 , H03M1/86 , H03M3/422 , H03M3/424 , H03M3/428 , H03M3/464
摘要： A continuous-time sigma-delta modulator includes a VCO-based quantizer, a rotator, a truncation circuit and a digital-to-analog converter (DAC). The VCO-based quantizer is arranged to generate a thermometer code based on an input signal and a feedback signal. The rotator is coupled to the VCO-based quantizer, and is arranged to generate a phase-shifted thermometer code based on the thermometer code and a phase shift, and generate a rearranged thermometer code based on the phase-shifted thermometer code to comply with a specific pattern. The truncation circuit is coupled to the rotator, and is arranged to extract a most significant bit (MSB) part from the rearranged thermometer code. The DAC is coupled to the truncation circuit, and is arranged to generate the feedback signal according to at least the MSB part. Two alternative continuous-time sigma-delta modulators are also disclosed.

9. 发明申请

US20120274495A1 MULTI-BIT SIGMA-DELTA MODULATOR WITH REDUCED NUMBER OF BITS IN FEEDBACK PATH 审中-公开
标题翻译：在反馈路径中具有减少位数的多位SIGMA-DELTA调制器
公开(公告)号：US20120274495A1
公开(公告)日：2012-11-01
申请号：US13548069
申请日：2012-07-12
申请人： Robert Henrikus Margaretha Van Veldhoven
发明人： Robert Henrikus Margaretha Van Veldhoven
IPC分类号： H03M3/02
CPC分类号： H03M3/428 , H03M3/452 , H03M7/302
摘要： A sigma-delta modulator for an ADC, passes an input signal to a loop filter, then to a multi-bit quantizer of the modulator. An output of the quantizer is passed to a digital filter, and a feedback signal is passed back to the loop filter, the feedback signal having fewer bits than are produced by the multi-bit quantizer. The digital filter has an order greater than one in the passband of the sigma-delta modulator.
摘要翻译：用于ADC的Σ-Δ调制器将输入信号传递到环路滤波器，然后传送到调制器的多位量化器。量化器的输出被传递到数字滤波器，并且反馈信号被传回到环路滤波器，反馈信号具有比由多位量化器产生的位少的位。数字滤波器在Σ-Δ调制器的通带中具有大于1的阶数。

10. 发明申请

US20110187570A1 SIGMA DELTA CONVERTER SYSTEM AND METHOD 审中-公开
标题翻译： SIGMA DELTA转换器系统和方法
公开(公告)号：US20110187570A1
公开(公告)日：2011-08-04
申请号：US13081918
申请日：2011-04-07
申请人： Giri NK Rangan , Roger Levinson , John M. Caruso
发明人： Giri NK Rangan , Roger Levinson , John M. Caruso
IPC分类号： H03M3/02
CPC分类号： H03M3/428 , H03M3/452
摘要： A sigma delta converter system and method includes a multi bit quantizer circuit coupled to an output of the converter. A single bit analog-to-digital converter circuit is contained in a feedback path of the converter. The converter includes a feed forward path operable to multiply an input voltage by a feed forward coefficient having a value that is a function of a gain control input signal. The gain control input signal can have a value that is a function of the output of the multi bit quantizer.
摘要翻译： Σ-Δ转换器系统和方法包括耦合到转换器的输出端的多位量化器电路。单个位模数转换器电路包含在转换器的反馈路径中。该转换器包括前馈路径，其可操作以将输入电压乘以具有作为增益控制输入信号的函数的值的前馈系数。增益控制输入信号可以具有作为多位量化器的输出的函数的值。

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