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1. 发明授权

US11882316B2 System and methods for data compression and nonuniform quantizers 有权
公开(公告)号：US11882316B2
公开(公告)日：2024-01-23
申请号：US17839060
申请日：2022-06-13
申请人： CABLE TELEVISION LABORATORIES, INC.
发明人： Zhensheng Jia , Luis Alberto Campos , Mu Xu , Jing Wang
IPC分类号： H04N19/94 , H04N19/126 , H03M3/00 , H04J14/04 , H03M1/00 , H03M3/04 , H03M1/66 , H03M1/12 , H03M7/30
CPC分类号： H04N19/94 , H03M1/008 , H03M1/1235 , H03M1/664 , H03M3/04 , H03M3/41 , H03M3/504 , H03M7/30 , H04J14/04 , H04N19/126 , H03M7/3082
摘要： An optical network includes a transmitting portion configured to (i) encode an input digitized sequence of data samples into a quantized sequence of data samples having a first number of digits per sample, (ii) map the quantized sequence of data samples into a compressed sequence of data samples having a second number of digits per sample, the second number being lower than the first number, and (iii) modulate the compressed sequence of data samples and transmit the modulated sequence over a digital optical link. The optical network further includes a receiving portion configured to (i) receive and demodulate the modulated sequence from the digital optical link, (ii) map the demodulated sequence from the second number of digits per sample into a decompressed sequence having the first number of digits per sample, and (iii) decode the decompressed sequence.

2. 发明申请

US20170085349A1 ANALOG-TO-DIGITAL CONVERTER WITH BANDPASS NOISE TRANSFER FUNCTION 有权
公开(公告)号：US20170085349A1
公开(公告)日：2017-03-23
申请号：US15165088
申请日：2016-05-26
申请人： MediaTek Inc.
发明人： Stacy Ho , Wei-Hsin Tseng
IPC分类号： H04L5/00 , H03M3/00 , H03M1/06 , H04B1/12 , H03M1/46
CPC分类号： H04L5/0041 , H03M1/0617 , H03M1/466 , H03M3/406 , H03M3/41 , H03M3/426 , H03M3/47 , H04B1/0075 , H04B1/123 , H04L5/001 , H04L27/2647
摘要： Methods and apparatus for providing bandpass analog to digital conversion (ADC) in RF receiver circuitry of a wireless-communication device. The bandpass ADC includes first noise-shaping successive approximation register (NS-SAR) circuitry arranged in a first path and second NS-SAR circuitry arranged in a second path parallel to the first path, wherein the first and second NS-SAR circuitries are configured to alternately sample an analog input voltage at a particular sampling rate and to output a digital voltage at the particular sampling rate.

3. 发明授权

US08717212B2 Bandpass-sampling delta-sigma demodulator 失效
标题翻译：带通采样δ-sigma解调器
公开(公告)号：US08717212B2
公开(公告)日：2014-05-06
申请号：US13623350
申请日：2012-09-20
申请人： Phuong Huynh
发明人： Phuong Huynh
IPC分类号： H03M3/00
CPC分类号： H03M3/02 , H03M3/40 , H03M3/41
摘要： An improved quadrature bandpass-sampling delta-sigma analog-to-digital demodulator is provided, which includes a loop filter, an A/D responsive to the loop filter, and a first feedback D/A responsive to the A/D up-converted in frequency by a first multiplier and a clock. A first summing circuit is responsive to the first D/A and an RF input for providing an input to the loop filter. A plurality of feedback D/As is responsive to the A/D up-converted in different frequencies by a plurality of multipliers and a plurality of clocks for providing feedback inputs to the loop filter. The loop filter comprises a plurality of resonators arranged in cascade configuration, a plurality of analog mixers to provide frequency shifting of the error signals propagating through the resonators, and a plurality of summing circuits responsive to the feedback D/As.
摘要翻译：提供了改进的正交带通采样Δ-Σ模数转换器，其包括环路滤波器，响应于环路滤波器的A / D和响应于A / D上变频的第一反馈D / A 频率乘第一乘法器和时钟。第一求和电路响应于第一D / A和RF输入，用于向环路滤波器提供输入。多个反馈D / AA响应于通过多个乘法器在不同频率中上变频的A / D和用于向环路滤波器提供反馈输入的多个时钟。环路滤波器包括以级联配置布置的多个谐振器，多个模拟混频器，用于提供通过谐振器传播的误差信号的频移，以及响应于反馈D / A的多个求和电路。

4. 发明授权

US07715490B2 Spectral emission shaping sigma delta modulator for wireless applications 有权
标题翻译：用于无线应用的光谱发射整形Σ-Δ调制器
公开(公告)号：US07715490B2
公开(公告)日：2010-05-11
申请号：US11370580
申请日：2006-03-08
申请人： Sameh S. Rezeq
发明人： Sameh S. Rezeq
IPC分类号： H04L27/00
CPC分类号： H03M7/3022 , H03L7/1976 , H03L2207/50 , H03M1/682 , H03M1/747 , H03M3/41 , H03M3/50 , H03M7/3042
摘要： A novel sigma delta amplitude modulator having a noise transfer function adapted to shift quantization noise outside at least one frequency band of interest. In one embodiment, the sigma delta amplitude modulator includes a programmable order low pass stage. In a second embodiment, the sigma delta amplitude modulator incorporates comb filtering wherein each comb filter comprises a plurality of fingers to permit greater programmability in the frequency location of notches. A polar transmitter incorporating the sigma delta amplitude modulator is presented that shapes the spectral emissions of the digitally-controlled power amplifier such that they are significantly and sufficiently attenuated in one or more desired frequency bands.
摘要翻译：一种具有适于将感兴趣的至少一个频带外的量化噪声移位的噪声传递函数的新颖Σ-Δ幅度调制器。在一个实施例中，Σ-Δ幅度调制器包括可编程次序低通级级。在第二实施例中，Σ-Δ幅度调制器包括梳状滤波，其中每个梳状滤波器包括多个指状物，以允许在缺口的频率位置中具有更大的可编程性。提出了一种结合了Σ-Δ幅度调制器的极化发射器，其形成了数字控制的功率放大器的频谱发射，使得它们在一个或多个期望的频带中被显着地和充分地衰减。

5. 发明授权

US07602325B2 Sigma delta analog to digital converter with internal synchronous demodulation 有权
标题翻译：具有内部同步解调功能的Σ-Δ模数转换器
公开(公告)号：US07602325B2
公开(公告)日：2009-10-13
申请号：US11966138
申请日：2007-12-28
申请人： Andrew Hutchinson
发明人： Andrew Hutchinson
IPC分类号： H03M3/00
CPC分类号： H03M3/41 , H03M3/43 , H03M3/456
摘要： A sigma-delta (ΣΔ) analog to digital converter with internal synchronous demodulation responsive to a sample clock, reference clock and conversion clock including a sample switching circuit responsive to an AC input to sample the AC input at the sample clock rate; the sample switching circuit including first and second input switches responsive to the reference clock for selectively, alternately sampling the positive and the negative AC input at the reference clock rate; and an inverter circuit responsive to the reference clock and the sample clock for reversing the polarity of signals from the sample clock in synchronism with the reference clock to reverse the sense of the input switches and synchronously demodulating the AC input within the converter.
摘要翻译：具有响应于采样时钟的内部同步解调的Σ-Δ（SigmaDelta）模数转换器，参考时钟和转换时钟包括响应于AC输入的采样开关电路，以采样时钟速率对AC输入进行采样; 所述采样切换电路包括响应于所述参考时钟的第一和第二输入开关，用于选择性地以参考时钟速率交替地对正和负的AC输入进行采样; 以及响应于参考时钟和采样时钟的反相器电路，用于与参考时钟同步地反转来自采样时钟的信号的极性，以反转输入开关的感测并同步解调转换器内的AC输入。

6. 发明申请

US20090167580A1 SIGMA DELTA ANALOG TO DIGITAL CONVERTER WITH INTERNAL SYNCHRONOUS DEMODULATION 有权
标题翻译： SIGMA DELTA模拟到具有内部同步解调的数字转换器
公开(公告)号：US20090167580A1
公开(公告)日：2009-07-02
申请号：US11966138
申请日：2007-12-28
申请人： Andrew HUTCHINSON
发明人： Andrew HUTCHINSON
IPC分类号： H03M3/02
CPC分类号： H03M3/41 , H03M3/43 , H03M3/456
摘要： A sigma-delta (ΣΔ) analog to digital converter with internal synchronous demodulation responsive to a sample clock, reference clock and conversion clock including a sample switching circuit responsive to an AC input to sample the AC input at the sample clock rate; the sample switching circuit including first and second input switches responsive to the reference clock for selectively, alternately sampling the positive and the negative AC input at the reference clock rate; and an inverter circuit responsive to the reference clock and the sample clock for reversing the polarity of signals from the sample clock in synchronism with the reference clock to reverse the sense of the input switches and synchronously demodulating the AC input within the converter.
摘要翻译：具有响应于采样时钟的内部同步解调的Σ-Δ（SigmaDelta）模数转换器，参考时钟和转换时钟包括响应于AC输入的采样开关电路，以采样时钟速率对AC输入进行采样; 所述采样切换电路包括响应于所述参考时钟的第一和第二输入开关，用于选择性地以参考时钟速率交替地对正和负的AC输入进行采样; 以及响应于参考时钟和采样时钟的反相器电路，用于与参考时钟同步地反转来自采样时钟的信号的极性，以反转输入开关的感测并同步解调转换器内的AC输入。

7. 发明申请

US20090002211A1 Radio Frequency Sigma-Delta-Modulator 有权
标题翻译：射频Σ-Δ调制器
公开(公告)号：US20090002211A1
公开(公告)日：2009-01-01
申请号：US12097097
申请日：2006-12-11
申请人： Lucien Johannes Breems , Dominicus Martinus Leenaerts
发明人： Lucien Johannes Breems , Dominicus Martinus Leenaerts
IPC分类号： H03M3/00
CPC分类号： H03M3/354 , H03M3/382 , H03M3/41
摘要： A radio-frequency ΣΔ-modulator comprises a first mixer in the forward path for down-converting the signals in this forward path with a local oscillator frequency and a second mixer in the feedback path for up-converting the feedback signal with the same local oscillator frequency. Delays between the two mixing operations cause a loss of gain in the loop of the ΣΔ-modulator. An adjustable amplifier in the feedback path compensates for this loss of gain.
摘要翻译：射频SigmaDelta调制器包括在正向路径中的第一混频器，用于以本地振荡器频率对该正向路径中的信号进行下变频，并且反馈路径中的第二混频器用于使用相同的本地振荡器对反馈信号进行上变频频率。两个混合操作之间的延迟导致SigmaDelta调制器的环路中的增益损失。反馈路径中的可调放大器可补偿此增益损失。

8. 发明申请

US20080284635A1 TRANSDUCER DEVICE 有权
标题翻译：传感器设备
公开(公告)号：US20080284635A1
公开(公告)日：2008-11-20
申请号：US12120659
申请日：2008-05-15
申请人： Werner Blatz , Robert Dvorszky , Ulrich Grosskinsky , Lourans Samid , Marco Schwarzmueller
发明人： Werner Blatz , Robert Dvorszky , Ulrich Grosskinsky , Lourans Samid , Marco Schwarzmueller
IPC分类号： H03M1/34
CPC分类号： H03M3/322 , H03M3/40 , H03M3/41
摘要： A transducer device for converting an analog DC voltage signal into a digital signal is provided, with an oscillator device for outputting a first oscillator signal and a second oscillator signal, whereby the oscillator device is formed to generate the first oscillator signal and the second oscillator signal phase-locked to one another and with the substantially same frequency from a reference signal, with an analog frequency converter connected to the oscillator device for transforming the analog DC voltage signal by the first oscillator signal in a first spectral range with a first center frequency to obtain a transformed signal, with an analog-to-digital converter for converting the transformed signal into a transformed digital signal; and with a digital frequency converter connected to the oscillator device for transforming the transformed digital signal by means of the second oscillator signal in a second spectral range with a second center frequency to obtain the digital signal.
摘要翻译：提供了一种用于将模拟直流电压信号转换为数字信号的换能器装置，具有用于输出第一振荡器信号和第二振荡器信号的振荡器装置，由此形成振荡器装置以产生第一振荡器信号和第二振荡器信号相互锁定并且具有与参考信号基本上相同的频率，其中模拟频率转换器连接到振荡器装置，用于在第一频谱范围内利用第一中心频率将第一振荡器信号的模拟直流电压信号变换为使用用于将经变换的信号转换成变换的数字信号的模数转换器获得变换的信号; 以及连接到所述振荡器装置的数字频率转换器，用于通过具有第二中心频率的第二频谱范围内的所述第二振荡器信号变换所述经变换的数字信号，以获得所述数字信号。

9. 发明授权

US07190293B2 Sigma-delta analog-to-digital converter and method for reducing harmonics 有权
标题翻译： Σ-Δ模数转换器和减少谐波的方法
公开(公告)号：US07190293B2
公开(公告)日：2007-03-13
申请号：US10515561
申请日：2003-05-19
申请人： Patrick Clement , Nadim Khlat
发明人： Patrick Clement , Nadim Khlat
IPC分类号： H03M1/12
CPC分类号： H03M3/466 , H03M3/41
摘要： An arrangement (100) and method for sigma-delta analog-to-digital conversion by providing parallel translating sigma-delta analog-to-digital converters (21, 22) and summing their outputs to produce a digital output signal having a bandwidth greater than that of the first or second translating sigma-delta analog-to-digital converters (21, 22). The parallel translating sigma-delta analog-to-digital converters (21, 22) use switching sequences arranged to cancel third and fifth harmonics in the digital output signal. Orthogonality error in the switching sequences applied to the sigma-delta modulators is compensated by adjusting the phase of the signals applied to mixers (51, 52).
摘要翻译：一种用于通过提供并行转换Σ-Δ模数转换器（21,22）并对其输出进行求和以产生具有大于或等于的带宽的数字输出信号的Σ-Δ模数转换的装置（100）和方法第一或第二平移Σ-Δ模数转换器（21,22）的转换。并行转换Σ-Δ模数转换器（21,22）使用布置成消除数字输出信号中的第三和第五谐波的开关序列。通过调整施加到混合器（51,52）的信号的相位来补偿施加到Σ-Δ调制器的开关序列中的正交性误差。

10. 发明申请

US20060111074A1 Hybrid heterodyne transmitters and receivers 有权
标题翻译：混合外差发射机和接收机
公开(公告)号：US20060111074A1
公开(公告)日：2006-05-25
申请号：US11208430
申请日：2005-08-19
申请人： Eugene Petilli , Brian Jadus , Clyde Washburn , John Alvermann
发明人： Eugene Petilli , Brian Jadus , Clyde Washburn , John Alvermann
IPC分类号： H04B1/26 , H04B1/16 , H04B15/00
CPC分类号： H04B1/28 , H03M3/364 , H03M3/40 , H03M3/41 , H03M3/438 , H03M3/496 , H04B1/001 , H04B1/0017 , H04B1/0025
摘要： Disclosed are hybrid heterodyne transmitters and receivers for use in communications systems, or other systems, and the corresponding methods for hybrid heterodyne transmitting and receiving. A heterodyne receiver for converting a continuous time modulated signal to a discrete time digital baseband signal includes a sigma-delta modulator. The sigma-delta modulator is a sigma-delta analog-to-digital converter constructed and arranged to receive a modulated signal at an RF carrier frequency and provide a quantized output at a first intermediate frequency. The heterodyne receiver may also include a digital mixer constructed and arranged to receive a data stream quantized by the sigma-delta analog-to-digital converter and receive a signal at a second mixing frequency. The digital mixer then provides digital signals representative of a baseband signal suitable for digital signal processing.
摘要翻译：公开了用于通信系统或其他系统的混合外差发射机和接收机以及用于混合外差发射和接收的相应方法。用于将连续时间调制信号转换为离散时间数字基带信号的外差接收器包括Σ-Δ调制器。 Σ-Δ调制器是构造和布置为以RF载波频率接收调制信号并在第一中频提供量化输出的Σ-Δ模拟 - 数字转换器。外差接收机还可以包括构造和布置成接收由Σ-Δ模数转换器量化并以第二混频器接收信号的数据流的数字混频器。然后，数字混合器提供表示适合于数字信号处理的基带信号的数字信号。

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