专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明申请

US20170039034A1 THRESHOLD FILTERING OF COMPRESSED DOMAIN DATA USING STEERING VECTOR 审中-公开
标题翻译：使用转向矢量对压缩域数据进行阈值滤波
公开(公告)号：US20170039034A1
公开(公告)日：2017-02-09
申请号：US15296139
申请日：2016-10-18
申请人： Intel Corporation
发明人： SUDHIR K. SATPATHY , SANU K. MATHEW , RAM K. KRISHNAMURTHY
IPC分类号： G06F7/533
CPC分类号： G06F7/533 , G06F7/24 , G06F7/5443 , G06T7/74 , G06T7/97 , H04N19/48 , H04N19/85
摘要： In an embodiment, a processor includes a compression domain threshold filter coupled to a plurality of cores. The compression domain threshold filter is to: receive a sample vector of compressed data to be filtered; calculate, based at least on a first subset of the elements of the sample vector, an estimated upper bound value of a dot product of the sample vector and a steering vector; determine whether the estimated upper bound value of the dot product satisfies a filter threshold value; and in response to a determination that the estimated upper bound value of the dot product does not satisfy the filter threshold value, discard the sample vector without completion of a calculation of the dot product of the sample vector and the steering vector. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括耦合到多个核的压缩域阈值滤波器。压缩域阈值滤波器是：接收要滤波的压缩数据的采样向量; 至少基于样本矢量的元素的第一子集计算样本矢量和导向矢量的点积的估计上限值; 确定点积的估计上限值是否满足滤波器阈值; 并且响应于确定点积的估计上限值不满足滤波器阈值，而不完成样本矢量和导向矢量的点乘积的计算而丢弃样本矢量。描述和要求保护其他实施例。

12. 发明授权

US09459831B2 Fast computation of products by dyadic fractions with sign-symmetric rounding errors 有权
$Fast computation of products by dyadic fractions with sign-symmetric rounding errors$
标题翻译：通过具有符号对称舍入误差的二进制分数快速计算产品
公开(公告)号：US09459831B2
公开(公告)日：2016-10-04
申请号：US14332028
申请日：2014-07-15
申请人： QUALCOMM Incorporated
发明人： Yuriy Reznik
IPC分类号： G06F7/483 , G06F7/533 , G06F17/14 , H04N19/60 , H04N19/42 , G06F7/499
CPC分类号： G06F7/483 , G06F7/49942 , G06F7/533 , G06F17/147 , H04N19/42 , H04N19/60
摘要： A product of an integer value and an irrational value may be determined by a sign-symmetric algorithm. A process may determine possible algorithms that minimize metrics such as mean asymmetry, mean error, variance of error, and magnitude of error. Given an integer variable x and rational dyadic constants that approximate the irrational fraction, a series of intermediate values may be produced that are sign-symmetric. The intermediate values may include a sequence of addition, subtraction and right shift operations the when summed together approximate the product of the integer and irrational value. Other operations, such as additions or subtractions of 0s or shifts by 0 bits may be removed.
摘要翻译：可以通过符号对称算法来确定整数值和非理性值的乘积。过程可以确定最小化度量的可能算法，例如平均不对称性，平均误差，误差方差和误差大小。给定一个整数变量x和近似非理性分数的有理二元常数，可以产生一系列中间值，这些中间值是符号对称的。中间值可以包括加法，减法和右移操作的序列，当加在一起近似整数和非理性值的乘积时。可以删除其他操作，例如0的加法或减法或0位的移位。

13. 发明授权

US09274751B2 Fused booth encoder multiplexer 有权
标题翻译：熔模展位编码器多路复用器
公开(公告)号：US09274751B2
公开(公告)日：2016-03-01
申请号：US11776454
申请日：2007-07-11
申请人： Wendy Ann Belluomini , Hung Cai Ngo , Jun Sawada
发明人： Wendy Ann Belluomini , Hung Cai Ngo , Jun Sawada
IPC分类号： G06F7/533 , G06F7/483 , G06F7/544
CPC分类号： G06F7/5338 , G06F7/483 , G06F7/533 , G06F7/5443 , G06F2207/3872
摘要： A multiplier circuit comprises a fused Booth encoder multiplexer which produces partial product bits, a tree which uses the partial product bits to generate partial products, and an adder which uses the partial products to generate intermediate sum and carry results for a multiplication operation. The fused Booth encoder multiplexer utilizes encoder-selector cells having a logic tree which carries out a Boolean function according to a Booth encoding and selection algorithm to produce one of the partial product bits at a dynamic node, and a latch connected to the dynamic node which maintains the value at an output node. The encoder-selector cells operate in parallel to produce the partial product bits generally simultaneously. A given one of the encoder-selector cells has a unique set of both multiplier operand inputs and multiplicand operand inputs, and produces a single partial product bit.
摘要翻译：乘法器电路包括产生部分乘积比特的融合布尔编码器多路复用器，使用部分积比特产生部分乘积的树，以及使用部分乘积来生成中间和并携带乘法运算结果的加法器。融合布尔编码器多路复用器利用具有逻辑树的编码器选择器单元，该逻辑树根据布斯编码和选择算法执行布尔函数，以在动态节点处产生部分乘积比特中的一个，以及连接到动态节点的锁存器，在输出节点维护该值。编码器选择器单元并行操作以通常同时产生部分乘积位。编码器选择器单元中的一个具有唯一的乘法器操作数输入和被乘数操作数输入的集合，并且产生单个部分乘积位。

14. 发明授权

US08229992B2 Fused booth encoder multiplexer 失效
标题翻译：熔模展位编码器多路复用器
公开(公告)号：US08229992B2
公开(公告)日：2012-07-24
申请号：US11670357
申请日：2007-02-01
申请人： Wendy Ann Belluomini , Hung Cai Ngo , Jun Sawada
发明人： Wendy Ann Belluomini , Hung Cai Ngo , Jun Sawada
IPC分类号： G06F7/52
CPC分类号： G06F7/5338 , G06F7/483 , G06F7/533 , G06F7/5443 , G06F2207/3872
摘要： A multiplier circuit comprises a fused Booth encoder multiplexer which produces partial product bits, a tree which uses the partial product bits to generate partial products, and an adder which uses the partial products to generate intermediate sum and carry results for a multiplication operation. The fused Booth encoder multiplexer utilizes encoder-selector cells having a logic tree which carries out a Boolean function according to a Booth encoding and selection algorithm to produce one of the partial product bits at a dynamic node, and a latch connected to the dynamic node which maintains the value at an output node. The encoder-selector cells operate in parallel to produce the partial product bits generally simultaneously. A given one of the encoder-selector cells has a unique set of both multiplier operand inputs and multiplicand operand inputs, and produces a single partial product bit.
摘要翻译：乘法器电路包括产生部分乘积比特的融合布尔编码器多路复用器，使用部分积比特产生部分乘积的树，以及使用部分乘积来生成中间和并携带乘法运算结果的加法器。融合布尔编码器多路复用器利用具有逻辑树的编码器选择器单元，该逻辑树根据布斯编码和选择算法执行布尔函数，以在动态节点处产生部分乘积比特中的一个，以及连接到动态节点的锁存器，在输出节点维护该值。编码器选择器单元并行操作以通常同时产生部分乘积位。编码器选择器单元中的一个具有唯一的乘法器操作数输入和被乘数操作数输入的集合，并且产生单个部分乘积位。

15. 发明授权

US07373368B1 Multiply execution unit that includes 4:2 and/or 5:3 compressors for performing integer and XOR multiplication 有权
标题翻译：包括4：2和/或5：3压缩器的执行单元，用于执行整数和XOR乘法
公开(公告)号：US07373368B1
公开(公告)日：2008-05-13
申请号：US10891978
申请日：2004-07-15
申请人： Leonard D. Rarick , Shu-Chin Tai
发明人： Leonard D. Rarick , Shu-Chin Tai
IPC分类号： G06F7/52
CPC分类号： G06F7/724 , G06F7/533
摘要： A multiply execution unit that can generate the integer product of a multiplicand and a multiplier and is also operable to generate the XOR product of the multiplicand and the multiplier. The multiply execution unit includes a summing circuit for summing a plurality of partial products. The summing circuit includes a plurality of rows. The summing circuit can generate an integer sum of the plurality of partial products and can generate an XOR sum of the plurality of partial products. The summing circuit includes a plurality of compressors in the first row of the summing circuit. The plurality of compressors each has more than three inputs that receive data, a carry output, and a sum output.
摘要翻译：乘法执行单元，其可以生成被乘数和乘数的整数乘积，并且还可操作以产生被乘数和乘数的XOR乘积。乘法执行单元包括用于求和多个部分乘积的求和电路。求和电路包括多行。求和电路可以生成多个部分乘积的整数，并且可以产生多个部分乘积的XOR和。求和电路包括在求和电路的第一行中的多个压缩机。多个压缩机每个具有多于三个接收数据的输入，进位输出和和输出。

16. 发明授权

US06993551B2 Sparse-coefficient functions for reducing computational requirements 失效
公开(公告)号：US06993551B2
公开(公告)日：2006-01-31
申请号：US10122453
申请日：2002-04-12
申请人： J. William Whikehart , Christopher John Hagan
发明人： J. William Whikehart , Christopher John Hagan
IPC分类号： G06F7/52
CPC分类号： G06F7/533 , G06F5/01 , G06F7/607
摘要： A method for reducing computational steps in a digital processor including multiplications producing a plurality of multiplication products. This method specifies a desired multiplication function to be implemented in a digital processor, the desired multiplication function having a respective set of initial coefficients corresponding to each digital multiplier stage of the multiplication function. An initial total number of non-zero bits of the initial coefficients is determined and the initial coefficients are modified. Further, a resulting number of non-zero bits in the modified set of coefficients is quantified. Finally, the modified set of coefficients that result in a reduced number of non-zero bits as compared to the initial coefficients is chosen. The new modified coefficients are implemented in the device by constructing the digital multiplier stages with the modified coefficients. Thus, the digital processor performs a desired multiplication function using “sparse” coefficients to achieve a reduced execution time or lower implementation cost for a given signal conditioning function.

17. 发明申请

US20050050133A1 Switching activity reduced coding for low-power digital signal processing circuitry 失效
标题翻译：开关活动减少了低功耗数字信号处理电路的编码
公开(公告)号：US20050050133A1
公开(公告)日：2005-03-03
申请号：US10650641
申请日：2003-08-28
申请人： Christian Lutkemeyer
发明人： Christian Lutkemeyer
IPC分类号： G06F7/52 , G06F7/533 , H03H17/02
CPC分类号： G06F7/533 , G06F7/5336 , H03H17/0236 , H03H2017/0692
摘要： A system and method for reducing power consumption in digital circuitry by reducing the amount of unnecessary switching in such circuitry. An aspect of the present invention provides a switching-reduction circuit that outputs a signal to a subsequent digital circuit. The value of the signal may depend on the relevance of the signal value to a next output of the subsequent digital circuit. A method according to various aspects of the present invention includes receiving a next input signal. The method further includes determining whether the next input signal may be relevant to a next output of a subsequent digital circuit. The method further includes providing the next input signal to the subsequent digital circuit when the next input signal may be relevant to the next output of the subsequent digital circuit, and providing a previous signal to the subsequent digital circuit when the next input signal will not be relevant to the next output of the subsequent digital circuit.
摘要翻译：一种通过减少这种电路中不必要的切换量来减少数字电路中的功耗的系统和方法。本发明的一个方面提供一种将信号输出到随后的数字电路的开关降低电路。信号的值可以取决于信号值与随后数字电路的下一个输出的相关性。根据本发明的各个方面的方法包括接收下一个输入信号。该方法还包括确定下一个输入信号是否可能与随后数字电路的下一个输出有关。该方法还包括当下一个输入信号可能与随后的数字电路的下一个输出相关时，向随后的数字电路提供下一个输入信号，并且当下一个输入信号不会与后续数字电路的下一个输出相关。

18. 发明授权

US4575812A X.times.Y Bit array multiplier/accumulator circuit 失效
标题翻译： XxY位阵列乘法器/累加器电路
公开(公告)号：US4575812A
公开(公告)日：1986-03-11
申请号：US615989
申请日：1984-05-31
申请人： Kevin L. Kloker , Ronald H. Cieslak
发明人： Kevin L. Kloker , Ronald H. Cieslak
IPC分类号： G06F7/533 , G06F7/50 , G06F7/506 , G06F7/508 , G06F7/52 , G06F7/53 , G06F7/544
CPC分类号： G06F7/533 , G06F7/5016 , G06F7/5332 , G06F7/5443 , G06F2207/3876 , G06F2207/4812 , G06F7/4991 , G06F7/49994
摘要： An X.times.Y bit array multiplier/accumulator circuit is provided for adding an input number having (X+Y) bits to an (X+Y) bit product of an X bit number and a Y bit number, where X and Y are integers. Modified Booth's algorithm is implemented with an array structure which maintains a regular and systematic structure. The array structure uses adders and multiplexers in a predetermined column and row arrangement. Propagation delay is minimized while utilizing the modified Booth's algorithm by using a sum skipping technique and by using inverting logic properties of adders. Sign bit extension is provided by additional logic circuitry and signed/unsigned modes of operation are provided.
摘要翻译：提供一个XxY位阵列乘法器/累加器电路，用于将具有（X + Y）位的输入号与X位数和Y位数的（X + Y）位乘相加，其中X和Y是整数。 Modified Booth的算法采用阵列结构来实现，该阵列结构保持了规则和系统的结构。阵列结构以预定的列和行排列使用加法器和多路复用器。传播延迟最小化，同时利用改进的布斯算法，通过使用跳跃技术和使用加法器的反相逻辑特性。符号位扩展由附加逻辑电路提供，并提供有符号/无符号操作模式。

19. 发明授权

US09965248B2 Threshold filtering of compressed domain data using steering vector 有权
公开(公告)号：US09965248B2
公开(公告)日：2018-05-08
申请号：US15296139
申请日：2016-10-18
申请人： Intel Corporation
发明人： Sudhir K. Satpathy , Sanu K. Mathew , Ram K. Krishnamurthy
IPC分类号： G06F7/544 , H04N19/48 , G06F7/533 , G06F7/24 , H04N19/85 , G06T7/00 , G06T7/73
CPC分类号： G06F7/533 , G06F7/24 , G06F7/5443 , G06T7/74 , G06T7/97 , H04N19/48 , H04N19/85
摘要： In an embodiment, a processor includes a compression domain threshold filter coupled to a plurality of cores. The compression domain threshold filter is to: receive a sample vector of compressed data to be filtered; calculate, based at least on a first subset of the elements of the sample vector, an estimated upper bound value of a dot product of the sample vector and a steering vector; determine whether the estimated upper bound value of the dot product satisfies a filter threshold value; and in response to a determination that the estimated upper bound value of the dot product does not satisfy the filter threshold value, discard the sample vector without completion of a calculation of the dot product of the sample vector and the steering vector. Other embodiments are described and claimed.

20. 发明申请

US20160274866A1 MULTIPLIER PIPELINING OPTIMIZATION WITH A BIT FOLDING CORRECTION 有权
标题翻译：具有折叠校正的多用户管道优化
公开(公告)号：US20160274866A1
公开(公告)日：2016-09-22
申请号：US14664669
申请日：2015-03-20
申请人： Intel Corporation
发明人： T.J. O'DWYER , PIERRE LAURENT
IPC分类号： G06F7/533 , G06F7/72
CPC分类号： G06F7/533 , G06F7/723
摘要： One embodiment provides a system. The system includes a register to store an operand; a multiplier; and optimizer logic to initiate a square/multiply stage to operate on the operand, initiate a reduction stage prior to completion of the square/multiply stage, and determine whether a carry propagation has occurred.
摘要翻译：一个实施例提供一种系统。该系统包括一个用于存储操作数的寄存器; 乘数以及优化器逻辑，用于启动平方/乘法级以对操作数进行操作，在完成平方/乘法级之前启动减少级，并确定是否发生进位传播。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式