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11. 发明授权

US4575812A X.times.Y Bit array multiplier/accumulator circuit 失效
标题翻译： XxY位阵列乘法器/累加器电路
公开(公告)号：US4575812A
公开(公告)日：1986-03-11
申请号：US615989
申请日：1984-05-31
申请人： Kevin L. Kloker , Ronald H. Cieslak
发明人： Kevin L. Kloker , Ronald H. Cieslak
IPC分类号： G06F7/533 , G06F7/50 , G06F7/506 , G06F7/508 , G06F7/52 , G06F7/53 , G06F7/544
CPC分类号： G06F7/533 , G06F7/5016 , G06F7/5332 , G06F7/5443 , G06F2207/3876 , G06F2207/4812 , G06F7/4991 , G06F7/49994
摘要： An X.times.Y bit array multiplier/accumulator circuit is provided for adding an input number having (X+Y) bits to an (X+Y) bit product of an X bit number and a Y bit number, where X and Y are integers. Modified Booth's algorithm is implemented with an array structure which maintains a regular and systematic structure. The array structure uses adders and multiplexers in a predetermined column and row arrangement. Propagation delay is minimized while utilizing the modified Booth's algorithm by using a sum skipping technique and by using inverting logic properties of adders. Sign bit extension is provided by additional logic circuitry and signed/unsigned modes of operation are provided.
摘要翻译：提供一个XxY位阵列乘法器/累加器电路，用于将具有（X + Y）位的输入号与X位数和Y位数的（X + Y）位乘相加，其中X和Y是整数。 Modified Booth的算法采用阵列结构来实现，该阵列结构保持了规则和系统的结构。阵列结构以预定的列和行排列使用加法器和多路复用器。传播延迟最小化，同时利用改进的布斯算法，通过使用跳跃技术和使用加法器的反相逻辑特性。符号位扩展由附加逻辑电路提供，并提供有符号/无符号操作模式。

12. 发明授权

US11836464B2 Method and apparatus for efficient binary and ternary support in fused multiply-add (FMA) circuits 有权
公开(公告)号：US11836464B2
公开(公告)日：2023-12-05
申请号：US17839905
申请日：2022-06-14
申请人： INTEL CORPORATION
发明人： Aditya Varma , Michael Espig
IPC分类号： G06F7/544 , G06F7/533 , G06F9/30 , G06F7/483 , G06N3/063 , G06N3/045
CPC分类号： G06F7/5443 , G06F7/483 , G06F7/533 , G06F9/3001 , G06F9/30014 , G06F9/3016 , G06F9/30112 , G06F2207/3812 , G06N3/045 , G06N3/063
摘要： An apparatus and method for efficiently performing a multiply add or multiply accumulate operation. For example, one embodiment of a processor comprises: a decoder to decode an instruction specifying an operation, the instruction comprising a first operand identifying a multiplier and a second operand identifying a multiplicand; and fused multiply-add (FMA) execution circuitry comprising first multiplication circuitry to perform a multiplication using the multiplicand and multiplier to generate a result for multipliers and multiplicands falling within a first precision range, and second multiplication circuitry to be used instead of the first multiplication circuitry for multipliers and multiplicands falling within a second precision range.

13. 发明授权

US09965248B2 Threshold filtering of compressed domain data using steering vector 有权
公开(公告)号：US09965248B2
公开(公告)日：2018-05-08
申请号：US15296139
申请日：2016-10-18
申请人： Intel Corporation
发明人： Sudhir K. Satpathy , Sanu K. Mathew , Ram K. Krishnamurthy
IPC分类号： G06F7/544 , H04N19/48 , G06F7/533 , G06F7/24 , H04N19/85 , G06T7/00 , G06T7/73
CPC分类号： G06F7/533 , G06F7/24 , G06F7/5443 , G06T7/74 , G06T7/97 , H04N19/48 , H04N19/85
摘要： In an embodiment, a processor includes a compression domain threshold filter coupled to a plurality of cores. The compression domain threshold filter is to: receive a sample vector of compressed data to be filtered; calculate, based at least on a first subset of the elements of the sample vector, an estimated upper bound value of a dot product of the sample vector and a steering vector; determine whether the estimated upper bound value of the dot product satisfies a filter threshold value; and in response to a determination that the estimated upper bound value of the dot product does not satisfy the filter threshold value, discard the sample vector without completion of a calculation of the dot product of the sample vector and the steering vector. Other embodiments are described and claimed.

14. 发明申请

US20160274866A1 MULTIPLIER PIPELINING OPTIMIZATION WITH A BIT FOLDING CORRECTION 有权
标题翻译：具有折叠校正的多用户管道优化
公开(公告)号：US20160274866A1
公开(公告)日：2016-09-22
申请号：US14664669
申请日：2015-03-20
申请人： Intel Corporation
发明人： T.J. O'DWYER , PIERRE LAURENT
IPC分类号： G06F7/533 , G06F7/72
CPC分类号： G06F7/533 , G06F7/723
摘要： One embodiment provides a system. The system includes a register to store an operand; a multiplier; and optimizer logic to initiate a square/multiply stage to operate on the operand, initiate a reduction stage prior to completion of the square/multiply stage, and determine whether a carry propagation has occurred.
摘要翻译：一个实施例提供一种系统。该系统包括一个用于存储操作数的寄存器; 乘数以及优化器逻辑，用于启动平方/乘法级以对操作数进行操作，在完成平方/乘法级之前启动减少级，并确定是否发生进位传播。

15. 发明申请

US20150363170A1 CALCULATION OF A NUMBER OF ITERATIONS 审中-公开
标题翻译：计算一个迭代数
公开(公告)号：US20150363170A1
公开(公告)日：2015-12-17
申请号：US14735271
申请日：2015-06-10
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Klaus M. Kroener , Silvia Melitta Mueller , Manuela Niekisch , Kerstin Schelm
IPC分类号： G06F7/535
CPC分类号： G06F7/5375 , G06F7/48 , G06F7/533
摘要： Performing an arithmetic operation in a data processing unit, including calculating a number of iterations for performing the arithmetic operation with a given number of bits per iteration. The number of bits per iteration is a positive natural number. A number of consecutive digit positions of a digit in a sequence of bits represented in the data processing unit is counted. The length of the sequence is a multiple of the number of bits per iteration. A quotient of the number of consecutive digit positions divided by the number of bits per iteration is calculated, as well as a remainder of the division.
摘要翻译：在数据处理单元中执行算术运算，包括以每次迭代给定的位数来计算用于执行算术运算的迭代次数。每次迭代的位数是正的自然数。对在数据处理单元中表示的比特序列中的数字的连续数位位置进行计数。序列的长度是每次迭代的位数的倍数。计算连续数字位数的数除以每次迭代的位数的商，以及除法的剩余部分。

16. 发明申请

US20140330878A1 FAST COMPUTATION OF PRODUCTS BY DYADIC FRACTIONS WITH SIGN-SYMMETRIC ROUNDING ERRORS 有权
标题翻译：通过具有符号对称错误的DYADIC分段快速计算产品
公开(公告)号：US20140330878A1
公开(公告)日：2014-11-06
申请号：US14332028
申请日：2014-07-15
申请人： QUALCOMM Incorporated
发明人： Yuriy Reznik
IPC分类号： G06F7/483
CPC分类号： G06F7/483 , G06F7/49942 , G06F7/533 , G06F17/147 , H04N19/42 , H04N19/60
摘要： A product of an integer value and an irrational value may be determined by a sign-symmetric algorithm. A process may determine possible algorithms that minimize metrics such as mean asymmetry, mean error, variance of error, and magnitude of error. Given an integer variable x and rational dyadic constants that approximate the irrational fraction, a series of intermediate values may be produced that are sign-symmetric. The intermediate values may include a sequence of addition, subtraction and right shift operations the when summed together approximate the product of the integer and irrational value. Other operations, such as additions or subtractions of 0s or shifts by 0 bits may be removed.
摘要翻译：可以通过符号对称算法来确定整数值和非理性值的乘积。过程可以确定最小化度量的可能算法，例如平均不对称性，平均误差，误差方差和误差大小。给定一个整数变量x和近似非理性分数的有理二元常数，可以产生一系列中间值，这些中间值是符号对称的。中间值可以包括加法，减法和右移操作的序列，当加在一起近似整数和非理性值的乘积时。可以删除其他操作，例如0的加法或减法或0位的移位。

17. 发明授权

US08819095B2 Fast computation of products by dyadic fractions with sign-symmetric rounding errors 有权
$Fast computation of products by dyadic fractions with sign-symmetric rounding errors$
标题翻译：通过具有符号对称舍入误差的二进制分数快速计算产品
公开(公告)号：US08819095B2
公开(公告)日：2014-08-26
申请号：US12139957
申请日：2008-06-16
申请人： Yuriy Reznik
发明人： Yuriy Reznik
IPC分类号： G06F7/14
CPC分类号： G06F7/483 , G06F7/49942 , G06F7/533 , G06F17/147 , H04N19/42 , H04N19/60
摘要： A product of an integer value and an irrational value may be determined by a sign-symmetric algorithm. A process may determine possible algorithms that minimize metrics such as mean asymmetry, mean error, variance of error, and magnitude of error. Given an integer variable x and rational dyadic constants that approximate the irrational fraction, a series of intermediate values may be produced that are sign-symmetric. The intermediate values may include a sequence of addition, subtraction and right shift operations the when summed together approximate the product of the integer and irrational value. Other operations, such as additions or subtractions of 0s or shifts by 0 bits may be removed.
摘要翻译：可以通过符号对称算法来确定整数值和非理性值的乘积。过程可以确定最小化度量的可能算法，例如平均不对称性，平均误差，误差方差和误差大小。给定一个整数变量x和近似非理性分数的有理二元常数，可以产生一系列中间值，这些中间值是符号对称的。中间值可以包括加法，减法和右移操作的序列，当加在一起近似整数和非理性值的乘积时。可以删除其他操作，例如0的加法或减法或0位的移位。

18. 发明申请

US20080098278A1 Multiplier product generation based on encoded data from addressable location 有权
标题翻译：基于可寻址位置的编码数据的乘数乘积生成
公开(公告)号：US20080098278A1
公开(公告)日：2008-04-24
申请号：US11540346
申请日：2006-09-29
申请人： Sanu Mathew , Vishak Venkatraman , Steven K. Hsu , Ram Krishnamurthy
发明人： Sanu Mathew , Vishak Venkatraman , Steven K. Hsu , Ram Krishnamurthy
IPC分类号： G11C29/00
CPC分类号： G11C7/1006 , G06F7/533 , G06F7/5332 , G06F7/5334 , G06F7/74
摘要： For one disclosed embodiment, an apparatus comprises first circuitry to output encoded data from an addressable location based at least in part on an address corresponding to a first number, wherein the encoded data is based at least in part on data that corresponds to the first number and that is encoded for partial product reduction, and second circuitry to generate a product based at least in part on the encoded data and on data corresponding to a second number. Other embodiments are also disclosed.
摘要翻译：对于一个公开的实施例，装置包括至少部分地基于对应于第一号码的地址从可寻址位置输出编码数据的第一电路，其中编码数据至少部分地基于对应于第一号码的数据并且其被编码用于部分产品减少，以及第二电路，用于至少部分地基于编码数据和对应于第二数量的数据来生成产品。还公开了其他实施例。

19. 发明授权

US07257609B1 Multiplier and shift device using signed digit representation 失效
标题翻译：乘数和移位装置使用有符号位表示
公开(公告)号：US07257609B1
公开(公告)日：2007-08-14
申请号：US10399178
申请日：2000-10-16
申请人： Marko Kosunen , Kari Halonen
发明人： Marko Kosunen , Kari Halonen
IPC分类号： G06F15/00 , G06F7/52
CPC分类号： G06F7/5272 , G06F5/015 , G06F7/533 , G06F9/3001 , G06F9/30025
摘要： The present invention proposes a multiplier device performing multiplication of different powers of two serially in time (not in parallel) in order to further reduce the area needed for a hardware realization. By virtue thereof, it is enabled to use only one adder in connection with the multiplication which contributes to a reduced hardware amount and reduced required area for the hardware. A shifter means based on binary weighted shifting is used for shifting in connection with the multiplication, thereby reducing the required hardware amount (number of multiplexers and hardwired shifting elements) and thus reducing the area for hardware implementation still further. The present invention can be used in applications using digital multiplication, such as in digital signal processing DSP, digital filters and/or finite impulse response filters FIR filters as well as programmable and/or adaptive digital filters. As the multiplier is represented in CSD coding, the number of necessary shifting operations can be reduced and the number of necessary additions can be reduced, thus contributing to a reduced area needed for a hardware realization of a shifting means and a multiplier device on a silicon chip.
摘要翻译：本发明提出一种乘法器装置，其在时间上（不是并行）串行地执行两个不同功率的乘法，以便进一步减小硬件实现所需的面积。由此，能够仅使用与乘法相关的一个加法器，这有助于降低硬件量并减少硬件所需的面积。基于二进制加权移位的移位装置用于与乘法相关的移位，从而减少所需的硬件量（多路复用器和硬连线移位元件的数量），从而进一步减少硬件实现的面积。本发明可以用于使用数字乘法的应用中，例如在数字信号处理DSP，数字滤波器和/或有限脉冲响应滤波器FIR滤波器以及可编程和/或自适应数字滤波器中。由于在CSD编码中表示乘法器，可以减少必要的移位操作的数量，并且可以减少必要的相加次数，从而有助于减少移位装置的硬件实现所需的面积和硅上的乘法器装置芯片。

20. 发明授权

US5285271A Digital color matrixing circuit 失效
标题翻译：数字彩色矩阵电路
公开(公告)号：US5285271A
公开(公告)日：1994-02-08
申请号：US700008
申请日：1991-05-14
申请人： Kenneth D. Gennetten
发明人： Kenneth D. Gennetten
IPC分类号： G09G5/00 , G06F7/52 , G06F17/16 , G06T1/00 , G06T5/00 , G06T5/20 , G09G5/02 , H04N1/46 , H04N1/60
CPC分类号： G06F7/533 , G06F17/16 , G06T5/20 , H04N1/60
摘要： An image scanning device, including CCDs provides digital color image data representing an image. A 3-by-3 matrix multiply logic is connected to the image scanning device for modifying or transforming the intensities of each individual color encoded in the digital color image data. The matrix multiply logic has a multiplier and an accumulator. The multiplier provides intermediate products by performing one-stage multiplications between the intensity values for each pixel and the coefficients of the 3-by-3 matrix. The one-stage multiplications are time multiplexed. The accumulator accumulates the intermediate products from the multiplier for each pixel to thereby provide optimized color values for each pixel. The multiplier implements specialized adders to perform the one-stage multiplications.
摘要翻译：包括CCD的图像扫描装置提供表示图像的数字彩色图像数据。将3×3矩阵乘法逻辑连接到图像扫描装置，用于修改或变换在数字彩色图像数据中编码的每个单独颜色的强度。矩阵乘法逻辑具有乘法器和累加器。乘法器通过在每个像素的强度值和3×3矩阵的系数之间执行一阶乘法来提供中间产品。单级乘法是时分复用的。累加器从每个像素的乘数累加中间产物，从而为每个像素提供优化的颜色值。乘法器实现专门的加法器来执行一级乘法。

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