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11. 发明授权

US5534725A Resin molded charge coupled device package and method for preparation thereof 失效
标题翻译：树脂模制电荷耦合器件封装及其制备方法
公开(公告)号：US5534725A
公开(公告)日：1996-07-09
申请号：US337016
申请日：1994-11-07
申请人： Ki R. Hur
发明人： Ki R. Hur
IPC分类号： H01L23/31 , H01L31/0203 , H01L23/495
CPC分类号： H01L23/315 , H01L27/14618 , H01L2224/48091 , H01L2224/48247 , H01L2924/0102 , H01L2924/09701 , H01L2924/16195
摘要： A resin molded CCD package and a method for preparing the CCD package by employing a transfer molding using a low-priced plastic material having a good moldability. This package comprises a semiconductor chip as a CCD, a lead frame being integrally provided with a paddle and a plurality of leads, a film wall being attached to an upper surface of the semiconductor chip such that it surrounds a light reception region of the semiconductor chip, a glass lid for sealing the light reception region and transmitting an outside light to the region, a plurality of metal wires for electrically connecting a plurality of bond pads of the semiconductor chip to individual inner leads of the lead frame, and a mold resin package body for hermetically sealing a predetermined part including the semiconductor chip and the inner leads, both being wire-bonded to each other. The present invention simplifies the preparation process of the CCD package, reduces the preparation cost and achieves the recent trend of compactness and requirement of mass production of the CCD package.
摘要翻译：树脂成型CCD封装以及通过使用具有良好成型性的低价塑料材料的传递模塑来制备CCD封装的方法。该封装包括作为CCD的半导体芯片，一体地设置有焊盘和多个引线的引线框架，薄膜壁附接到半导体芯片的上表面，使得其围绕半导体芯片的光接收区域用于密封光接收区域并将外部光透射到该区域的玻璃盖，用于将半导体芯片的多个接合焊盘电连接到引线框架的各个内部引线的多个金属线，以及模制树脂封装用于密封包括半导体芯片和内部引线的预定部分的两个线彼此线接合。本发明简化了CCD封装的制备过程，降低了制备成本，实现了CCD封装的紧凑化和批量生产的最新趋势。

12. 发明授权

US5526221A Degaussing circuit 失效
标题翻译：去磁电路
公开(公告)号：US5526221A
公开(公告)日：1996-06-11
申请号：US136063
申请日：1993-10-14
申请人： Jong K. An
发明人： Jong K. An
IPC分类号： H01F13/00 , H04N9/29
CPC分类号： H01F13/006 , H04N9/29
摘要： A degaussing circuit comprising a rectifying circuit for rectifying an AC voltage inputted therein into a DC voltage, a capacitor for smoothing the DC voltage from the rectifying circuit, a RC charging circuit for charging with the DC voltage smoothed by the capacitor, a positive temperature coefficient resistor having a resistance which is increased with an increase in a temperature due to an AC current flowing therethrough upon power supply, a degaussing coil for removing a magnetic field in response to the AC current flowing through the positive temperature coefficient resistor thereto, a relay for controlling the flow of the AC current through the positive temperature coefficient resistor to the degaussing coil, and a relay driving circuit for controlling an ON/OFF state of the relay in response to the voltage charged on the RC charging circuit. A transistor in the relay driving circuit is turned off by the voltage charged on the charging circuit as the resistance of the positive temperature coefficient resistor rises due to the AC current after the lapse of a predetermined time period from a point of time of the power supply and the relay is turned off as the transistor is turned off. Therefore, no current flows through the degaussing coil although the resistance of the positive temperature coefficient resistor is reduced as the temperature falls.
摘要翻译： 1.一种消磁电路，包括：整流电路，用于将输入其中的交流电压整流为直流电压;电容器，用于使来自整流电路的直流电压平滑;一个用于对由电容器平滑的直流电压进行充电的RC充电电路;正温度系数电阻器，其电阻随着电源上流过的交流电流而随温度升高而增加，用于响应于流经正温度系数电阻器的交流电流而去除磁场的消磁线圈，用于控制通过所述正温度系数电阻器的所述交流电流流向所述消磁线圈;以及继电器驱动电路，用于响应于在所述RC充电电路上充电的电压来控制所述继电器的接通/断开状态。继电器驱动电路中的晶体管由于在从供电时间经过预定时间段之后由于AC电流而正电温度系数电阻器的电阻上升，充电电路上充电的电压被切断并且当晶体管截止时，继电器关闭。因此，尽管正温度系数电阻器的电阻随着温度的降低而降低，但没有电流流过消磁线圈。

13. 发明授权

US5517142A Output buffer with a reduced transient bouncing phenomenon 失效
标题翻译：输出缓冲器具有减少的瞬态弹跳现象
公开(公告)号：US5517142A
公开(公告)日：1996-05-14
申请号：US294715
申请日：1994-08-23
申请人： Seong J. Jang , Young H. Jun
发明人： Seong J. Jang , Young H. Jun
IPC分类号： G06F3/00 , G11C7/02 , G11C7/10 , H03K19/0175 , H03B1/00
CPC分类号： G11C7/1057 , G11C7/1051
摘要： An output buffer is disclosed. In the prior art, when an output buffer swings to a supply voltage Vcc and a ground voltage Vss, the current drops rapidly at the supply voltage or the ground voltage, thereby generating bouncing of the supply voltage Vcc or bouncing of the ground voltage Vss. For eliminating this phenomenon, a capacitor is provided connected to an output node of the inventive output buffer to reduce the amount of the current flowing to the supply voltage terminal and the ground voltage terminal at the time point at which an output level is changed. Therefore, voltage drop and the bouncing of the supply voltage and the ground voltage is reduced by applying a precharge voltage which is precharged in the capacitor to the output node.
摘要翻译：公开了输出缓冲器。在现有技术中，当输出缓冲器摆动到电源电压Vcc和接地电压Vss时，电流以电源电压或接地电压迅速下降，从而产生电源电压Vcc的跳动或接地电压Vss的跳动。为了消除这种现象，提供连接到本发明的输出缓冲器的输出节点的电容器，以减少在输出电平改变的时间点流向电源电压端子和接地电压端子的电流量。因此，通过将预充电在电容器中的预充电电压施加到输出节点来降低电压降和电源电压和接地电压的跳动。

14. 发明授权

US5481498A Redundancy circuit for semiconductor memory device 失效
标题翻译：半导体存储器件冗余电路
公开(公告)号：US5481498A
公开(公告)日：1996-01-02
申请号：US320341
申请日：1994-10-11
申请人： Seok Woo Han
发明人： Seok Woo Han
IPC分类号： G11C29/00 , G11C29/04 , H01L21/8247 , H01L27/115 , G11C7/00
CPC分类号： G11C29/789
摘要： A memory redundancy circuit using FLOTOX transistors instead of conventional link fuses and thus capable of redundancy programming even after the packaging of the chip. The redundancy circuit is capable of generating spare signals in order to use spare memory cells for particular addresses. The circuit includes: a reference line having a certain voltage level for generating spare signals; a reference voltage supplying circuit for supplying the required voltage to the reference line; two or more FLOTOX transistors connected to the reference line; and high voltage driving circuits provided for the FLOTOX transistors, and connected to address lines in such a manner as to supply the required voltage to the gates of the FLOTOX transistors for programming.
摘要翻译：使用FLOTOX晶体管代替常规链路熔丝的存储器冗余电路，因此即使在芯片封装之后也能进行冗余编程。冗余电路能够产生备用信号，以便为特定地址使用备用存储器单元。该电路包括：具有用于产生备用信号的一定电压电平的参考线; 参考电压提供电路，用于向参考线提供所需的电压; 连接到参考线的两个或多个FLOTOX晶体管; 以及为FLOTOX晶体管提供的高电压驱动电路，并且以向所述FLOTOX晶体管的栅极提供所需电压以进行编程的方式连接到地址线。

15. 发明授权

US5480824A Semiconductor memory cell capacitor and fabrication method thereof 失效
标题翻译：半导体存储单元电容器及其制造方法
公开(公告)号：US5480824A
公开(公告)日：1996-01-02
申请号：US79186
申请日：1993-06-18
申请人： Young-Kwon Jun
发明人： Young-Kwon Jun
IPC分类号： H01L21/302 , H01L21/02 , H01L21/3065 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108 , H01L21/70
CPC分类号： H01L27/10852 , H01L28/92 , Y10S438/947
摘要： A capacitor of a semiconductor memory cell having a maximized capacitance and a process for formation thereof are disclosed. The process is characterized in that a projected portion or a depressed portion is formed. Sets of polysilicon layers and silicon oxide layers are stacked over the projected or depressed portion. The sets of stacked layers are etched back, so that the layers having a slower etch rate remain in the form of multi-layer rims. An underlying silicon oxide layer is etched using the multi-layer rims as a mask to form a multi-layer cylinder. Then a polysilicon layer is deposited and etched back deeper than the thickness of the polysilicon layer. The silicon oxide layer is subjected to a wet etch to form a multi-layer cylindrical storage electrode. Then a dielectric layer and cell plate are formed on the storage electrode.
摘要翻译：公开了具有最大电容的半导体存储单元的电容器及其形成工艺。该方法的特征在于形成突出部分或凹陷部分。多晶硅层和氧化硅层的集合层叠在投影或凹陷部分上。层叠的层被回蚀刻，使得具有较慢蚀刻速率的层保持为多层轮缘的形式。使用多层轮缘作为掩模蚀刻底层氧化硅层以形成多层圆柱体。然后沉积多晶硅层并将其蚀刻回比多晶硅层的厚度更深。对氧化硅层进行湿蚀刻以形成多层圆柱形存储电极。然后在存储电极上形成电介质层和电池板。

16. 发明授权

US5464712A Method for fabricating a phase shifting mask 失效
标题翻译：制造相移掩模的方法
公开(公告)号：US5464712A
公开(公告)日：1995-11-07
申请号：US233069
申请日：1994-04-26
申请人： O. Suk Han
发明人： O. Suk Han
IPC分类号： G03F1/30 , G03F1/68 , H01L21/027 , G03F9/00
CPC分类号： G03F1/30
摘要： A method for fabricating a phase shifting mask suitable for positive photoresist process. The method includes the steps of: (a) forming a plurality of opaque layer patterns (44) in an array at a fixed interval from each other in their width direction on a substrate (41); (b) coating an interlayer (45) on and covering the opaque layer patterns; (c) forming interlayer patterns (45) on the substrate at both longitudinal sides of each opaque layer pattern by etching the interlayer; (d) forming a plurality of insulation films (46) on the substrate between adjacent pairs of the opaque layer patterns on which the interlayer patterns are formed; (e) removing the remaining interlayer under each of the insulation films; and (f) forming a phase shifter (47) having a ninety degree area (47-2) in a region where the interlayer has been removed and a one hundred and eighty degree area (47-1) in the remainder of the region by heating the insulation film.
摘要翻译：一种用于制造适于正性光致抗蚀剂工艺的相移掩模的方法。该方法包括以下步骤：（a）在衬底（41）上以固定的间隔在其宽度方向上以阵列形式形成多个不透明层图案（44）; （b）在中间层（45）上涂覆并覆盖不透明层图案; （c）通过蚀刻中间层在每个不透明层图案的两个纵向侧在基底上形成层间图案（45）; （d）在其上形成有层间图案的不透明层图案的相邻对之间在基板上形成多个绝缘膜（46）; （e）除去每个绝缘膜下的剩余中间层; 以及（f）在去除了中间层的区域中形成有90度区域（47-2）的移相器（47），并且在该区域的其余部分中形成了一个区域（47-1）加热绝缘膜。

17. 发明授权

US5461593A Word-line driver for a semiconductor memory device 失效
标题翻译：用于半导体存储器件的字线驱动器
公开(公告)号：US5461593A
公开(公告)日：1995-10-24
申请号：US326424
申请日：1994-10-20
申请人： Seung-Bong Kim
发明人： Seung-Bong Kim
IPC分类号： G11C11/407 , G11C8/08 , G11C11/418 , G11C16/06 , G11C17/00 , G11C11/40
CPC分类号： G11C8/08
摘要： A word-line driver of a semiconductor memory device having an address buffer for receiving a row address and a word-line decoder for converting an output signal of the address buffer into a word-line decoding signal is disclosed. The word-line driver includes: a first pull-up transistor for transferring a first row selecting signal to a first node connected to a first word line, responding to the word-line decoding signal; a first pull-down transistor connected between the first node and a ground voltage terminal for pulling down a voltage level of the first node, responding to a complementary signal of the first row selecting signal; a second pull-up transistor for transferring a second row selecting signal to a second node connected to a second word line, responding to the word-line decoding signal; a second pull-down transistor connected between the second node and a ground voltage terminal for pulling down a voltage level of the second node, responding to a complementary signal of the second row selecting signal; and a switching transistor connected between the first and second nodes which is controlled by the word-line decoding signal.
摘要翻译：公开了具有用于接收行地址的地址缓冲器和用于将地址缓冲器的输出信号转换为字线解码信号的字线解码器的半导体存储器件的字线驱动器。字线驱动器包括：第一上拉晶体管，用于响应于字线解码信号，将第一行选择信号传送到连接到第一字线的第一节点; 连接在所述第一节点和地电压端子之间的第一下拉晶体管，用于根据所述第一行选择信号的互补信号来降低所述第一节点的电压电平; 第二上拉晶体管，用于响应于所述字线解码信号，将第二行选择信号传送到连接到第二字线的第二节点; 连接在所述第二节点和地电压端子之间的第二下拉晶体管，用于下降所述第二节点的电压电平;响应所述第二行选择信号的互补信号; 以及连接在第一和第二节点之间的开关晶体管，其由字线解码信号控制。

18. 发明授权

US5454705A Semiconductor mold having cavity blocks with cavities on top and bottom surfaces 失效
标题翻译：半导体模具具有在顶表面和底表面上具有空腔的空腔模块
公开(公告)号：US5454705A
公开(公告)日：1995-10-03
申请号：US993424
申请日：1992-12-21
申请人： Seung Dae Back
发明人： Seung Dae Back
IPC分类号： H01L21/56 , B29C45/02 , B29C45/14 , B29C45/26 , B29C45/10
CPC分类号： B29C45/2673
摘要： A metallic mold for molding semiconductor package including a pair of cavity blocks capable of molding two types of semi conductor packages in order to reduce manufacturing cost. The metallic mold includes an upper cavity block to be inserted in its normal state and its turned over state in an upper chase block mounted on a lower surface of a top mold base of an upper mold die which is formed at its upper surface with one type of cavities and at its lower surface with another type of cavities, and a lower cavity block to be inserted in its normal state and its turned over state in a lower chase bock mounted on a bottom mold base of a lower mold base which is formed at its upper surface with cavities mating with the another type of cavities of the upper cavity block and at its lower surface with cavities mating with the one type of cavities of the upper cavity block.
摘要翻译：一种用于模制半导体封装的金属模具，其包括能够模制两种类型的半导体封装的一对空腔模块，以便降低制造成本。该金属模具包括上模块，该上模块在上模具的上表面安装有上模具底座的下表面，其上表面具有一个类型并且在其下表面具有另一种类型的空腔，以及下腔体块，其在正常状态下被插入，并且在下模具底座中的翻盖状态安装在下模具底座上，下模具底座形成在下模具底座上，其上表面具有与上腔模块的另一种类型的空腔配合的空腔，并且在其下表面具有与上腔模块的一种类型的空腔配合的空腔。

19. 发明授权

US5436577A CMOS tri-state buffer circuit and operation method thereof 失效
标题翻译： CMOS三态缓冲电路及其操作方法
公开(公告)号：US5436577A
公开(公告)日：1995-07-25
申请号：US97256
申请日：1993-07-23
申请人： Cheol-Hee Lee
发明人： Cheol-Hee Lee
IPC分类号： H03K19/0175 , H03K17/16 , H03K19/017 , H03K19/00
CPC分类号： H03K17/163
摘要： A 3-state buffer circuit applicable for a CMOS output drive circuit is disclosed. The output circuit provides reduced ground noise and delay time of an output signal by decreasing a counter-electromotive force generated upon turning ON of the output transistor. The circuit includes a subsidiary drive circuit for applying a voltage less than the power source Vcc to a gate of an NMOS transistor connected on the ground side of the drive circuit so that generation of the counter-electromotive force is minimized.
摘要翻译：公开了一种适用于CMOS输出驱动电路的3态缓冲电路。输出电路通过减小在输出晶体管导通时产生的反电动势来减小输出信号的接地噪声和延迟时间。电路包括用于将小于电源Vcc的电压施加到连接在驱动电路的接地侧上的NMOS晶体管的栅极的辅助驱动电路，从而使反电动势的产生最小化。

20. 发明授权

US5426318A Horizontal charge coupled device having a multiple reset gate 失效
标题翻译：具有复位门的水平电荷耦合器件
公开(公告)号：US5426318A
公开(公告)日：1995-06-20
申请号：US867243
申请日：1992-04-10
申请人： Seo K. Lee
发明人： Seo K. Lee
IPC分类号： H01L27/148 , H01L21/339 , H01L29/423 , H01L29/762 , H01L29/768 , H04N5/335 , H04N5/357 , H04N5/369 , H04N5/372 , H01L29/78
CPC分类号： H01L29/42396 , H01L29/76816
摘要： A horizontal charge coupled device (HCCD) is provided with a multiple reset gate in order to establish a more stable, less noisy voltage in an output node floating diffusion. Charges are transferred from an input of the HCCD to the floating diffusion by multiple, overlapping gate structures. Signal charges are detected or read out from the floating diffusion through an amplifier/inverter circuit. Periodically, the voltage of the floating diffusion is established to a reference level by application of a reset signal to a multiple reset gate structure, which results in charges in the floating diffusion being transferred to a reset drain. Noise induced by the reset operation is lessened on average due to the multiple reset gate structure.
摘要翻译：水平电荷耦合器件（HCCD）具有多个复位栅极，以便在输出节点浮动扩散中建立更稳定，更低噪声的电压。充电通过多个重叠的栅极结构从HCCD的输入传输到浮动扩散。通过放大器/逆变器电路从浮动扩散中检测或读出信号电荷。周期性地，浮置扩散的电压通过将复位信号施加到多重复位栅极结构而建立到参考电平，这导致浮动扩散中的电荷被传送到复位漏极。由于多重复位门结构，复位操作引起的噪声平均减小。

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