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11. 发明授权

US4899151A Apparatus for converting digital values to analog values 失效
标题翻译：用于将数字值转换为模拟值的装置
公开(公告)号：US4899151A
公开(公告)日：1990-02-06
申请号：US915784
申请日：1986-10-06
申请人： Joseph H. Colles
发明人： Joseph H. Colles
IPC分类号： H03M1/74 , H03M1/00
CPC分类号： H03M1/687 , H03M1/685
摘要： A plurality of members, each constructed to produce a substantially constant current when energized, are disposed electrically in a matrix defined by a plurality of rows and a plurality of columns. A plurality of signals cumulatively represent a digital value. Each of the signals has logic levels respectively coding for binary "1" and binary "0" and each has an individual binary significance. The binary signals of intermediate binary significance are decoded to activate an individual rows. The binary signals of high binary significance are decoded to activate an individual column. The member common to the activated row and the activated column then receives a substantially constant current, as do all of the members of lower binary signficance than such common member. The signals of lowest binary significance are also decoded to produce a current having a magnitude indicative of the binary value coded by such signals. This magnitude corresponds to that obtained by multiplying a particular portion of the substantially constant current by a ratio having as a numerator the value represented by the binary signals of least binary significance and having as its denominator the maximum value capable of being coded by such binary signals. The current coding for the binary signals of the least binary significance passes through a member otherwise superfluous in the matrix and preferably having an extreme position electrically in the matrix. The currents flowing through the members in the matrix are added in an output line to indicate an analog of the digital value.
摘要翻译：被构造成在通电时产生基本上恒定的电流的多个构件电气地设置在由多个行和多个列限定的矩阵中。多个信号累积地表示数字值。每个信号具有分别编码二进制“1”和二进制“0”的逻辑电平，并且每个具有单独的二进制含义。中间二进制有效的二进制信号被解码以激活单独的行。高二进制有效的二进制信号被解码以激活单独的列。所激活的行和激活的列共同的成员然后接收基本上恒定的电流，与所有这些公共成员相比较低的二进制值的所有成员也是如此。最低二进制有效性的信号也被解码以产生具有表示由这些信号编码的二进制值的幅度的电流。该幅度对应于通过将基本上恒定的电流的特定部分乘以具有由最小二进制有效值的二进制信号表示的值作为分子而具有作为其分母的能够由这种二进制信号编码的最大值的比例而获得的量值。对二进制有意义的二进制信号的当前编码通过在矩阵中多余的成员，优选地在矩阵中具有极端位置。流过矩阵中的构件的电流被添加到输出线中以指示数字值的模拟。

12. 发明授权

US4638241A Regulated current supply 失效
标题翻译：调节电流供应
公开(公告)号：US4638241A
公开(公告)日：1987-01-20
申请号：US775524
申请日：1985-09-13
申请人： Joseph H. Colles
发明人： Joseph H. Colles
IPC分类号： G05F3/24 , H03M1/00 , G05F3/08
CPC分类号： G05F3/247 , H03M1/124
摘要： A first semi-conductor has a first threshold voltage and provides a particular voltage drop across it in its saturated state of operation. A second semi-conductor has a second threshold voltage and provides the particular voltage drop across it in its saturated state of operation. The second semi-conductor may be a native device. The first and second semi-conductors are connected to provide a common flow of current. A current is induced, as by a third semi-conductor, to flow in the second semi-conductor. The first and second semi-conductors are commonly biased to produce a flow of saturated current through them when a current is induced to flow in the second semi-conductor. Each of the first, second and third semi-conductors may be provided with a gate, drain and source. The sources and drains of the semi-conductors may be in series. The gates of the first and second semi-conductors may be commonly biased and the gate of the third semi-conductor may be biased to produce the flow of current through the second and third semi-conductors. A circuit may be connected across the first semi-conductor and may be provided with first and second states of operation. In the first state, the saturated current flows through the third, second and first semi-conductors and, in the second state, the saturated current flows through the third and second semi-conductors and the parallel circuit. The parallel circuit may be included in a digital-to-analog converter in which bits are disposed in rows and columns and in which an analog value is produced by activating bits in selected rows and columns.
摘要翻译：第一半导体具有第一阈值电压并且在其饱和的操作状态下在其上提供特定的电压降。第二半导体具有第二阈值电压，并且在其饱和的操作状态下提供跨越其的特定电压降。第二半导体可以是本地设备。连接第一和第二半导体以提供公共的电流。由第三半导体引起电流在第二半导体中流动。当电流在第二半导体中流动时，第一和第二半导体通常被偏置以产生通过它们的饱和电流。第一，第二和第三半导体中的每一个可以设置有栅极，漏极和源极。半导体的源极和漏极可以是串联的。第一和第二半导体的栅极可以被公共偏置，并且第三半导体的栅极可被偏置以产生通过第二和第三半导体的电流。电路可以跨越第一半导体连接并且可以被提供有第一和第二操作状态。在第一状态下，饱和电流流过第三，第二和第一半导体，并且在第二状态下，饱和电流流过第三和第二半导体和并联电路。并行电路可以包括在数模转换器中，其中位以行和列布置，并且其中通过激活所选行和列中的位产生模拟值。

13. 发明授权

US6075790A Asynchronous transfer mode system for, and method of, writing a cell payload between a control queue on one side of a system bus and a status queue on the other side of the system bus 失效
标题翻译：在系统总线一侧的控制队列与系统总线另一侧的状态队列之间写入单元有效负载的异步传输模式系统及其方法
公开(公告)号：US6075790A
公开(公告)日：2000-06-13
申请号：US764692
申请日：1996-12-11
申请人： Bradford C. Lincoln , David R. Meyer
发明人： Bradford C. Lincoln , David R. Meyer
IPC分类号： H04L12/56 , H04Q11/04 , H04L12/28
CPC分类号： H04Q11/0478 , H04L2012/5616 , H04L2012/5681
摘要： A status queue in a host and a control queue in a segmentation and reassembly (SAR) subsystem are on opposite sides of a host bus in a control plane. Buffer descriptors in the host and the SAR and buffers in the host are in a data plane. To transfer cell payloads to a first line interfacing the SAR, the host writes the SAR that it has such cell payloads. The host writes the host buffer descriptors into the control queue to obtain the transfer of the buffer payload to the first line. The SAR writes the status queue when the transfer has been completed. To transfer cell payloads to the host memory, the host writes into the control queue the address of the buffers to receive the payload from the SAR. The SAR then writes the buffer descriptors to the status queue to obtain the transfer of the cell payloads to the buffers. Each of the control and status queues may be respectively considered to constitute two (2) control queues and two (2) status queues. The SAR determines if either status queue is full by comparing the address written by the SAR into such status queue with the address written by the host periodically to the SAR where the host is in the status queue. The host determines if either control queue is full by comparing the address written by the host into such control queue with the address written by the SAR periodically to the host where the SAR is in the control queue.
摘要翻译：主机中的状态队列和分段和重组（SAR）子系统中的控制队列位于控制平面中的主机总线的相对侧。主机和SAR中的缓冲区描述符和主机中的缓冲区位于数据平面中。为了将信元有效载荷传送到与SAR相连接的第一行，主机写入SAR具有这样的信元有效载荷。主机将主机缓冲区描述符写入控制队列，以获得缓冲区有效载荷到第一行的传输。传输完成后，SAR写状态队列。为了将单元有效载荷传送到主机存储器，主机向控制队列写入从SAR接收有效负载的缓冲器的地址。然后，SAR将缓冲区描述符写入状态队列，以获得单元有效负载到缓冲区的传输。每个控制和状态队列可以分别被认为构成两（2）个控制队列和两个（2）状态队列。 SAR通过将由SAR写入的地址与这样的状态队列进行比较，由主机周期性地向主机处于状态队列的SAR写入地址，确定状态队列是否满。主机通过将由主机写入这样的控制队列的地址与由SAR所写入的地址周期性地向SAR控制队列中的主机进行比较来确定是否任一个控制队列满。

14. 发明授权

US5949781A Controller for ATM segmentation and reassembly 失效
标题翻译：控制器用于ATM分段和重组
公开(公告)号：US5949781A
公开(公告)日：1999-09-07
申请号：US467311
申请日：1995-06-06
申请人： Bradford C. Lincoln , Douglas M. Brady , David R. Meyer , Warner B. Andrews, Jr.
发明人： Bradford C. Lincoln , Douglas M. Brady , David R. Meyer , Warner B. Andrews, Jr.
IPC分类号： H04Q3/00 , H04L12/56 , H04Q11/04
CPC分类号： H04Q11/0478 , H04L12/5601 , H04L2012/561 , H04L2012/5616 , H04L2012/5649 , H04L2012/5651 , H04L2012/5652 , H04L2012/5679
摘要： A header and a payload in a cell are separated for transfer between a cell interface and a host memory. The header is transferred to a control memory. For transfer to the host memory, the control memory initially provides a host-memory region address and the region length. The payload is recorded in such region. The control memory also provides a second host-memory region address, and length, when the payload length exceeds the payload length in the first address region. For transfer from the host memory to the cell interface, the control memory provides a host memory region address and the header combines the header and the payload and passes the combination to the cell interface. Cells from different sources (i.e. terminals) are scheduled at table positions dependent upon their individual transfer rates. The cells at the scheduled positions are normally transferred in time slots corresponding to such positions. When more than one (1) cell is scheduled at the same position, one (1) cell is transferred on a preset priority basis to the corresponding time slot. The other cells are delayed for transfer subsequently in idle time slots (i.e. no cell normally scheduled) in the same or other priorities. The cell delays for each source are accumulated to a maximum preset value. When the cell delays accumulated for a source exceed the normal time spacing between cells from that source, a cell the source transfers a cell in an idle time slot prior to the normally scheduled time slot to compensate for such delay.
摘要翻译：单元格中的标题和有效负载被分离以在单元接口和主机存储器之间传送。标题被传送到控制存储器。为了传输到主机存储器，控制存储器最初提供主机 - 存储器区域地址和区域长度。有效载荷记录在这样的区域。当有效载荷长度超过第一地址区域中的有效载荷长度时，控制存储器还提供第二主机 - 存储器区域地址和长度。为了从主机存储器传送到单元接口，控制存储器提供主机存储器区域地址，并且报头组合报头和有效载荷，并将组合传递到单元接口。来自不同来源（即终端）的小区根据其个人传送速率被安排在表位置。预定位置处的单元通常在对应于这些位置的时隙中传送。当多于一个（1）小区被调度在相同位置时，一（1）个小区以预设的优先级被传送到相应的时隙。在相同或其他优先级中，其他小区被延迟以在空闲时隙（即，没有小区正常安排）中传送。每个源的单元延迟被累积到最大预设值。当来自源的单元延迟超过来自该源的单元之间的正常时间间隔时，源单元在正常调度的时隙之前的空闲时隙中传送单元以补偿这种延迟。

15. 发明授权

US5715437A System for, and method of, processing in hardware commands received from software without polling of the hardware by the software 失效
标题翻译：从软件接收的硬件命令的处理系统和方法，而不用软件轮询硬件
公开(公告)号：US5715437A
公开(公告)日：1998-02-03
申请号：US337939
申请日：1994-11-10
申请人： David C. Baker , Michael D. Asal
发明人： David C. Baker , Michael D. Asal
IPC分类号： G06F3/153 , G06F9/24 , G06F9/38 , G06T11/00 , G09G5/36 , G06T1/60 , G06F15/76
CPC分类号： G06F9/3814 , G06F9/24 , G06F9/3802 , G06F9/3879
摘要： A CPU introduces software commands to a first limited capacity memory (e.g. FIFO), on an integrated circuit chip. Data (e.g. graphics) from a first portion of a second memory (off chip) is processed in accordance with such commands. A second portion (e.g. FIFO) of the second memory may also store commands normally passing from the CPU through the first memory. When the first memory becomes full, the commands may pass from the CPU through the second portion of the second memory (which may have a storage capacity considerably greater than that of the first memory) and then through the first memory. The commands may continue to flow in this auxiliary path until the second portion of the second memory becomes empty. A third memory of a limited capacity on the chip may pass the commands from the CPU to the first memory in the normal operation or to the second portion of the second memory when the first memory becomes full. The CPU may also pass commands to other peripheral equipment while a ready line is high. When low, the ready line prevents commands from passing to the peripheral equipment while the third memory is full. However, a command may pass from the third memory to the first or second memory to make the ready line high. A counter indicates the number of commands in the first and third memories and the second portion of the second memory. Software occasionally interrogates the counter to update in the software the number of commands in the counter.
摘要翻译： CPU将集成电路芯片上的软件命令引入第一有限容量存储器（例如FIFO）。根据这样的命令来处理来自第二存储器（离线芯片）的第一部分的数据（例如图形）。第二存储器的第二部分（例如FIFO）也可以存储正常地从CPU通过第一存储器的命令。当第一存储器变满时，命令可以从CPU通过第二存储器的第二部分（其可能具有明显大于第一存储器的存储容量），然后通过第一存储器。这些命令可以在该辅助路径中继续流动，直到第二个存储器的第二部分变空。当第一存储器变满时，芯片上的有限容量的第三存储器可以在正常操作中将命令从CPU传送到第一存储器，或者在第一存储器变满时将其传递到第二存储器的第二部分。当准备好的线路高时，CPU也可以将命令传递给其他外围设备。当为低电平时，就绪线路防止命令在第三个存储器已满时传递到外围设备。然而，命令可以从第三存储器传递到第一或第二存储器，以使就绪行高。计数器指示第一和第三存储器和第二存储器的第二部分中的命令的数量。软件偶尔询问计数器，在软件中更新计数器中的命令数。

16. 发明授权

US5640162A Digital-to-analog converter with binary coded inputs to produce a plurality of outputs in the form of thermometer code 失效
标题翻译：具有二进制编码输入的数模转换器，以温度计代码的形式产生多个输出
公开(公告)号：US5640162A
公开(公告)日：1997-06-17
申请号：US317489
申请日：1994-10-04
申请人： Lanny L. Lewyn
发明人： Lanny L. Lewyn
IPC分类号： H03M1/68 , H03M1/80
CPC分类号： H03M1/687 , H03M1/806
摘要： Binary bits of least binary significance are converted to a corresponding analog output. Binary bits of increased binary significance are converted to a first plurality of thermometer outputs. A plurality of switching assemblies, each preferably recursive and preferably formed from a plurality of switches (e.g. transistors), process individual pairs of successive ones of such thermometer outputs. Each stage respectively produces first or second outputs or the analog output for first, second and third relationships between the thermometer outputs in such pair. The analog output has a variable value between the first and second outputs depending upon the value of the least significant binary bits. When the binary value is represented only by the binary bits of least and increased binary significance, the first, second and analog outputs are combined to produce an analog output representative of such binary bits. When the binary value additionally includes binary bits of even greater binary significance, an additional decoder decodes such binary bits to produce a second plurality of thermometer outputs. Second pluralities of switching assemblies, each plurality preferably having a construction corresponding to that of the first plurality, receive individual pairs of the thermometer outputs in the second plurality and produce the first or second outputs or an individual one of the outputs in the first plurality. These thermometer outputs are combined to produce an analog output representative of all of the binary bits. The second pluralities of switching assemblies comprise a number corresponding to the number of thermometer outputs in the second plurality.
摘要翻译：最小二进制有效性的二进制位被转换为相应的模拟输出。具有增加的二进制有效性的二进制位被转换为第一多个温度计输出。多个开关组件各自优选地递归并且优选地由多个开关（例如晶体管）形成，处理这些温度计输出中相继的单独对。每个阶段分别产生第一或第二输出或模拟输出，用于在这种对中的温度计输出之间的第一，第二和第三关系。根据最低有效二进制位的值，模拟输出在第一和第二输出之间具有可变值。当二进制值仅由具有最小和增加的二进制有效性的二进制位表示时，第一，第二和模拟输出被组合以产生表示这种二进制位的模拟输出。当二进制值另外包括二进制值更大的二进制位时，另外的解码器对这样的二进制位解码以产生第二多个温度计输出。第二多个切换组件优选地具有与第一多个结构相对应的结构，在第二多个中接收单独的温度计输出对，并产生第一或第二输出或第一多个输出中的单个输出。这些温度计输出被组合以产生代表所有二进制位的模拟输出。第二多个切换组件包括对应于第二多个温度计输出的数量的数字。

17. 发明授权

US5631593A Adjustable delay line 失效
标题翻译：可调延时线
公开(公告)号：US5631593A
公开(公告)日：1997-05-20
申请号：US670397
申请日：1996-06-25
申请人： Stuart B. Molin
发明人： Stuart B. Molin
IPC分类号： H03H11/26
CPC分类号： H03H11/265
摘要： A plurality of binary signals each having first and second logic levels respectively representing a binary "1" and a binary "0" and each indicating a binary digit of an individual binary significance cumulatively represent an adjustable delay to be provided by a plurality of delay elements. A first particular number of the binary signals of greatest binary significance are decoded to provide, in a thermometer code, a plurality of signals each having first and second amplitudes. The signals in the thermometer code control the operation of individual switches each having first and second operative relationships to provide respectively for a maximum delay or a minimum delay in an associated one of the delay elements. The binary signals of least binary significance are decoded to produce an analog signal variable between the first and second amplitudes. The analog signal is introduced, in a third operative relationship of an individual one of the switches, to the delay element associated with such switch to provide a delay variable between the minimum and maximum values in accordance with the amplitude of the analog signal. The selection of the individual one of the switches is dependent upon the pattern of the binary signals in the thermometer code, this pattern being a binary 10 in a successive pair of the decoded binary signals. The delay elements may be connected in series to provide a cumulative delay constituting the sum of the delays in the different delay elements and corresponding to the delay indicated by the binary signals.
摘要翻译：分别具有第一和第二逻辑电平的多个二进制信号分别表示二进制“1”和二进制“0”，并且每个二进制信号表示单个二进制显式的二进制数字累积地表示可由多个延迟元件提供的可调延迟。解码具有最大二值含义的二进制信号的第一特定数量，以在温度计代码中提供多个具有第一和第二幅度的信号。温度计代码中的信号控制各自具有第一和第二操作关系的各个开关的操作，以分别提供相关联的一个延迟元件中的最大延迟或最小延迟。对二进制有意义的二进制信号进行解码，以产生在第一和第二振幅之间的模拟信号变量。在开关中的单个开关的第三操作关系中引入模拟信号到与这种开关相关联的延迟元件，以根据模拟信号的幅度在最小值和最大值之间提供延迟变量。开关中的单个开关的选择取决于温度计代码中的二进制信号的模式，该模式是连续的解码二进制信号对中的二进制10。延迟元件可以串联连接以提供构成不同延迟元件中的延迟之和并对应于由二进制信号指示的延迟的累积延迟。

18. 发明授权

US5627885A System for, and method of, transmitting and receiving through telephone lines signals representing data 失效
标题翻译：通过电话线发送和接收表示数据的信号的系统和方法
公开(公告)号：US5627885A
公开(公告)日：1997-05-06
申请号：US195628
申请日：1994-02-14
申请人： Eric Paneth , Mordechai Segal , Boaz Rippin , Ehud H. Rokach
发明人： Eric Paneth , Mordechai Segal , Boaz Rippin , Ehud H. Rokach
IPC分类号： H03H21/00 , H04B3/23 , H04L7/04 , H04L7/06 , H04L7/10 , H04L25/00 , H04L25/03 , H04L25/48 , H04M11/00
CPC分类号： H04L25/00 , H04B3/23 , H04L25/03057 , H04L25/03866 , H04L7/043 , H04L7/06 , H04L7/10
摘要： Analog signals representing individual digital values (.+-.1, .+-.3) pass through a telephone line to a receiver. These signals may be first provided in a pseudo random sequence. A linear echo canceller and a first adder eliminate, to an extent, echo signals resulting from second analog signals transmitted on the same telephone line by the receiver. A non-linear echo canceller and a second adder further reduce the echo signals and specifically reduce non-linear components in the echo signals. Adjustable signal delays achieve optimal performance of the linear and non-linear echo cancellers. An equalizer containing four (4) different modules then compensates for signal distortions introduced by the telephone line and minimizes the effect of noise in the telephone line. The equalizer modules are a digital gain control element, a feed forward digital filter and two (2) feedback digital filters. A detector module produces in one of several different ways at the receiver an estimate of the digital data (.+-.1, .+-.3) transmitted at the other end of the telephone line. The detector either extracts the digital information based on peaks in the received (non-equalized) signal or by adding the equalized signals with preset threshold values. A scrambler-descrambler module locally generates a replica of the digital symbols transmitted in analog form at the other end of the telephone line, based on a limited number (e.g. 23) of correctly detected digital values. The scrambler-descrambler module may also operate as a descrambler to recover data scrambled by the transmitter at the other end.
摘要翻译：表示各个数字值（+/- 1，+/- 3）的模拟信号通过电话线路传送到接收器。这些信号可以首先以伪随机序列提供。线性回波消除器和第一加法器在一定程度上消除由接收器在相同电话线上发送的第二模拟信号产生的回波信号。非线性回波消除器和第二加法器进一步减少回波信号并且具体地减少回波信号中的非线性分量。可调节的信号延迟实现了线性和非线性回波消除器的最佳性能。包含四（4）个不同模块的均衡器然后补偿由电话线引入的信号失真，并最大限度地减少电话线路中噪声的影响。均衡器模块是数字增益控制元件，前馈数字滤波器和两（2）个反馈数字滤波器。检测器模块在接收机处以几种不同的方式之一产生在电话线的另一端传输的数字数据（+/- 1，+/- 3）的估计。检测器根据接收（非均衡）信号中的峰值提取数字信息，或通过将均衡信号与预设阈值相加。扰码解扰器模块基于有限数量（例如23个）正确检测的数字值本地生成在电话线的另一端以模拟形式传输的数字符号的副本。加扰器解扰器模块还可以作为解扰器来操作，以恢复另一端由发射机加扰的数据。

19. 发明授权

US5554950A Delay line providing an adjustable delay in response to binary input signals 失效
标题翻译：延迟线提供响应于二进制输入信号的可调延迟
公开(公告)号：US5554950A
公开(公告)日：1996-09-10
申请号：US382677
申请日：1995-02-02
申请人： Stuart B. Molin
发明人： Stuart B. Molin
IPC分类号： H03H11/26
CPC分类号： H03H11/265
摘要： A plurality of binary signals each having first and second logic levels respectively representing a binary "1" and a binary "0" and each indicating a binary digit of an individual binary significance cumulatively represent an adjustable delay to be provided by a plurality of delay elements. A first particular number of the binary signals of greatest binary significance are decoded to provide, in a thermometer code, a plurality of signals each having first and second amplitudes. The signals in the thermometer code control the operation of individual switches each having first and second operative relationships to provide respectively for a maximum delay or a minimum delay in an associated one of the delay elements. The binary signals of least binary significance are decoded to produce an analog signal variable between the first and second amplitudes. The analog signal is introduced, in a third operative relationship of an individual one of the switches, to the delay element associated with such switch to provide a delay variable between the minimum and maximum values in accordance with the amplitude of the analog signal. The selection of the individual one of the switches is dependent upon the pattern of the binary signals in the thermometer code, this pattern being a binary 10 in a successive pair of the decoded binary signals. The delay elements may be connected in series to provide a cumulative delay constituting the sum of the delays in the different delay elements and corresponding to the delay indicated by the binary signals.
摘要翻译：分别具有第一和第二逻辑电平的多个二进制信号分别表示二进制“1”和二进制“0”，并且每个二进制信号表示单个二进制显式的二进制数字累积地表示可由多个延迟元件提供的可调延迟。解码具有最大二值含义的二进制信号的第一特定数量，以在温度计代码中提供多个具有第一和第二幅度的信号。温度计代码中的信号控制各自具有第一和第二操作关系的各个开关的操作，以分别提供相关联的一个延迟元件中的最大延迟或最小延迟。对二进制有意义的二进制信号进行解码，以产生在第一和第二振幅之间的模拟信号变量。在开关中的单个开关的第三操作关系中引入模拟信号到与这种开关相关联的延迟元件，以根据模拟信号的幅度在最小值和最大值之间提供延迟变量。开关中的单个开关的选择取决于温度计代码中的二进制信号的模式，该模式是连续的解码二进制信号对中的二进制10。延迟元件可以串联连接以提供构成不同延迟元件中的延迟之和并对应于由二进制信号指示的延迟的累积延迟。

20. 发明授权

US5541598A Current cell for converting a binary value to an analog value 失效
标题翻译：用于将二进制值转换为模拟值的当前单元格
公开(公告)号：US5541598A
公开(公告)日：1996-07-30
申请号：US333973
申请日：1994-11-03
申请人： Behnam Malek-Khosravi
发明人： Behnam Malek-Khosravi
IPC分类号： H03M1/74 , H03K17/041 , H03K19/017 , H03K19/0175 , H03K19/0948 , H03M1/08 , H03M1/66
CPC分类号： H03K17/04106 , H03M1/0863 , H03M1/742
摘要： A digital value represented by binary signals is converted to a corresponding analog value by three (3) current cells, preferably C-MOS p-type, in a digital-to-analog converter (DAC). The three (3) transistors, preferably disposed on an integrated circuit chip, comprise (a) an input switch transistor receiving a digital input signal at its gate, (b) an output transistor providing an output current at its drain and (c) a current bias transistor. The switch and output transistor sources and the bias transistor drain are common. The output transistor gate is biased by a substantially constant voltage. The bias transistor source receives a supply voltage through a bonding pad on an integrated circuit chip and a bond wire extending from the pad to a pin on the chip package lead frame. At low frequencies (e.g. 100 MHz), the wave shape of the output transistor drain current is flat. At increased frequencies (e.g. 225 MHz), the output current has a spike from a supply voltage spike induced in the bond wire as a result of different magnitudes in the bias transistor current when the switch transistor responds to binary signals.
摘要翻译：由二进制信号表示的数字值在数模转换器（DAC）中被三（3）个当前单元，最好是C-MOS p型转换成相应的模拟值。优选地设置在集成电路芯片上的三（3）个晶体管包括（a）在其栅极处接收数字输入信号的输入开关晶体管，（b）在其漏极处提供输出电流的输出晶体管，以及（c）电流偏置晶体管。开关和输出晶体管源极和偏置晶体管漏极是常见的。输出晶体管栅极被基本恒定的电压偏置。偏置晶体管源通过集成电路芯片上的接合焊盘和从焊盘延伸到芯片封装引线框架上的引脚的接合线接收电源电压。在低频（例如100MHz）下，输出晶体管漏极电流的波形是平坦的。在增加的频率（例如225MHz）下，当开关晶体管响应二进制信号时，由于偏置晶体管电流的不同幅度，输出电流具有从接合线中引起的电源电压尖峰的尖峰。

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