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11. 发明授权

US5111204A Apparatus for converting data between digital and analog values 失效
标题翻译：用于在数字和模拟值之间转换数据的装置
公开(公告)号：US5111204A
公开(公告)日：1992-05-05
申请号：US512757
申请日：1990-07-16
申请人： Henry S. Katzenstein
发明人： Henry S. Katzenstein
IPC分类号： H03M1/06 , H03M1/76
CPC分类号： H03M1/0651 , H03M1/76
摘要： Apparatus converts into an analog value signals representing digital values. Sub-sets of switches are provided, the number of switches in each sub-set being directly related to the digital significance of the switches in such sub-set. The switches in each sub-set may be paired to provide for a conductivity of one switch in each pair. The signals representing individual digital values are introduced to the associated sub-sets to provide for the conductivity of an individual one of the switches in each pair in accordance with the digital value represented by such signals. The switches are connected in a recursive relationship defined by repetitions of a basic block. Each basic block is in turn defined by a pair of basic sub-blocks. A plurality of capacitors are also provided as output members. The capacitors are connected to the recursive relationship of the switches to charge the capacitors through paths defined by the conductive ones of the switches. When the capacitors are conductive, the switches operate to introduce the charge from the capacitors to one of two output lines. For progressive increases in the digital value, a progressive number of the capacitors are connected to a particular one of the output lines, and capacitors previously connected to the particular output line are maintained connected to the output line with such progressive increases in the digital value. The cumulative current through the particular output line is indicative of the analog value.
摘要翻译：设备转换为表示数字值的模拟值信号。提供了一组子交换机，每个子集中的交换机的数量与这种子集中交换机的数字有效性直接相关。每个子集中的开关可以配对以提供每对中的一个开关的导电性。代表各个数字值的信号被引入相关联的子集，以根据由这些信号表示的数字值来提供每对中的每个开关中的一个开关的导电性。开关以基本块的重复定义的递归关系连接。每个基本块又由一对基本子块限定。还提供多个电容器作为输出部件。电容器连接到开关的递归关系，以通过由导通开关限定的路径对电容器充电。当电容器导通时，开关操作以将电荷从电容器引入两条输出线之一。对于数字值的逐渐增加，逐渐数量的电容器连接到特定的输出线，并且先前连接到特定输出线的电容器以数字值的逐渐增加保持连接到输出线。通过特定输出线的累积电流表示模拟值。

12. 发明授权

US4899154A Flash comparator 失效
标题翻译：闪存比较器
公开(公告)号：US4899154A
公开(公告)日：1990-02-06
申请号：US224871
申请日：1988-07-26
申请人： Joseph H. Colles
发明人： Joseph H. Colles
IPC分类号： H03M1/36
CPC分类号： H03M1/365
摘要： Input and reference voltages are respectively applied to the control elements of first and second transistors. This causes a substantially constant current to be divided between the first and second transistors in first time periods. In second time periods alternating with the first periods, the reference voltage is also applied to the control element of the first transistor to produce a current representation of the reference voltage. This causes the first and second transistors respectively to produce in the second periods voltages dependent only upon their relative characteristics. These voltages are introduced in the second periods to first and second capacitances to charge the capacitances when first switches such as transistors are closed. Subsequently in the second periods, the charges in the first and second capacitances are respectively transferred to third and fourth capacitances to charge the third and fourth capacitances. The voltages across the third and fourth capacitances are respectively introduced in the first periods to the third and fourth transistors to control the transistor conductivities. The resultant currents produced by the third and fourth transistors are respectively introduced to the first and second transistors in the first periods to compensate for the differences in the characteristics of the first and second transistors. As a result, the voltage difference at the outputs of the first and second transistors in the first periods respectively represent only the difference between the input and reference voltages.
摘要翻译：输入和参考电压分别施加到第一和第二晶体管的控制元件。这导致在第一时间段内在第一和第二晶体管之间划分基本恒定的电流。在与第一周期交替的第二时间段中，参考电压也被施加到第一晶体管的控制元件以产生参考电压的电流表示。这使得第一和第二晶体管分别在第二周期中产生仅依赖于它们的相对特性的电压。这些电压在第二周期中被引入到第一和第二电容，以在诸如晶体管的第一开关闭合时对电容进行充电。随后在第二周期中，将第一和第二电容中的电荷分别传送到第三和第四电容，以对第三和第四电容充电。第三和第四电容两端的电压分别在第一和第四晶体管中被引入以控制晶体管的电导率。在第一周期中由第三和第四晶体管产生的合成电流分别被引入第一和第二晶体管，以补偿第一和第二晶体管的特性的差异。结果，在第一周期中的第一和第二晶体管的输出处的电压差分别仅表示输入电压和参考电压之间的差。

13. 发明授权

US4812818A Digital-to-analog converter 失效
公开(公告)号：US4812818A
公开(公告)日：1989-03-14
申请号：US18014
申请日：1987-02-24
申请人： Joseph H. Colles
发明人： Joseph H. Colles
IPC分类号： H03M1/74 , H01L27/02 , H03M1/00 , H03M1/66
CPC分类号： H01L27/0207 , H03M1/0648 , H03M1/685
摘要： An integrated circuit chip has circuitry for converting a binary coded value to an analog value. The chip includes first and second matrices each defined by rows and columns. The rows and columns have sources at different positions for producing currents in response to binary signals coding for the binary value. Each row in the first matrix is connected to a row in the second matrix on a reverse-image basis. For example, if each matrix has thirty two (32) rows, rows 1 and 32 in the first matrix are respectively connected to rows 32 and 1 in the second matrix. The rows in the matrices are sequentially selected in a pattern providing particular convergences and divergences of successive paris of such rows in each matrix. Such sequential selection provides progressive convergences and then progressive divergences of the rows in each of the successive pairs in each matrix about the center line as a reference. Such progressive convergences and divergences may occur in at least a pair of successive cycles. When such a selection occurs, the selected rows in each matrix in one cycle are interleaved in such matrix with the selected rows in the other cycle. In this way, compensation may be provided on the chip for second order errors such as result from stresses in the chip.

14. 发明授权

US4733153A Switching system for capacitor charging/discharging 失效
标题翻译：电容充放电开关系统
公开(公告)号：US4733153A
公开(公告)日：1988-03-22
申请号：US69317
申请日：1987-07-02
申请人： Henry S. Katzenstein
发明人： Henry S. Katzenstein
IPC分类号： H03K17/04 , H03K17/06 , H03K17/60 , H03K17/66 , H03K7/06 , H02M7/00 , H03G3/00
CPC分类号： H03K17/603 , H03K17/06 , H03K17/601
摘要： First and second switches such as transistors are connected to a charge storage member such as a capacitance. The capacitance is charged through the first transistor from a positive supply when the transistor becomes conductive. The capacitances is discharged through the second transistor to a reference potential such as ground when the second transistor becomes conductive. The conductivities of the first and second transistors are controlled by pulses from a pulse source such as a transformer. The transformer primary produces a pulse of one polarity upon the occurrence of the leading edge of an input signal and a pulse of an opposite polarity upon the occurrence of the trailing edge of the input signal. Two secondary windings are respectively connected in opposite polarities to the bases of the first and second transistors to provide for the conductivity of only one of the transistors at any one time. The transformers saturate the conductive transistor to prolong on a limited basis the time during which the transistor remains conductive. The other one of the transistors is made instantaneously non-conductive by providing for an instantaneous discharge of the stored base charge between the base and emitter of the transistor. A constant current source is electrically in parallel with the first transistor to sustain the capacitance charge at a high level after the limited period of time in which the first transistor remains conducitive. A low frequency transistor is connected in parallel with the second transistor to sustain the discharge of the capacitance after the limited period of time in which the second transistor remains conductive.

15. 发明授权

US5790110A System and method for generating video in a computer system 失效
公开(公告)号：US5790110A
公开(公告)日：1998-08-04
申请号：US783777
申请日：1997-01-15
申请人： David C. Baker , Daniel P. Mulligan , Eric J. Schell
发明人： David C. Baker , Daniel P. Mulligan , Eric J. Schell
IPC分类号： H04N11/20 , G09G5/00 , G09G5/06 , G09G5/39 , G09G5/393 , G09G5/395 , H04N7/01 , H04N9/64 , H04N11/14 , H04N11/16 , G09G5/02
CPC分类号： H04N9/641 , G09G5/39 , G09G2310/04 , G09G2340/02 , G09G2340/125 , G09G5/06 , G09G5/393 , H04N11/14 , H04N11/16
摘要： A system and method for generating composite video signals in a computer. Digital pixel data may be processed by software to form component video pixel data, which may include luminance and chrominance components. A chrominance look-up table is provided in a display memory and is used for modulation of the chrominance components. The modulated components are then combined to form digital composite video pixel data which may be stored in a frame buffer in the display memory. Video control information is precalculated and stored in the display memory in advance. The digital composite video pixel data and video control information are then recovered from the display memory to produce a formatted stream of video data. The architecture of this system greatly reduces hardware complexity and bandwidth requirements. In addition, the process may be controlled by a media stream controller which is also adapted for audio and graphics processing. This allows the display memory and various other components to be shared by multiple media subsystems.

16. 发明授权

US5768275A Controller for ATM segmentation and reassembly 失效
标题翻译：控制器用于ATM分段和重组
公开(公告)号：US5768275A
公开(公告)日：1998-06-16
申请号：US633955
申请日：1996-04-15
申请人： Bradford C. Lincoln , Douglas M. Brady , David R. Meyer , Warner B. Andrews, Jr.
发明人： Bradford C. Lincoln , Douglas M. Brady , David R. Meyer , Warner B. Andrews, Jr.
IPC分类号： H04Q3/00 , H04L12/56 , H04Q11/04
CPC分类号： H04Q11/0478 , H04L12/5601 , H04L2012/561 , H04L2012/5616 , H04L2012/5649 , H04L2012/5651 , H04L2012/5652 , H04L2012/5679
摘要： A header and a payload in a cell are separated for transfer between a cell interface and a host memory. The header is transferred to a control memory. For transfer to the host memory, the control memory initially provides a host-memory region address and the region length. The payload is recorded in such region. The control memory also provides a second host-memory region address, and length, when the payload length exceeds the payload length in the first address region. For transfer from the host memory to the cell interface, the control memory provides a host memory region address and the header combines the header and the payload and passes the combination to the cell interface. Cells from different sources (i.e. terminals) are scheduled at table positions dependent upon their individual transfer rates. The cells at the scheduled positions are normally transferred in time slots corresponding to such positions. When more than one (1) cell is scheduled at the same position, one (1) cell is transferred on a preset priority basis to the corresponding time slot. The other cells are delayed for transfer subsequently in idle time slots (i.e. no cell normally scheduled) in the same or other priorities. The cell delays for each source are accumulated to a maximum preset value. When the cell delays accumulated for a source exceed the normal time spacing between cells from that source, the source transfers a cell in an idle time slot prior to the normally scheduled time slot to compensate for such delay.
摘要翻译：单元格中的标题和有效负载被分离以在单元接口和主机存储器之间传送。标题被传送到控制存储器。为了传输到主机存储器，控制存储器最初提供主机 - 存储器区域地址和区域长度。有效载荷记录在这样的区域。当有效载荷长度超过第一地址区域中的有效载荷长度时，控制存储器还提供第二主机 - 存储器区域地址和长度。为了从主机存储器传送到单元接口，控制存储器提供主机存储器区域地址，并且报头组合报头和有效载荷，并将组合传递到单元接口。来自不同来源（即终端）的小区根据其个人传送速率被安排在表位置。预定位置处的单元通常在对应于这些位置的时隙中传送。当多于一个（1）小区被调度在相同位置时，一（1）个小区以预设的优先级被传送到相应的时隙。在相同或其他优先级中，其他小区被延迟以在空闲时隙（即，没有小区正常安排）中传送。每个源的单元延迟被累积到最大预设值。当来自源的单元延迟超过来自该源的单元之间的正常时间间隔时，源在正常调度的时隙之前的空闲时隙中传送单元以补偿这种延迟。

17. 发明授权

US5731744A Voltage controlled oscillator 失效
标题翻译：压控振荡器
公开(公告)号：US5731744A
公开(公告)日：1998-03-24
申请号：US654054
申请日：1996-05-28
申请人： Jan C. Diffenderfer
发明人： Jan C. Diffenderfer
IPC分类号： H03B5/32 , H03B5/36 , H03L5/00 , H03J5/14
CPC分类号： H03B5/32 , H03B5/366 , H03L5/00
摘要： An apparatus and a method are provided to obtain oscillations from a crystal at a particular frequency by introducing real and imaginary components of voltage to the crystal. The imaginary component of voltage is different from the real component of voltage by a particular phase angle such as 90.degree.. The voltage introduced to the crystal is processed to produce a first current having characteristics corresponding to such voltage and to produce a second current having characteristics related to the imaginary component of such voltage. The first and second currents are combined to produce a first current corresponding to the real component of the voltage introduced to the crystal. This current is shifted through a phase angle of 90.degree. to produce a second current corresponding to the imaginary component of the voltage introduced to the crystal. The first current is converted to a first voltage which is regulated to provide a particular gain. This regulated voltage corresponds to the real component of the voltage introduced to the crystal. The second current is converted to a second voltage which can be adjusted to adjust the frequency of the oscillations from the oscillator. The second voltage corresponds to the imaginary component of the voltage introduced to the crystal. The first and second voltages are combined to produce the voltage for introduction to the crystal.
摘要翻译：提供了一种装置和方法，以通过将晶体的电压的实部和虚部分量从特定频率的晶体获得振荡。电压的虚分量与90°的特定相位角的实际电压分量不同。处理引入晶体的电压以产生具有对应于这种电压的特性的第一电流，并产生具有与该电压的虚分量相关的特性的第二电流。第一和第二电流被组合以产生对应于引入晶体的电压的实分量的第一电流。该电流通过90°的相位角移动，产生对应于引入晶体的电压的虚分量的第二电流。第一电流被转换成第一电压，其被调节以提供特定的增益。该调节电压对应于引入晶体的电压的实际分量。第二电流被转换成可调节的第二电压以调节振荡器的振荡频率。第二电压对应于引入晶体的电压的虚分量。第一和第二电压被组合以产生用于引入晶体的电压。

18. 发明授权

US5627396A Micromachined relay and method of forming the relay 失效
标题翻译：微加工继电器和形成继电器的方法
公开(公告)号：US5627396A
公开(公告)日：1997-05-06
申请号：US443456
申请日：1995-05-18
申请人： Christopher D. James , Henry S. Katzenstein
发明人： Christopher D. James , Henry S. Katzenstein
IPC分类号： H01L29/84 , H01H1/20 , H01H59/00 , H01L29/82
CPC分类号： H01H59/0009 , H01H1/20 , H01H2001/0084 , H01H2059/0018 , Y10T307/878
摘要： A bridging member extending across a cavity in a semiconductor substrate (e.g. signal crystal silicon) has successive layers--a masking layer, an electrically conductive layer (e.g. polysilicon) and an insulating layer (e.g. SiO.sub.2). A first electrical contact (e.g. gold coated with ruthenium) extends on the insulating layer in a direction perpendicular to the extension of the bridging member across the cavity. A pair of bumps (e.g. gold) are on the insulating layer each between the contact and one of the cavity ends. Initially the bridging member and then the contact and the bumps are formed on the substrate and then the cavity is etched in the substrate through holes in the bridging member. A pair of second electrical contacts (e.g. gold coated with ruthenium) are on the surface of an insulating substrate (e.g. pyrex glass) adjacent the semiconductor substrate. The two substrates are bonded after the contacts are cleaned. The first contact is normally separated from the second contacts because the bumps engage the insulating substrate surface. When a voltage is applied between an electrically conductive layer on the insulating substrate surface and the polysilicon layer, the bridging member is deflected so that the first contact engages the second contacts. Electrical leads extend on the surface of the insulating substrate from the second contacts to bonding pads disposed adjacent a second cavity in the semiconductor substrate. The resultant relays on a wafer may be separated by sawing the semiconductor and insulating substrates at the position of the second cavity in each relay to expose the pads for electrical connections.
摘要翻译：延伸穿过半导体衬底（例如信号晶体硅）中的空腔的桥接构件具有连续的层 - 掩模层，导电层（例如多晶硅）和绝缘层（例如SiO 2）。第一电接触件（例如镀有钌的金）在垂直于桥接构件的延伸方向的绝缘层上延伸穿过空腔。一对凸起（例如金）在绝缘层上分别位于接触件和一个空腔端部之间。最初，桥接构件，然后在衬底上形成接触和凸块，然后通过桥接构件中的孔在衬底中蚀刻空腔。一对第二电触点（例如镀有钌的金）位于与半导体衬底相邻的绝缘衬底（例如耐热玻璃）的表面上。触点清洁后，两个基板接合。第一触点通常与第二触点分离，因为凸块与绝缘基板表面接合。当在绝缘衬底表面上的导电层和多晶硅层之间施加电压时，桥接构件被偏转，使得第一触点接合第二触点。电引线在绝缘基板的表面上从第二触点延伸到邻近半导体衬底中的第二腔的接合焊盘。可以通过在每个继电器中的第二腔的位置处锯切半导体和绝缘基板来分离晶片上的所得继电器，以露出用于电连接的焊盘。

19. 发明授权

US5620933A Micromachined relay and method of forming the relay 失效
标题翻译：微加工继电器和形成继电器的方法
公开(公告)号：US5620933A
公开(公告)日：1997-04-15
申请号：US445139
申请日：1995-05-19
申请人： Christopher D. James , Henry S. Katzenstein
发明人： Christopher D. James , Henry S. Katzenstein
IPC分类号： H01L29/84 , H01H1/20 , H01H59/00 , H01L21/461 , H01L21/465
CPC分类号： H01H59/0009 , H01H1/20 , H01H2001/0084 , H01H2059/0018 , Y10T307/878
摘要： A bridging member extending across a cavity in a semiconductor substrate (e.g. single crystal silicon) has successive layers--a masking layer, an electrically conductive layer (e.g. polysilicon) and an insulating layer (e.g. SiO.sub.2). A first electrical contact (e.g. gold coated with ruthenium) extends on the insulating layer in a direction perpendicular to the extension of the bridging member across the cavity. A pair of bumps (e.g. gold) are on the insulating layer each between the contact and one of the cavity ends. Initially the bridging member and then the contact and the bumps are formed on the substrate and then the cavity is etched in the substrate through holes in the bridging member. A pair of second electrical contacts (e.g. gold coated with ruthenium) are on the surface of an insulating substrate (e.g. pyrex glass) adjacent the semiconductor substrate. The two substrates are bonded after the contacts are cleaned. The first contact is normally separated from the second contacts because the bumps engage the insulating substrate surface. When a voltage is applied between an electrically conductive layer on the insulating substrate surface and the polysilicon layer, the bridging member is deflected so that the first contact engages the second contacts. Electrical leads extend on the surface of the insulating substrate from the second contacts to bonding pads disposed adjacent a second cavity in the semiconductor substrate. The resultant relays on a wafer may be separated by sawing the semiconductor and insulating substrates at the position of the second cavity in each relay to expose the pads for electrical connections.
摘要翻译：延伸穿过半导体衬底（例如单晶硅）中的空腔的桥接构件具有连续的层 - 掩模层，导电层（例如多晶硅）和绝缘层（例如SiO 2）。第一电接触件（例如镀有钌的金）在垂直于桥接构件的延伸方向的绝缘层上延伸穿过空腔。一对凸起（例如金）在绝缘层上分别位于接触件和一个空腔端部之间。最初，桥接构件，然后在衬底上形成接触和凸块，然后通过桥接构件中的孔在衬底中蚀刻空腔。一对第二电触点（例如镀有钌的金）位于与半导体衬底相邻的绝缘衬底（例如耐热玻璃）的表面上。触点清洁后，两个基板接合。第一触点通常与第二触点分离，因为凸块与绝缘基板表面接合。当在绝缘衬底表面上的导电层和多晶硅层之间施加电压时，桥接构件被偏转，使得第一触点接合第二触点。电引线在绝缘基板的表面上从第二触点延伸到邻近半导体衬底中的第二腔的接合焊盘。可以通过在每个继电器中的第二腔的位置处锯切半导体和绝缘基板来分离晶片上的所得继电器，以露出用于电连接的焊盘。

20. 发明授权

US5500892A Echo canceller 失效
标题翻译：回音消除器
公开(公告)号：US5500892A
公开(公告)日：1996-03-19
申请号：US195267
申请日：1994-02-14
申请人： Daniel L. Essig
发明人： Daniel L. Essig
IPC分类号： H03H21/00 , H04B3/23 , H04M11/00
CPC分类号： H04B3/237
摘要： Analog signals representing individual digital values (+3, +1, -1, -3) of data pass through a telephone line to a receiver. These signals may first be provided in a pseudo random sequence. A linear echo canceller and a first adder at the receiver simultaneously eliminate, to some extent, echo signals resulting from second analog signals transmitted through the telephone line by the receiver. A non-linear echo canceller and a second adder further significantly reduce the echo signals and specifically reduce non-linear components in the echo signals. Adjustable signal delays achieve optimal performance of the linear and non-linear echo cancellers. In one inventive embodiment, each echo canceller includes a memory which stores, for each terminal in such echo canceller, data representing (a) the pseudo random sequence and (b) coefficients for adjusting the signals in such sequence. Such data for each terminal in such echo canceller is recorded in the memory for introduction to the next terminal in the memory. For each terminal in such echo canceller, the signals representing the data for the coefficient and the output from the associated adder are processed to determine an adjusted value of such coefficient for storage in the memory and for use in the next cycle of processing. The adjusted coefficient value and the data stored in the memory for such terminal are processed to produce signals for introduction to the associated adder. The signals from the second adder are processed to restore the data transmitted through the telephone line to the receiver.
摘要翻译：表示数据的各个数字值（+3，+1，-1，-3）的模拟信号通过电话线通过接收机。这些信号可以首先以伪随机序列提供。在接收器处，线性回波消除器和第一加法器同时消除由接收器通过电话线传输的第二模拟信号产生的回波信号。非线性回波消除器和第二加法器进一步显着地减少回波信号并且具体地减小回波信号中的非线性分量。可调节的信号延迟实现了线性和非线性回波消除器的最佳性能。在一个发明实施例中，每个回声消除器包括一个存储器，存储对于这种回波消除器中的每个终端，表示（a）伪随机序列的数据和（b）用于以这样的顺序调整信号的系数。这种回波消除器中的每个终端的这样的数据被记录在存储器中以被引入到存储器中的下一个终端。对于这种回波消除器中的每个终端，处理表示系数的数据和来自相关联的加法器的输出的信号，以确定用于在存储器中存储并用于下一个处理周期的这种系数的调整值。处理调整后的系数值和存储在该终端的存储器中的数据，以产生用于引入相关加法器的信号。来自第二加法器的信号被处理以将通过电话线传输的数据恢复到接收器。

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