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11. 发明授权

US5028975A Semiconductor devices and a process for producing the same 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US5028975A
公开(公告)日：1991-07-02
申请号：US527641
申请日：1990-05-23
申请人： Kouichi Nagasawa , Yoshio Sakai , Osamu Minato , Toshiaki Masuhara , Satoshi Meguro
发明人： Kouichi Nagasawa , Yoshio Sakai , Osamu Minato , Toshiaki Masuhara , Satoshi Meguro
IPC分类号： H01L29/78 , H01L21/285 , H01L21/768 , H01L21/8244 , H01L23/485 , H01L23/522 , H01L23/532 , H01L27/11
CPC分类号： H01L27/1112 , H01L21/28525 , H01L21/76895 , H01L23/485 , H01L23/522 , H01L23/53271 , H01L2924/0002 , Y10S257/903
摘要： Disclosed is an MOSIC including a plurality of silicon gate type MOSFET's in which, after polycrystalline silicon wirings are formed simultaneously with polycrystalline silicon gates, the electrodes contacted with the source and drain regions are made of polycrystalline silicon so as to be connected to the polycrystalline silicon wirings, thereby to prevent the shallow pn junctions of the source and drain regions from being destroyed by the contacts and to provide a high degree of integration to one silicon chip.

12. 发明授权

US4901128A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US4901128A
公开(公告)日：1990-02-13
申请号：US934556
申请日：1986-11-24
申请人： Hideo Sunami , Tokuo Kure , Masanobu Miyao , Yoshifumi Kawamoto , Katsuhiro Shimohigashi , Yoshio Sakai , Osamu Minato , Toshiaki Masuhara , Mitsumasa Koyanagi , Shinji Shimizu
发明人： Hideo Sunami , Tokuo Kure , Masanobu Miyao , Yoshifumi Kawamoto , Katsuhiro Shimohigashi , Yoshio Sakai , Osamu Minato , Toshiaki Masuhara , Mitsumasa Koyanagi , Shinji Shimizu
IPC分类号： G11C11/404 , H01L27/108 , H01L29/94
CPC分类号： G11C11/404 , H01L27/10829 , H01L27/10841 , H01L29/945
摘要： A semiconductor memory comprises a capacitor with a data storage portion, and an insulated-gate field-effect transistor. The capacitor is formed by a plate which is made up of the side walls and base of a groove formed in a semiconductor substrate, and by a capacitor electrode formed on the side walls and the base, over an insulation film, and which is connected electrically to the source or drain of the insulated-gate field-effect transistor. Various embodiments are provided for reducing size and preventing leakage between other memory cells, including forming stacked capacitors, forming the transistor over the capacitor, using a silicon-over-insulator arrangement for the transistor, forming a common capacitor plate and providing high impurity layers within the substrate.
摘要翻译：半导体存储器包括具有数据存储部分的电容器和绝缘栅场效应晶体管。该电容器由在半导体衬底中形成的沟槽的侧壁和底部以及形成在侧壁和基底上的电容器电极在绝缘膜上形成并且电连接到绝缘栅场效应晶体管的源极或漏极。提供了各种实施例，用于减小尺寸并防止其它存储单元之间的泄漏，包括形成叠层电容器，在电容器上形成晶体管，使用用于晶体管的绝缘体上硅布置，形成公共电容器板并提供高杂质层底物。

13. 发明授权

US4849801A Semiconductor memory device having increased capacitance for the storing nodes of the memory cells 失效
标题翻译：具有用于存储单元的存储节点的电容增加的半导体存储器件
公开(公告)号：US4849801A
公开(公告)日：1989-07-18
申请号：US113381
申请日：1987-10-27
申请人： Shigeru Honjyo , Osamu Minato , Yoshio Sakai , Toshiaki Yamanaka , Katsuhiro Shimohigashi , Toshiaki Masuhara
发明人： Shigeru Honjyo , Osamu Minato , Yoshio Sakai , Toshiaki Yamanaka , Katsuhiro Shimohigashi , Toshiaki Masuhara
IPC分类号： H01L29/94 , G11C11/41 , H01L21/8244 , H01L27/10 , H01L27/11
CPC分类号： H01L27/1112 , Y10S257/903
摘要： A semiconductor memory device is provided in which an electrode applied with the power supply voltage or the ground voltage is provided on an insulating layer over the drain and/or the gate of the MOS transistors constituting the memory cell of a static memory device, thereby to increasing the capacitance of the storing node of the memory cell. This semiconductor memory device significantly reduces the occurrence of soft errors.
摘要翻译：提供一种半导体存储器件，其中施加有电源电压或接地电压的电极设置在构成静态存储器件的存储单元的MOS晶体管的漏极和/或栅极上的绝缘层上，从而增加存储单元的存储节点的电容。该半导体存储器件显着地减少了软错误的发生。

14. 发明授权

US4492974A DMOS With gate protection diode formed over base region 失效
标题翻译： DMOS在基极区域形成栅极保护二极管
公开(公告)号：US4492974A
公开(公告)日：1985-01-08
申请号：US350589
申请日：1982-02-22
申请人： Isao Yoshida , Takeaki Okabe , Mineo Katsueda , Minoru Nagata , Toshiaki Masuhara , Kazutoshi Ashikawa , Hideaki Kato , Mitsuo Ito , Shigeo Ohtaka , Osamu Minato , Yoshio Sakai
发明人： Isao Yoshida , Takeaki Okabe , Mineo Katsueda , Minoru Nagata , Toshiaki Masuhara , Kazutoshi Ashikawa , Hideaki Kato , Mitsuo Ito , Shigeo Ohtaka , Osamu Minato , Yoshio Sakai
IPC分类号： H01L27/02 , H01L27/04 , H01L27/06 , H01L29/78 , H01L29/861 , H01L29/90 , H02H3/20
CPC分类号： H01L29/7811 , H01L27/0255 , H01L27/0688 , H01L29/7808 , H01L29/861 , H01L2924/0002
摘要： A semiconductor integrated circuit device is provided to include a vertical type MOSFET and a gate protection element for the MOSFET. The vertical type MOSFET is made up of a silicon layer of n-type conductivity formed on an n.sup.+ -type silicon substrate, a base region of p-type conductivity formed in the surface of the silicon layer of n-type conductivity, an n.sup.+ -type source region provided in the base region, and a gate electrode formed on a portion of the base region through a gate insulating film. The silicon substrate serves as the drain. The gate protection element is formed of a polycrystalline silicon layer which is provided on the base region through an insulating film and includes at least one pn junction. By virtue of forming the gate protection element over the base region rather than directly over the substrate, a more stable operation is achieved.
摘要翻译：提供半导体集成电路器件以包括用于MOSFET的垂直型MOSFET和栅极保护元件。垂直型MOSFET由n +型硅衬底上形成的n型导电硅层，n型导电性硅层表面形成的p型导电基极区，n +型硅衬底，设置在基极区域中的源极区，以及通过栅极绝缘膜形成在基极区域的一部分上的栅电极。硅衬底用作漏极。栅极保护元件由多晶硅层形成，该多晶硅层通过绝缘膜设置在基极区上并且包括至少一个pn结。通过在基极区域而不是直接在衬底上形成栅极保护元件，实现更稳定的操作。

15. 发明授权

US4935901A Semiconductor memory with divided bit load and data bus lines 失效
公开(公告)号：US4935901A
公开(公告)日：1990-06-19
申请号：US158259
申请日：1988-02-19
申请人： Toshio Sasaki , Osamu Minato , Shigeru Honjiyo , Koichiro Ishibashi , Toshiaki Masuhara
发明人： Toshio Sasaki , Osamu Minato , Shigeru Honjiyo , Koichiro Ishibashi , Toshiaki Masuhara
IPC分类号： G11C11/419
CPC分类号： G11C11/419
摘要： A static RAM memory is divided into a plurality of mats (12). Word lines (16) in each pair of mats are accessed by an x-decoder (14). Columns or bit lines are accessed by a y-decoder (20) which selectively connect pairs of bit lines (22) to common data bus segments (24). Transistors (60, 62) connect selected bit lines with a load during a write cycle to stabilize those bit lines and memory cells into which data is written. The x-decoders are connected with near word lines (16a) for addressing a near half of each mat and are operatively connected with remote word lines (16b) for addressing word lines in a remote half of each mat. In this manner, each mat is divided into two effective mats. The bit lines of all the effective mats within an actual mat are connected with the same output data bus segment. A pair of sensing amplifiers (32) is provided for each bit of memory which is accessed concurrently, e.g. eight bits, such that the high and low output of each flip-flop memory cell (18) are both amplified. A pair of driving amplifiers (34) further amplify each high and low output before applying them to an output data bus (38).

16. 发明授权

US4616243A Gate protection for a MOSFET 失效
标题翻译： MOSFET的栅极保护
公开(公告)号：US4616243A
公开(公告)日：1986-10-07
申请号：US621682
申请日：1984-06-18
申请人： Osamu Minato , Toshio Sasaki , Toshiaki Masuhara
发明人： Osamu Minato , Toshio Sasaki , Toshiaki Masuhara
IPC分类号： H01L29/78 , H01L27/02 , H01L27/06
CPC分类号： H01L27/0266
摘要： This invention relates to a protection device of a semiconductor device. The present invention can prevent the drop of a gate breakdown voltage due to miniaturization of a device without impeding the high speed performance of the circuit attached thereto. The invention improves the voltage that can be applied to the input terminal of the device by reducing the surface breakdown voltage of a surface breakdown type MOS transistor, which is a principal member of a protection device, and reducing the resistance after the breakdown. This can be accomplished, for example, by increasing the concentration of a region in which the MOS transistor is disposed, by reducing the depth of the region, and so forth.
摘要翻译：本发明涉及半导体装置的保护装置。本发明可以防止由于器件的小型化导致的栅极击穿电压的下降，而不会妨碍附接到其上的电路的高速性能。本发明通过降低作为保护装置的主要部件的表面击穿型MOS晶体管的表面击穿电压并且降低击穿之后的电阻来提高可施加到器件的输入端子的电压。这可以通过例如通过降低区域的深度等来增加其中配置MOS晶体管的区域的浓度来实现。

17. 发明授权

US5172335A Semiconductor memory with divided bit load and data bus lines 失效
标题翻译：半导体存储器采用分割位负载和数据总线
公开(公告)号：US5172335A
公开(公告)日：1992-12-15
申请号：US727314
申请日：1991-07-01
申请人： Toshio Sasaki , Osamu Minato , Shigeru Honjiyo , Koichiro Ishibashi , Toshiaki Masuhara
发明人： Toshio Sasaki , Osamu Minato , Shigeru Honjiyo , Koichiro Ishibashi , Toshiaki Masuhara
IPC分类号： G11C11/419
CPC分类号： G11C11/419
摘要： A static RAM memory is divided into a plurality of mats (12). Word lines (16) in each pair of mats are accessed by an x-decoder (14). Columns or bit lines are accessed by a y-decoder (20) which selectively connect pairs of bit lines (22) to common data bus segments (24). Transistors (60, 62) connect selected bit lines with a load during a write cycle to stabilize those bit lines and memory cells into which data is written. The x-decoders are connected with near word lines (16a) for addressing a near half of each mat and are operatively connected with remote word lines (16b) for addressing word lines in a remote half of each mat. In this manner, each mat is divided into two effective mats. The bit lines of all the effective mats within an actual mat are connected with the same output data bus segment. A pair of sensing amplifiers (32) is provided for each bit of memory which is accessed concurrently, e.g. eight bits, such that the high and low output of each flip-flop memory cell (18) are both amplified. A pair of driving amplifiers (34) further amplify each high and low output before applying them to an output data bus (38).
摘要翻译：静态RAM存储器被分成多个垫（12）。每对垫子中的字线（16）由x解码器（14）访问。列或位线由y解码器（20）访问，y解码器选择性地将成对的位线（22）连接到公共数据总线段（24）。晶体管（60,62）在写入周期期间将选定的位线与负载连接，以稳定写入数据的位线和存储单元。 x解码器与近字线（16a）连接，用于寻址每个垫的近一半，并且与远程字线（16b）可操作地连接，用于寻址每个垫的远程一半中的字线。以这种方式，每个垫子被分成两个有效的垫子。实际的垫内的所有有效垫的位线与相同的输出数据总线段连接。为每个存储器位提供一对感测放大器（32），该位被同时访问。八位，使得每个触发器存储单元（18）的高和低输出都被放大。一对驱动放大器（34）在将它们施加到输出数据总线（38）之前进一步放大每个高和低输出。

18. 发明授权

US4937790A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4937790A
公开(公告)日：1990-06-26
申请号：US227893
申请日：1988-08-03
申请人： Toshio Sasaki , Toshiaki Masuhara , Osamu Minato
发明人： Toshio Sasaki , Toshiaki Masuhara , Osamu Minato
IPC分类号： G11C29/00
CPC分类号： G11C29/76 , G11C29/808
摘要： A semiconductor memory device is disclosed, in which a word line address translation unit, a data line address translation unit, a first spare memory and a second spare memory are provided in addition to a main memory to relieve a defective memory cell in the main memory. Spare word line address signals for selecting a spare word line on the first spare memory are written in the word line address translation unit, spare data line address signals for selecting a spare data line on the second spare memory are written in the data line address translation unit, and each of the word line address translation unit and the data line address translation unit is constructed of an ordinary semiconductor memory of the multi-bit output type.
摘要翻译：公开了一种半导体存储器件，其中除了主存储器之外还提供字线地址转换单元，数据线地址转换单元，第一备用存储器和第二备用存储器，以减轻主存储器中的有缺陷的存储器单元。用于选择第一备用存储器上的备用字线的备用字线地址信号被写入字线地址转换单元中，用于选择第二备用存储器上的备用数据线的备用数据线地址信号被写入数据线地址转换单位，并且字线地址转换单元和数据线地址转换单元中的每一个由多位输出类型的普通半导体存储器构成。

19. 发明授权

US4280065A Tri-state type driver circuit 失效
标题翻译：三态驱动电路
公开(公告)号：US4280065A
公开(公告)日：1981-07-21
申请号：US969269
申请日：1978-12-14
申请人： Osamu Minato , Toshiaki Masuhara , Toshio Sasaki , Masaharu Kubo
发明人： Osamu Minato , Toshiaki Masuhara , Toshio Sasaki , Masaharu Kubo
IPC分类号： H03K19/0175 , H03K5/02 , H03K19/082 , H03K19/094 , H03K19/0944 , H03K19/0948 , H03K3/01 , H03K19/08
CPC分类号： H03K19/09429 , H03K19/0823 , H03K19/09448 , H03K5/023
摘要： This invention relates to a tri-state type driver circuit in which any one of the three possible output signals of "float", "on", or "off" is produced at high speed even when an output terminal is accompanied with a great load. The tri-state type driver circuit comprises an output inverter circuit which employs a bipolar transistor as a load thereof and a MOS-FET as a driver thereof, a first logical circuit which is coupled to an input terminal of the bipolar transistor, which first logical circuit is made up of a C-MOS circuit receiving an external select signal and a C-MOS circuit having an input signal transmitted thereto and whose output can be specified by the external select signal, and a second logical circuit which is coupled to an input terminal of the MOS-FET, which second logical circuit is made up of a C-MOS circuit receiving the external select signal and a C-MOS circuit having the input signal transmitted thereto. The state of the external select signal will determine whether the driver circuit output will be "float" (regardless of the input to the driver circuit) or "on" or "off" (in correspondence with the input to the driver circuit).
摘要翻译：本发明涉及一种三态型驱动电路，其中即使输出端子伴随着大的负载，也可以高速度地产生“浮动”，“接通”或“断开”的三个可能的输出信号中的任何一个。三态型驱动器电路包括采用双极晶体管作为其负载的输出反相器电路和作为其驱动器的MOS-FET，耦合到双极晶体管的输入端的第一逻辑电路，第一逻辑电路由接收外部选择信号的C-MOS电路和具有传输的输入信号的C-MOS电路组成，其输出可由外部选择信号指定，第二逻辑电路耦合到输入端 MOS-FET的端子，该第二逻辑电路由接收外部选择信号的C-MOS电路和传输了该输入信号的C-MOS电路组成。外部选择信号的状态将决定驱动器电路输出是否为“浮动”（不管驱动电路的输入）还是“开”或“关”（与驱动电路的输入相对应）。

20. 发明授权

US4539660A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US4539660A
公开(公告)日：1985-09-03
申请号：US331278
申请日：1981-12-16
申请人： Katsuki Miyauchi , Tetsuichi Kudo , Osamu Minato , Toshiaki Masuhara , Yoshio Uetani
发明人： Katsuki Miyauchi , Tetsuichi Kudo , Osamu Minato , Toshiaki Masuhara , Yoshio Uetani
IPC分类号： H02J7/00 , G06F1/00 , G06F1/26 , G06F12/16 , G11C5/14 , G11C11/413 , H01B5/14 , H01L21/336 , H01L21/8247 , H01L23/495 , H01L25/00 , H01L27/105 , H01L29/788 , H01L29/792 , H01M2/10 , H01M4/58 , H01M10/052 , H01M10/0562 , H01M10/44 , H02J1/00 , H02J7/34 , G11C11/34
CPC分类号： H01M10/0562 , G11C5/141 , H01L23/49593 , H01M2/1066 , H01L2224/49171 , H01L24/49 , H01L2924/00014 , H01L2924/01014 , H01L2924/10253 , H01L2924/14 , H01L2924/19041
摘要： A nonvolatile memory in which at least one power supply element is carried with an integrated circuit chip containing the memory and connected to power supply terminals of the integrated circuit chip having a memory cell array in which a plurality of memory elements or memory circuits are arrayed.
摘要翻译：一种非易失性存储器，其中至少一个电源元件被携带有集成电路芯片，所述集成电路芯片包含所述存储器并且连接到所述集成电路芯片的电源端子，所述集成电路芯片具有其中排列有多个存储器元件或存储器电路的存储单元阵列。

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