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11. 发明申请

US20110147822A1 Semiconductor memory device and method for manufacturing the same 审中-公开
公开(公告)号：US20110147822A1
公开(公告)日：2011-06-23
申请号：US12929894
申请日：2011-02-23
申请人： Kenji Aoyama , Eiji Ito , Masahiro Kiyotoshi , Tadashi Iguchi , Moto Yabuki
发明人： Kenji Aoyama , Eiji Ito , Masahiro Kiyotoshi , Tadashi Iguchi , Moto Yabuki
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L21/764 , H01L29/40114 , H01L29/66825
摘要： A semiconductor memory device has a semiconductor substrate, a plurality of word lines formed at predetermined intervals on the semiconductor substrate, each word line having a gate insulating film, a charge storage layer, a first insulating film, and a controlling gate electrode which are stacked in order, and including a metal oxide layer above the level of the gate insulating film, a second insulating film covering a side of the word line and a surface of the semiconductor substrate between the word lines, and having a film thickness of 15 nm or less, and a third insulating film formed between the word lines adjacent to each other such that a region below the level of the metal oxide layer has a cavity.

12. 发明授权

US5879447A Semiconductor device and its fabricating method 失效
公开(公告)号：US5879447A
公开(公告)日：1999-03-09
申请号：US478765
申请日：1995-06-07
申请人： Takako Okada , Shigeru Kambayashi , Moto Yabuki , Shinji Onga , Yoshitaka Tsunashima , Yuuichi Mikata , Haruo Okano
发明人： Takako Okada , Shigeru Kambayashi , Moto Yabuki , Shinji Onga , Yoshitaka Tsunashima , Yuuichi Mikata , Haruo Okano
IPC分类号： H01L21/02 , H01L21/20 , H01L21/28 , H01L21/329 , H01L21/334 , H01L21/336 , H01L21/822 , H01L21/8249 , H01L27/04 , H01L27/06 , H01L27/12 , H01L29/49 , H01L29/78 , H01L29/786 , C30B19/00
CPC分类号： H01L28/82 , H01L21/2022 , H01L21/28035 , H01L29/6609 , H01L29/66181 , H01L29/66613 , H01L29/66628 , H01L29/66651 , H01L29/66757 , H01L29/66765 , H01L29/78675 , H01L29/78678 , H01L29/49 , H01L29/78654
摘要： A single crystal and a polycrystal having an excellent crystal quality and providing a highly reliable semiconductor device are formed by solid phase growth at low temperatures. An amorphous thin film is deposited on a substrate such that an average inter-atomic distance of main constituent element of the amorphous thin film is 1.02 times or more of an average inter-atomic distance of the elements in single crystal, and crystallization energy is applied to the amorphous thin film to perform solid phase growth to thereby form a single crystal. In another embodiment of the present invention, an amorphous semiconductor thin film is formed on a substrate or an insulating film such that an average inter-atomic distance distribution of main constituent element of the film substantially coincides with an average inter-atomic distance distribution of the element in a single crystal, and crystallization energy is applied to the amorphous semiconductor thin film to cause solid phase growth to thereby form a single crystalline semiconductor thin film.

13. 发明授权

US5582640A Semiconductor device and its fabricating method 失效
公开(公告)号：US5582640A
公开(公告)日：1996-12-10
申请号：US56443
申请日：1993-04-30
申请人： Takako Okada , Shigeru Kambayashi , Moto Yabuki , Shinji Onga , Yoshitaka Tsunashima , Yuuichi Mikata , Haruo Okano
发明人： Takako Okada , Shigeru Kambayashi , Moto Yabuki , Shinji Onga , Yoshitaka Tsunashima , Yuuichi Mikata , Haruo Okano
IPC分类号： H01L21/02 , H01L21/20 , H01L21/28 , H01L21/329 , H01L21/334 , H01L21/336 , H01L21/822 , H01L21/8249 , H01L27/04 , H01L27/06 , H01L27/12 , H01L29/49 , H01L29/78 , H01L29/786
CPC分类号： H01L28/82 , H01L21/2022 , H01L21/28035 , H01L29/6609 , H01L29/66181 , H01L29/66613 , H01L29/66628 , H01L29/66651 , H01L29/66757 , H01L29/66765 , H01L29/78675 , H01L29/78678 , H01L29/49 , H01L29/78654
摘要： A single crystal and a polycrystal having an excellent crystal quality and providing a highly reliable semiconductor device are formed by solid phase growth at low temperatures. An amorphous thin film is deposited on a substrate such that an average inter-atomic distance of main constituent element of the amorphous thin film is 1.02 times or more of an average inter-atomic distance of the elements in single crystal, and crystallization energy is applied to the amorphous thin film to perform solid phase growth to thereby form a single crystal. In another embodiment of the present invention, an amorphous semiconductor thin film is formed on a substrate or an insulating film such that an average inter-atomic distance distribution of main constituent element of the film substantially coincides with an average inter-atomic distance distribution of the element in a single crystal, and crystallization energy is applied to the amorphous semiconductor thin film to cause solid phase growth to thereby form a single crystalline semiconductor thin film.

14. 发明申请

US20090212352A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20090212352A1
公开(公告)日：2009-08-27
申请号：US12391953
申请日：2009-02-24
申请人： Kenji AOYAMA , Eiji Ito , Masahiro Kiyotoshi , Tadashi Iguchi , Moto Yabuki
发明人： Kenji AOYAMA , Eiji Ito , Masahiro Kiyotoshi , Tadashi Iguchi , Moto Yabuki
IPC分类号： H01L29/792 , H01L21/28 , H01L29/788
CPC分类号： H01L27/11521 , H01L21/28273 , H01L21/764 , H01L29/66825
摘要： A semiconductor memory device has a semiconductor substrate, a plurality of word lines formed at predetermined intervals on the semiconductor substrate, each word line having a gate insulating film, a charge storage layer, a first insulating film, and a controlling gate electrode which are stacked in order, and including a metal oxide layer above the level of the gate insulating film, a second insulating film covering a side of the word line and a surface of the semiconductor substrate between the word lines, and having a film thickness of 15 nm or less, and a third insulating film formed between the word lines adjacent to each other such that a region below the level of the metal oxide layer has a cavity.
摘要翻译：半导体存储器件具有半导体衬底，在半导体衬底上以预定间隔形成的多个字线，每个字线具有栅极绝缘膜，电荷存储层，第一绝缘膜和控制栅电极，它们被堆叠并且包括位于栅极绝缘膜的高度之上的金属氧化物层，覆盖字线的一侧的第二绝缘膜和字线之间的半导体衬底的表面，并且具有15nm的膜厚度或并且形成在彼此相邻的字线之间的第三绝缘膜，使得低于金属氧化物层的电平的区域具有空腔。

15. 发明申请

US20050127513A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20050127513A1
公开(公告)日：2005-06-16
申请号：US11042176
申请日：2005-01-26
申请人： Moto Yabuki
发明人： Moto Yabuki
IPC分类号： H01L27/105 , H01L21/02 , H01L21/20 , H01L21/768 , H01L21/8246 , H01L23/48 , H01L27/115
CPC分类号： H01L27/11502 , H01L21/76838 , H01L27/11507 , H01L28/40 , H01L28/82
摘要： Disclosed is a semiconductor device comprising an underlying film, a first electrode formed on the underlying film, a first dielectric film formed on the first electrode, a second electrode formed on the first dielectric film, and a first interconnect including a first conductive portion extending in a stack direction of the first electrode, the first dielectric film and the second electrode, a side surface of the first conductive portion being in contact with one of the first electrode and the second electrode.
摘要翻译：公开了一种半导体器件，包括下面的膜，形成在下面的膜上的第一电极，形成在第一电极上的第一电介质膜，形成在第一电介质膜上的第二电极和第一互连件，第一互连件包括第一导电部分，第一电极的堆叠方向，第一电介质膜和第二电极，第一导电部分的侧表面与第一电极和第二电极中的一个接触。

16. 发明授权

US06614642B1 Capacitor over plug structure 有权
标题翻译：电容器插头结构
公开(公告)号：US06614642B1
公开(公告)日：2003-09-02
申请号：US10065122
申请日：2002-09-19
申请人： Bum-ki Moon , Moto Yabuki , Gerhard Beitel , Nicolas Nagel , Andreas Hilliger , Takamichi Tsuchiya
发明人： Bum-ki Moon , Moto Yabuki , Gerhard Beitel , Nicolas Nagel , Andreas Hilliger , Takamichi Tsuchiya
IPC分类号： H01G4228
CPC分类号： H01L28/75 , H01L21/28568 , H01L28/60 , H01L28/90
摘要： A capacitor over plug (COP) structure is disclosed. The COP avoids the step which is created in conventional COP structures, which adversely impacts the properties of the capacitor. In one embodiment, the step is avoided by providing a plug having upper and lower portions. The upper portion, which is coupled to the bottom electrode of the capacitor, has substantially the same surface area as the bottom electrode. A barrier layer can be provided between the plug and bottom electrode to avoid oxidation of the plug material.
摘要翻译：公开了一种电容器插头（COP）结构。 COP避免了常规COP结构中产生的步骤，这对电容器的性能产生不利影响。在一个实施例中，通过提供具有上部和下部的插塞来避免该步骤。耦合到电容器的底部电极的上部具有与底部电极基本相同的表面积。可以在塞子和底部电极之间提供阻挡层以避免塞子材料的氧化。

17. 发明授权

US07960779B2 Nonvolatile semiconductor memory and manufacturing method thereof 有权
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US07960779B2
公开(公告)日：2011-06-14
申请号：US12393186
申请日：2009-02-26
申请人： Takayuki Toba , Takayuki Okamura , Moto Yabuki
发明人： Takayuki Toba , Takayuki Okamura , Moto Yabuki
IPC分类号： H01L29/792 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/11573
摘要： A nonvolatile semiconductor memory of an aspect of the invention includes memory cells in the memory cell forming area, and select gate transistors in the select gate forming area. Each memory cell has two first diffusion layers formed in a semiconductor substrate, a first gate insulating film formed on the semiconductor substrate, a charge storage layer formed on the first gate insulating film, a first intermediate insulating film formed on the charge storage layer and a first gate electrode formed on the first intermediate insulating film. Each select gate transistor has two second diffusion layers formed in the semiconductor substrate, a second gate insulating film formed on the semiconductor substrate, a second intermediate insulating film formed in direct contact with the second gate insulating film and having the same structure as the first intermediate insulating film, and a second gate electrode formed on the second intermediate insulating film.
摘要翻译：本发明的一个方面的非易失性半导体存储器包括存储单元形成区域中的存储单元，并且在选择栅极形成区域中选择栅极晶体管。每个存储单元具有形成在半导体衬底中的两个第一扩散层，形成在半导体衬底上的第一栅极绝缘膜，形成在第一栅极绝缘膜上的电荷存储层，形成在电荷存储层上的第一中间绝缘膜和第一栅电极，形成在第一中间绝缘膜上。每个选择晶体管具有形成在半导体衬底中的两个第二扩散层，形成在半导体衬底上的第二栅极绝缘膜，与第二栅极绝缘膜直接接触形成并具有与第一中间层相同结构的第二中间绝缘膜绝缘膜和形成在第二中间绝缘膜上的第二栅电极。

18. 发明授权

US5854133A Method for manufacturing a semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US5854133A
公开(公告)日：1998-12-29
申请号：US698200
申请日：1996-08-15
申请人： Takayo Hachiya , Moto Yabuki , Hiroyuki Kamijou
发明人： Takayo Hachiya , Moto Yabuki , Hiroyuki Kamijou
IPC分类号： H01L21/302 , H01L21/304 , H01L21/3065 , H01L21/3105 , H01L21/311 , H01L21/463
CPC分类号： H01L21/31116 , H01L21/304 , H01L21/31053
摘要： According to the present invention, to flatten the surface of a silicon substrate by polishing an element isolating buried insulation film by chemical mechanical polishing, a polysilicon film is formed on the top surface of a projection of a silicon substrate. After that, a buried insulation film is formed all over the silicon substrate along the irregularities thereof. A carbon film is formed on the surface of a recess of the buried insulation film. Using the carbon film as a stopper, the buried insulation film is polished by the chemical mechanical polishing to ease the irregularities of the surface of the polished insulation film. Then the carbon film is removed and, using the polysilicon film as a stopper, the buried insulation film is polished by the chemical mechanical polishing to flatten the surface of the polished insulation film. Thus, the flatness of the buried insulation film can easily be controlled, and the surface of the silicon substrate can always be flattened satisfactorily.
摘要翻译：根据本发明，通过化学机械研磨抛光元件隔离掩埋绝缘膜来使硅衬底的表面平坦化，在硅衬底的突起的顶表面上形成多晶硅膜。之后，沿着其不规则形状在硅衬底上形成掩埋绝缘膜。在掩埋绝缘膜的凹部的表面上形成碳膜。使用碳膜作为止动器，通过化学机械抛光对掩埋绝缘膜进行抛光，以减轻抛光绝缘膜的表面的不规则性。然后除去碳膜，使用多晶硅膜作为止动器，通过化学机械抛光对掩埋绝缘膜进行抛光，使抛光绝缘膜的表面平坦化。因此，可以容易地控制埋入绝缘膜的平坦度，并且能够令人满意地使硅衬底的表面平坦化。

19. 发明授权

US07915156B2 Semiconductor memory device and method for manufacturing the same 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US07915156B2
公开(公告)日：2011-03-29
申请号：US12391953
申请日：2009-02-24
申请人： Kenji Aoyama , Eiji Ito , Masahiro Kiyotoshi , Tadashi Iguchi , Moto Yabuki
发明人： Kenji Aoyama , Eiji Ito , Masahiro Kiyotoshi , Tadashi Iguchi , Moto Yabuki
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L21/28273 , H01L21/764 , H01L29/66825
摘要： A semiconductor memory device has a semiconductor substrate, a plurality of word lines formed at predetermined intervals on the semiconductor substrate, each word line having a gate insulating film, a charge storage layer, a first insulating film, and a controlling gate electrode which are stacked in order, and including a metal oxide layer above the level of the gate insulating film, a second insulating film covering a side of the word line and a surface of the semiconductor substrate between the word lines, and having a film thickness of 15 nm or less, and a third insulating film formed between the word lines adjacent to each other such that a region below the level of the metal oxide layer has a cavity.
摘要翻译：半导体存储器件具有半导体衬底，在半导体衬底上以预定间隔形成的多个字线，每个字线具有栅极绝缘膜，电荷存储层，第一绝缘膜和控制栅电极，它们被堆叠并且包括位于栅极绝缘膜的高度之上的金属氧化物层，覆盖字线的一侧的第二绝缘膜和字线之间的半导体衬底的表面，并且具有15nm的膜厚度或并且形成在彼此相邻的字线之间的第三绝缘膜，使得低于金属氧化物层的电平的区域具有空腔。

20. 发明申请

US20090218607A1 NONVOLATILE SEMICONDUCTOR MEMORY AND MANUFACTURING METHOD THEREOF 有权
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US20090218607A1
公开(公告)日：2009-09-03
申请号：US12393186
申请日：2009-02-26
申请人： Takayuki Toba , Takayuki Okamura , Moto Yabuki
发明人： Takayuki Toba , Takayuki Okamura , Moto Yabuki
IPC分类号： H01L29/792 , H01L29/00 , H01L21/336
CPC分类号： H01L27/11573
摘要： A nonvolatile semiconductor memory of an aspect of the invention includes memory cells in the memory cell forming area, and select gate transistors in the select gate forming area. Each memory cell has two first diffusion layers formed in a semiconductor substrate, a first gate insulating film formed on the semiconductor substrate, a charge storage layer formed on the first gate insulating film, a first intermediate insulating film formed on the charge storage layer and a first gate electrode formed on the first intermediate insulating film. Each select gate transistor has two second diffusion layers formed in the semiconductor substrate, a second gate insulating film formed on the semiconductor substrate, a second intermediate insulating film formed in direct contact with the second gate insulating film and having the same structure as the first intermediate insulating film, and a second gate electrode formed on the second intermediate insulating film.
摘要翻译：本发明的一个方面的非易失性半导体存储器包括存储单元形成区域中的存储单元，并且在选择栅极形成区域中选择栅极晶体管。每个存储单元具有形成在半导体衬底中的两个第一扩散层，形成在半导体衬底上的第一栅极绝缘膜，形成在第一栅极绝缘膜上的电荷存储层，形成在电荷存储层上的第一中间绝缘膜和第一栅电极，形成在第一中间绝缘膜上。每个选择晶体管具有形成在半导体衬底中的两个第二扩散层，形成在半导体衬底上的第二栅极绝缘膜，与第二栅极绝缘膜直接接触形成并具有与第一中间层相同结构的第二中间绝缘膜绝缘膜和形成在第二中间绝缘膜上的第二栅电极。

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