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1. 发明授权

US08664631B2 Nonvolatile memory device 失效
标题翻译：非易失性存储器件
公开(公告)号：US08664631B2
公开(公告)日：2014-03-04
申请号：US13236713
申请日：2011-09-20
申请人： Jun Hirota , Yoko Iwakaji , Moto Yabuki
发明人： Jun Hirota , Yoko Iwakaji , Moto Yabuki
IPC分类号： H01L45/00
CPC分类号： H01L45/04 , H01L27/2409 , H01L27/2481 , H01L45/1233 , H01L45/145 , H01L45/1675
摘要： According to one embodiment, a nonvolatile memory device includes a word line interconnect layer, a bit line interconnect layer, a pillar, and charge bearing members. The word line interconnect layer includes a plurality of word lines extending in a first direction. The bit line interconnect layer includes a plurality of bit lines extending in a second direction that intersects the first direction. The pillar is disposed between each of the word lines and each of the bit lines. The charge bearing members contain a negative fixed charge, and provided on side faces of the pillars. The pillars includes a diode film provided with a p-type layer and an n-type layer and a variable resistance film stacked on the diode film. The charge bearing member is disposed on side faces of the p-type layer, and is not disposed on side faces of the n-type layer.
摘要翻译：根据一个实施例，非易失性存储器件包括字线互连层，位线互连层，柱和电荷承载部件。字线互连层包括沿第一方向延伸的多个字线。位线互连层包括沿与第一方向相交的第二方向延伸的多个位线。支柱设置在每个字线和每个位线之间。电荷承载部件包含负的固定电荷，并且设置在支柱的侧面上。支柱包括二极管膜，该二极管膜设置有层叠在二极管膜上的p型层和n型层以及可变电阻膜。电荷承载部件配置在p型层的侧面，不配置在n型层的侧面。

2. 发明申请

US20130077461A1 STORAGE DEVICE 审中-公开
标题翻译：储存设备
公开(公告)号：US20130077461A1
公开(公告)日：2013-03-28
申请号：US13423755
申请日：2012-03-19
申请人： Akihiro Koga , Yasushi Tomizawa , Hideo Shinomiya , Moto Yabuki , Jun Hirota , Yoshihisa Iwata , Masayuki Ichige , Kikuko Sugimae , Junya Matsunami
发明人： Akihiro Koga , Yasushi Tomizawa , Hideo Shinomiya , Moto Yabuki , Jun Hirota , Yoshihisa Iwata , Masayuki Ichige , Kikuko Sugimae , Junya Matsunami
IPC分类号： G11B9/00
CPC分类号： G11B9/02 , G11B9/1418 , G11B9/1436
摘要： A storage device includes a recording medium, a probe, a substrate, and a processing unit. The recording medium stores a signal. The probe reads or writes the signal to/from the recording medium. The substrate is provided with the probe via a conductive anchor interposed therebetween and a first connection terminal connected to the probe. The processing unit is provided on the substrate and has a second connection terminal. The second connection terminal is connected to the first connection terminal.
摘要翻译：存储装置包括记录介质，探针，基板和处理单元。记录介质存储信号。探头将信号读取或写入记录介质。基板经由插入其间的导电锚固体和连接到探针的第一连接端子设置有探针。处理单元设置在基板上，并具有第二连接端子。第二连接端子连接到第一连接端子。

3. 发明申请

US20110193049A1 MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME 失效
标题翻译：存储器件及其制造方法
公开(公告)号：US20110193049A1
公开(公告)日：2011-08-11
申请号：US12844374
申请日：2010-07-27
申请人： Yoko IWAKAJI , Jun Hirota , Kyoichi Suguro , Moto Yabuki
发明人： Yoko IWAKAJI , Jun Hirota , Kyoichi Suguro , Moto Yabuki
IPC分类号： H01L45/00 , H01L21/02
CPC分类号： H01L27/1021 , G11C13/0007 , G11C2213/71 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/16 , H01L45/1675
摘要： According to one embodiment, a method for manufacturing a memory device is disclosed. The method includes forming a silicon diode. At least an upper portion of the silicon diode is made of a semiconductor material containing silicon and doped with impurity. The method includes forming a metal layer made of a metal on the silicon diode. The method includes forming a metal nitride layer made of a nitride of the metal on the metal layer. The method includes forming a resistance change film. In addition, the method includes reacting the metal layer with the silicon diode and the metal nitride layer by heat treatment to form an electrode film containing the metal, silicon, and nitrogen.
摘要翻译：根据一个实施例，公开了一种用于制造存储器件的方法。该方法包括形成硅二极管。硅二极管的至少上部由含有硅并掺杂杂质的半导体材料制成。该方法包括在硅二极管上形成由金属制成的金属层。该方法包括在金属层上形成由金属的氮化物制成的金属氮化物层。该方法包括形成电阻变化膜。此外，该方法包括通过热处理使金属层与硅二极管和金属氮化物层反应，以形成含有金属，硅和氮的电极膜。

4. 发明授权

US07960779B2 Nonvolatile semiconductor memory and manufacturing method thereof 有权
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US07960779B2
公开(公告)日：2011-06-14
申请号：US12393186
申请日：2009-02-26
申请人： Takayuki Toba , Takayuki Okamura , Moto Yabuki
发明人： Takayuki Toba , Takayuki Okamura , Moto Yabuki
IPC分类号： H01L29/792 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/11573
摘要： A nonvolatile semiconductor memory of an aspect of the invention includes memory cells in the memory cell forming area, and select gate transistors in the select gate forming area. Each memory cell has two first diffusion layers formed in a semiconductor substrate, a first gate insulating film formed on the semiconductor substrate, a charge storage layer formed on the first gate insulating film, a first intermediate insulating film formed on the charge storage layer and a first gate electrode formed on the first intermediate insulating film. Each select gate transistor has two second diffusion layers formed in the semiconductor substrate, a second gate insulating film formed on the semiconductor substrate, a second intermediate insulating film formed in direct contact with the second gate insulating film and having the same structure as the first intermediate insulating film, and a second gate electrode formed on the second intermediate insulating film.
摘要翻译：本发明的一个方面的非易失性半导体存储器包括存储单元形成区域中的存储单元，并且在选择栅极形成区域中选择栅极晶体管。每个存储单元具有形成在半导体衬底中的两个第一扩散层，形成在半导体衬底上的第一栅极绝缘膜，形成在第一栅极绝缘膜上的电荷存储层，形成在电荷存储层上的第一中间绝缘膜和第一栅电极，形成在第一中间绝缘膜上。每个选择晶体管具有形成在半导体衬底中的两个第二扩散层，形成在半导体衬底上的第二栅极绝缘膜，与第二栅极绝缘膜直接接触形成并具有与第一中间层相同结构的第二中间绝缘膜绝缘膜和形成在第二中间绝缘膜上的第二栅电极。

5. 发明授权

US5854133A Method for manufacturing a semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US5854133A
公开(公告)日：1998-12-29
申请号：US698200
申请日：1996-08-15
申请人： Takayo Hachiya , Moto Yabuki , Hiroyuki Kamijou
发明人： Takayo Hachiya , Moto Yabuki , Hiroyuki Kamijou
IPC分类号： H01L21/302 , H01L21/304 , H01L21/3065 , H01L21/3105 , H01L21/311 , H01L21/463
CPC分类号： H01L21/31116 , H01L21/304 , H01L21/31053
摘要： According to the present invention, to flatten the surface of a silicon substrate by polishing an element isolating buried insulation film by chemical mechanical polishing, a polysilicon film is formed on the top surface of a projection of a silicon substrate. After that, a buried insulation film is formed all over the silicon substrate along the irregularities thereof. A carbon film is formed on the surface of a recess of the buried insulation film. Using the carbon film as a stopper, the buried insulation film is polished by the chemical mechanical polishing to ease the irregularities of the surface of the polished insulation film. Then the carbon film is removed and, using the polysilicon film as a stopper, the buried insulation film is polished by the chemical mechanical polishing to flatten the surface of the polished insulation film. Thus, the flatness of the buried insulation film can easily be controlled, and the surface of the silicon substrate can always be flattened satisfactorily.
摘要翻译：根据本发明，通过化学机械研磨抛光元件隔离掩埋绝缘膜来使硅衬底的表面平坦化，在硅衬底的突起的顶表面上形成多晶硅膜。之后，沿着其不规则形状在硅衬底上形成掩埋绝缘膜。在掩埋绝缘膜的凹部的表面上形成碳膜。使用碳膜作为止动器，通过化学机械抛光对掩埋绝缘膜进行抛光，以减轻抛光绝缘膜的表面的不规则性。然后除去碳膜，使用多晶硅膜作为止动器，通过化学机械抛光对掩埋绝缘膜进行抛光，使抛光绝缘膜的表面平坦化。因此，可以容易地控制埋入绝缘膜的平坦度，并且能够令人满意地使硅衬底的表面平坦化。

6. 发明授权

US08436331B2 Memory device and method for manufacturing same 失效
标题翻译：存储器件及其制造方法
公开(公告)号：US08436331B2
公开(公告)日：2013-05-07
申请号：US12844374
申请日：2010-07-27
申请人： Yoko Iwakaji , Jun Hirota , Kyoichi Suguro , Moto Yabuki
发明人： Yoko Iwakaji , Jun Hirota , Kyoichi Suguro , Moto Yabuki
IPC分类号： H01L21/02
CPC分类号： H01L27/1021 , G11C13/0007 , G11C2213/71 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/16 , H01L45/1675
摘要： According to one embodiment, a method for manufacturing a memory device is disclosed. The method includes forming a silicon diode. At least an upper portion of the silicon diode is made of a semiconductor material containing silicon and doped with impurity. The method includes forming a metal layer made of a metal on the silicon diode. The method includes forming a metal nitride layer made of a nitride of the metal on the metal layer. The method includes forming a resistance change film. In addition, the method includes reacting the metal layer with the silicon diode and the metal nitride layer by heat treatment to form an electrode film containing the metal, silicon, and nitrogen.
摘要翻译：根据一个实施例，公开了一种用于制造存储器件的方法。该方法包括形成硅二极管。至少硅二极管的上部由含有硅并掺杂杂质的半导体材料制成。该方法包括在硅二极管上形成由金属制成的金属层。该方法包括在金属层上形成由金属的氮化物制成的金属氮化物层。该方法包括形成电阻变化膜。此外，该方法包括通过热处理使金属层与硅二极管和金属氮化物层反应，以形成含有金属，硅和氮的电极膜。

7. 发明申请

US20110233506A1 NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME 审中-公开
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20110233506A1
公开(公告)日：2011-09-29
申请号：US12873604
申请日：2010-09-01
申请人： Yoko IWAKAJI , Jun HIROTA , Moto YABUKI
发明人： Yoko IWAKAJI , Jun HIROTA , Moto YABUKI
IPC分类号： H01L45/00 , H01L21/02
CPC分类号： G11C13/0002 , G11C13/0069 , G11C13/0097 , G11C2213/71 , G11C2213/72 , H01L27/1021 , H01L27/2409 , H01L27/2481 , H01L29/868 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1675
摘要： According to one embodiment, a nonvolatile memory device includes a first electrode, a second electrode, a resistance change portion and a select element. The resistance change portion is provided between the first electrode and the second electrode and configured to transition between a first resistance state and a second resistance state. The select element is provided between the resistance change portion and the first electrode and has a p-layer including a p-type semiconductor, an i-layer including an intrinsic semiconductor, and an n-layer including an n-type semiconductor. The select element contains an impurity having a smaller bandgap energy than the intrinsic semiconductor, and a concentration peak of the impurity in the i-layer is placed in a center portion of layer thickness of the i-layer.
摘要翻译：根据一个实施例，非易失性存储器件包括第一电极，第二电极，电阻变化部分和选择元件。电阻变化部分设置在第一电极和第二电极之间并且被配置为在第一电阻状态和第二电阻状态之间转变。选择元件设置在电阻变化部分和第一电极之间，并且具有包括p型半导体的p层，包括本征半导体的i层和包括n型半导体的n层。选择元件含有具有比本征半导体更小的带隙能量的杂质，并且将i层中的杂质的浓度峰值放置在i层的层厚度的中心部分。

8. 发明授权

US06906908B1 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06906908B1
公开(公告)日：2005-06-14
申请号：US10849111
申请日：2004-05-20
申请人： Moto Yabuki , Andreas Hilliger
发明人： Moto Yabuki , Andreas Hilliger
IPC分类号： H01L21/02 , H01L21/285 , H01L21/768 , H01L21/8246 , H01L27/115 , H01G4/20
CPC分类号： H01L27/11502 , H01L21/28568 , H01L21/76895 , H01L27/11507 , H01L28/57 , H01L28/75
摘要： Disclosed is a semiconductor device comprising a semiconductor substrate, a capacitor provided above the semiconductor substrate, an insulation region which covers the capacitor and has a first hole and a second hole, the first hole being provided apart from the capacitor and extending in a vertical direction with respect to a main surface of the semiconductor substrate, the second hole reaching an electrode of the capacitor, extending in the vertical direction with respect to the main surface of the semiconductor substrate and being shallower than the first hole, a tungsten plug provided in the first hole, a first oxygen barrier film provided between the tungsten plug and a side wall of the first hole, and a conductive plug provided in the second hole and connected to the electrode of the capacitor.
摘要翻译：公开了一种半导体器件，包括半导体衬底，设置在半导体衬底上方的电容器，覆盖电容器并具有第一孔和第二孔的绝缘区域，第一孔与电容器分开设置并沿垂直方向延伸相对于半导体基板的主表面，第二孔到达电容器的电极，相对于半导体基板的主表面在垂直方向上延伸并且比第一孔浅;设置在第一孔中的钨丝塞第一孔，设置在钨塞和第一孔的侧壁之间的第一氧阻隔膜，以及设置在第二孔中并连接到电容器的电极的导电栓。

9. 发明申请

US20110147822A1 Semiconductor memory device and method for manufacturing the same 审中-公开
公开(公告)号：US20110147822A1
公开(公告)日：2011-06-23
申请号：US12929894
申请日：2011-02-23
申请人： Kenji Aoyama , Eiji Ito , Masahiro Kiyotoshi , Tadashi Iguchi , Moto Yabuki
发明人： Kenji Aoyama , Eiji Ito , Masahiro Kiyotoshi , Tadashi Iguchi , Moto Yabuki
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L21/764 , H01L29/40114 , H01L29/66825
摘要： A semiconductor memory device has a semiconductor substrate, a plurality of word lines formed at predetermined intervals on the semiconductor substrate, each word line having a gate insulating film, a charge storage layer, a first insulating film, and a controlling gate electrode which are stacked in order, and including a metal oxide layer above the level of the gate insulating film, a second insulating film covering a side of the word line and a surface of the semiconductor substrate between the word lines, and having a film thickness of 15 nm or less, and a third insulating film formed between the word lines adjacent to each other such that a region below the level of the metal oxide layer has a cavity.

10. 发明授权

US5879447A Semiconductor device and its fabricating method 失效
公开(公告)号：US5879447A
公开(公告)日：1999-03-09
申请号：US478765
申请日：1995-06-07
申请人： Takako Okada , Shigeru Kambayashi , Moto Yabuki , Shinji Onga , Yoshitaka Tsunashima , Yuuichi Mikata , Haruo Okano
发明人： Takako Okada , Shigeru Kambayashi , Moto Yabuki , Shinji Onga , Yoshitaka Tsunashima , Yuuichi Mikata , Haruo Okano
IPC分类号： H01L21/02 , H01L21/20 , H01L21/28 , H01L21/329 , H01L21/334 , H01L21/336 , H01L21/822 , H01L21/8249 , H01L27/04 , H01L27/06 , H01L27/12 , H01L29/49 , H01L29/78 , H01L29/786 , C30B19/00
CPC分类号： H01L28/82 , H01L21/2022 , H01L21/28035 , H01L29/6609 , H01L29/66181 , H01L29/66613 , H01L29/66628 , H01L29/66651 , H01L29/66757 , H01L29/66765 , H01L29/78675 , H01L29/78678 , H01L29/49 , H01L29/78654
摘要： A single crystal and a polycrystal having an excellent crystal quality and providing a highly reliable semiconductor device are formed by solid phase growth at low temperatures. An amorphous thin film is deposited on a substrate such that an average inter-atomic distance of main constituent element of the amorphous thin film is 1.02 times or more of an average inter-atomic distance of the elements in single crystal, and crystallization energy is applied to the amorphous thin film to perform solid phase growth to thereby form a single crystal. In another embodiment of the present invention, an amorphous semiconductor thin film is formed on a substrate or an insulating film such that an average inter-atomic distance distribution of main constituent element of the film substantially coincides with an average inter-atomic distance distribution of the element in a single crystal, and crystallization energy is applied to the amorphous semiconductor thin film to cause solid phase growth to thereby form a single crystalline semiconductor thin film.

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