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11. 发明授权

US08610236B2 Edge devices layout for improved performance 有权
标题翻译：边缘设备布局，以提高性能
公开(公告)号：US08610236B2
公开(公告)日：2013-12-17
申请号：US12851702
申请日：2010-08-06
申请人： Yen-Huei Chen , Jung-Hsuan Chen , Shao-Yu Chou , Hung-Jen Liao , Li-Chun Tien
发明人： Yen-Huei Chen , Jung-Hsuan Chen , Shao-Yu Chou , Hung-Jen Liao , Li-Chun Tien
IPC分类号： H01L27/08
CPC分类号： H01L21/28008 , H01L21/28123 , H01L21/823425 , H01L21/823481 , H01L27/0207 , H01L29/66628 , H01L29/7848
摘要： A word line driver includes an active area having a length that extends in a first direction over a semiconductor substrate. A plurality of fingers formed over an upper surface of the active area. Each of the plurality of fingers has a length that extends in a second direction and forms a MOS transistor with a portion of the active area. A first dummy structure is disposed between an outer one of the plurality of fingers and an edge of the semiconductor substrate. The first dummy structure includes a portion that is at least partially disposed over a portion of the active area.
摘要翻译：字线驱动器包括具有沿半导体衬底的第一方向延伸的长度的有源区。多个指状物形成在有源区域的上表面上。多个指状物中的每一个具有在第二方向上延伸的长度，并且形成具有有效区域的一部分的MOS晶体管。第一虚设结构设置在多个指状物的外部之一和半导体衬底的边缘之间。第一虚拟结构包括至少部分地设置在有效区域的一部分上的部分。

12. 发明申请

US20120181707A1 Distributed Metal Routing 有权
标题翻译：分布式金属路由
公开(公告)号：US20120181707A1
公开(公告)日：2012-07-19
申请号：US13007235
申请日：2011-01-14
申请人： You-Cheng Xiao , Yen-Huei Chen , Jung-Hsuan Chen , Shao-Yu Chou , Li-Chun Tien , Hung-Jen Liao
发明人： You-Cheng Xiao , Yen-Huei Chen , Jung-Hsuan Chen , Shao-Yu Chou , Li-Chun Tien , Hung-Jen Liao
IPC分类号： H01L23/48 , H01L21/28
CPC分类号： H01L21/76879 , H01L21/768 , H01L21/76832 , H01L23/4824 , H01L23/485 , H01L23/522 , H01L23/528 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： A system and method for a distributed metal routing is disclosed. An embodiment comprises a metal_0 layer with a metal_1 layer overlying the metal_0 layer. The metal_1 layer comprises separate parallel lines, with lines having different signals being distributed across the metal_1 layer. Such a layout decreases the parasitic resistance within the metal_0 layer as it decreases the distance current travels. Additionally, the distributed layout in metal_1 allows connections to be made to a metal_2 layer without the need for a hammer head connection of vias.
摘要翻译：公开了一种用于分布式金属布线的系统和方法。一个实施例包括具有覆盖在metal_0层上的metal_1层的metal_0层。金属层1包括分开的平行线，具有不同信号的线分布在metal_1层上。这样的布局减小了metal_0层内的寄生电阻，因为它减小了电流行进的距离。此外，metal_1中的分布式布局允许连接到metal_2层，而不需要通孔的锤头连接。

13. 发明授权

US08111542B2 8T low leakage SRAM cell 有权
标题翻译： 8T低泄漏SRAM单元
公开(公告)号：US08111542B2
公开(公告)日：2012-02-07
申请号：US12273959
申请日：2008-11-19
申请人： Jui-Jen Wu , Yen-Huei Chen , Shao-Yu Chou , Hung-Jen Liao
发明人： Jui-Jen Wu , Yen-Huei Chen , Shao-Yu Chou , Hung-Jen Liao
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： This invention discloses a static random access memory (SRAM) cell comprising a pair of cross-coupled inverters having a storage node, and a NMOS transistor having a gate terminal, a first and a second source/drain terminal connected to the storage node, a read word-line (RWL) and a read bit-line (RBL), respectively, the RWL and RBL being activated during a read operation and not being activated during any write operation.
摘要翻译：本发明公开了一种静态随机存取存储器（SRAM）单元，其包括具有存储节点的一对交叉耦合的反相器，以及具有栅极端子，连接到存储节点的第一和第二源极/漏极端子的NMOS晶体管，分别读取字线（RWL）和读位线（RBL），RWL和RBL在读操作期间被激活，并且在任何写操作期间未被激活。

14. 发明授权

US08077517B2 Distributed VDC for SRAM memory 有权
标题翻译：分布式VDC用于SRAM存储器
公开(公告)号：US08077517B2
公开(公告)日：2011-12-13
申请号：US12338732
申请日：2008-12-18
申请人： Li-Wen Wang , Yen-Huei Chen , Chen-Lin Yang , Hsien-Yu Pan , Shao-Yu Chou , Hung-Jen Liao
发明人： Li-Wen Wang , Yen-Huei Chen , Chen-Lin Yang , Hsien-Yu Pan , Shao-Yu Chou , Hung-Jen Liao
IPC分类号： G11C11/34
CPC分类号： G11C11/413 , G11C5/04 , G11C5/147
摘要： An integrated circuit structure includes a memory. The memory includes a first memory macro and a second memory macro identical to the first memory macro. A first power block is connected to the first memory macro and is configured to provide a regulated voltage to the first memory macro. The first power block has a first input and a first output. A second power block substantially identical to the first power block is connected to the second memory macro and is configured to provide the regulated voltage to the second memory macro. The second power block has a second input and a second output. The first input and the second input are interconnected. The first output and the second output are interconnected.
摘要翻译：集成电路结构包括存储器。存储器包括与第一存储器宏相同的第一存储器宏和第二存储器宏。第一功率块连接到第一存储器宏，并被配置为向第一存储器宏提供调节电压。第一功率块具有第一输入和第一输出。基本上与第一功率块相同的第二功率块连接到第二存储器宏，并且被配置为向第二存储器宏提供调节电压。第二功率块具有第二输入和第二输出。第一输入和第二输入互连。第一个输出和第二个输出相互连接。

15. 发明申请

US20090316498A1 CIRCUIT AND METHOD FOR VDD-TRACKING CVDD VOLTAGE SUPPLY 有权
标题翻译：用于VDD跟踪CVDD电压供应的电路和方法
公开(公告)号：US20090316498A1
公开(公告)日：2009-12-24
申请号：US12205243
申请日：2008-09-05
申请人： Yen-Huei Chen , Wei Min Chan , Shao-Yu Chou
发明人： Yen-Huei Chen , Wei Min Chan , Shao-Yu Chou
IPC分类号： G11C7/00 , G11C5/14
CPC分类号： G11C11/413 , G11C5/147
摘要： Circuit and methods for providing the CVDD supply to the cells in an SRAM array while maintaining a desired VDD voltage. A circuit is described for tracking the VDD supply voltage and providing a CVDD supply for the SRAM cells that maintains an offset above VDD until a maximum voltage for the CVDD voltage is reached. The CVDD voltage supplies the word line drivers and the cells in an SRAM array, while the bit line precharge and the remaining circuitry is operated on the VDD supply. By maintaining a maximum offset between the voltage CVDD and the supply voltage VDD, the SRAM will have the required static noise margins for reliable operation, while a lowered VDD_min voltage may also be obtained. A method for supplying a CVDD voltage to an SRAM cell array is disclosed where the CVDD voltage tracks a VDD supply voltage plus a predetermined offset voltage.
摘要翻译：用于向SRAM阵列中的单元提供CVDD电源同时保持期望的VDD电压的电路和方法。描述了用于跟踪VDD电源电压并为SRAM单元提供CVDD电源的电路，其保持高于VDD的偏移，直到达到CVDD电压的最大电压。 CVDD电压为SRAM阵列中的字线驱动器和单元供电，而位线预充电和其余电路在VDD电源上工作。通过保持电压CVDD和电源电压VDD之间的最大偏移，SRAM将具有用于可靠运行的所需静态噪声容限，同时也可获得降低的VDD_min电压。公开了一种向SRAM单元阵列提供CVDD电压的方法，其中CVDD电压跟踪VDD电源电压加上预定的偏移电压。

16. 发明授权

US08391097B2 Memory word-line driver having reduced power consumption 有权
标题翻译：存储器字线驱动器具有降低的功耗
公开(公告)号：US08391097B2
公开(公告)日：2013-03-05
申请号：US12786791
申请日：2010-05-25
申请人： Wei Min Chan , Yen-Huei Chen , Chen-Lin Yang , Hsiu-Hui Yang , Shao-Yu Chou
发明人： Wei Min Chan , Yen-Huei Chen , Chen-Lin Yang , Hsiu-Hui Yang , Shao-Yu Chou
IPC分类号： G11C11/34 , G11C7/00
CPC分类号： G11C16/30 , G11C8/08
摘要： A word-line driving circuit for driving a word-line in a memory array includes a NAND circuit having a pair of address inputs and an output, an output inverter circuit having an inverter power supply node, an input coupled to the output of the NAND circuit and an output for providing a word line signal, a power gate coupled between a first power supply node and the inverter power supply node, and a control circuit coupled to the power gate. The control circuit controls the power gate to place the word line driver circuit in active or standby mode in response to the output of the NAND circuit.
摘要翻译：用于驱动存储器阵列中的字线的字线驱动电路包括具有一对地址输入和输出的NAND电路，具有反相器电源节点的输出反相器电路，耦合到NAND的输出的输入电路和用于提供字线信号的输出，耦合在第一电源节点和逆变器电源节点之间的电源栅极以及耦合到电源门的控制电路。控制电路控制电源门以响应于NAND电路的输出将字线驱动电路置于有效或待机模式。

17. 发明申请

US20110292754A1 MEMORY WORD-LINE DRIVER HAVING REDUCED POWER CONSUMPTION 有权
标题翻译：具有降低功耗的存储器字线驱动器
公开(公告)号：US20110292754A1
公开(公告)日：2011-12-01
申请号：US12786791
申请日：2010-05-25
申请人： Wei Min Chan , Yen-Huei Chen , Chen-Lin Yang , Hsiu-Hui Yang , Shao-Yu Chou
发明人： Wei Min Chan , Yen-Huei Chen , Chen-Lin Yang , Hsiu-Hui Yang , Shao-Yu Chou
IPC分类号： G11C8/08
CPC分类号： G11C16/30 , G11C8/08
摘要： A word-line driving circuit for driving a word-line in a memory array includes a NAND circuit having a pair of address inputs and an output, an output inverter circuit having an inverter power supply node, an input coupled to the output of the NAND circuit and an output for providing a word line signal, a power gate coupled between a first power supply node and the inverter power supply node, and a control circuit coupled to the power gate. The control circuit controls the power gate to place the word line driver circuit in active or standby mode in response to the output of the NAND circuit.
摘要翻译：用于驱动存储器阵列中的字线的字线驱动电路包括具有一对地址输入和输出的NAND电路，具有反相器电源节点的输出反相器电路，耦合到NAND的输出的输入电路和用于提供字线信号的输出，耦合在第一电源节点和逆变器电源节点之间的电源栅极以及耦合到电源门的控制电路。控制电路控制电源门以响应于NAND电路的输出将字线驱动电路置于有效或待机模式。

18. 发明授权

US08576655B2 Semiconductor memories 有权
标题翻译：半导体存储器
公开(公告)号：US08576655B2
公开(公告)日：2013-11-05
申请号：US13164807
申请日：2011-06-21
申请人： Wei Min Chan , Yen-Huei Chen , Jihi-Yu Lin , Hsien-Yu Pan , Hung-Jen Liao
发明人： Wei Min Chan , Yen-Huei Chen , Jihi-Yu Lin , Hsien-Yu Pan , Hung-Jen Liao
IPC分类号： G11C8/00
CPC分类号： G11C11/412
摘要： A semiconductor memory includes a bit cell having first and inverters forming a latch. First and second transistors are respectively coupled to first and second storage nodes of the latch and to first and second write bit lines. Each of the first and second transistors has a respective gate coupled to a first node. Third and fourth transistors are coupled together in series at the first node and are disposed between a write word line and a first voltage source. Each of the first and second transistors has a respective gate coupled to a first control line. A fifth transistor has a source coupled to a second voltage source, a drain coupled to at least one of the inverters of the latch, and a gate coupled to the first node. A read port is coupled to a first read bit line and to the second storage node of the latch.
摘要翻译：半导体存储器包括具有形成锁存器的第一和反相器的位单元。第一和第二晶体管分别耦合到锁存器的第一和第二存储节点以及第一和第二写入位线。第一和第二晶体管中的每一个具有耦合到第一节点的相应栅极。第三和第四晶体管在第一节点处串联耦合在一起，并且设置在写入字线和第一电压源之间。第一和第二晶体管中的每一个具有耦合到第一控制线的相应栅极。第五晶体管具有耦合到第二电压源的源极，耦合到锁存器的至少一个反相器的漏极和耦合到第一节点的栅极。读端口耦合到第一读位线和锁存器的第二存储节点。

19. 发明申请

US20120195106A1 SRAM Timing Cell Apparatus and Methods 有权
标题翻译： SRAM定时单元设备和方法
公开(公告)号：US20120195106A1
公开(公告)日：2012-08-02
申请号：US13017793
申请日：2011-01-31
申请人： Li-Wen Wang , Shao-Yu Chou , Jihi-Yu Lin , Wei Min Chan , Yen-Huei Chen , Ping Wang
发明人： Li-Wen Wang , Shao-Yu Chou , Jihi-Yu Lin , Wei Min Chan , Yen-Huei Chen , Ping Wang
IPC分类号： G11C11/40 , G11C7/06
CPC分类号： G11C7/227 , G11C11/418
摘要： Apparatus and methods for providing SRAM timing tracking cell circuits are disclosed. In an embodiment, an apparatus comprises an SRAM array comprising static random access memory cells arranged in rows and columns; a plurality of word lines each coupled to memory cells along one of the rows; a clock generation circuit for outputting clock signals; a word line generation circuit for generating a pulse on the plurality of word lines responsive to one of the clock signals and for ending the pulse responsive to one of the clock signals; and a tracking cell for receiving a clock signal and for outputting a word line pulse end signal to the clock generation circuit, following an SRAM tracking time; wherein the tracking cell further comprises SRAM tracking circuits positioned in the SRAM array and coupled in series to provide a signal indicating the SRAM tracking time. Methods for SRAM timing are disclosed.
摘要翻译：公开了用于提供SRAM定时跟踪单元电路的装置和方法。在一个实施例中，一种装置包括一个SRAM阵列，它包括排列成行和列的静态随机存取存储单元; 多条字线，每条字线都沿着一条行与存储器单元耦合; 用于输出时钟信号的时钟发生电路; 字线生成电路，用于响应于所述时钟信号中的一个生成在所述多个字线上的脉冲，并响应于所述时钟信号之一来终止所述脉冲; 以及跟踪单元，用于接收时钟信号并用于在SRAM跟踪时间之后将时钟产生电路输出字线脉冲结束信号; 其中所述跟踪单元还包括位于所述SRAM阵列中并且串联耦合的SRAM跟踪电路，以提供指示所述SRAM跟踪时间的信号。公开了SRAM定时的方法。

20. 发明授权

US07952939B2 Circuit and method for VDD-tracking CVDD voltage supply 有权
标题翻译：用于VDD跟踪CVDD电压源的电路和方法
公开(公告)号：US07952939B2
公开(公告)日：2011-05-31
申请号：US12205243
申请日：2008-09-05
申请人： Yen-Huei Chen , Wei Min Chan , Shao-Yu Chou
发明人： Yen-Huei Chen , Wei Min Chan , Shao-Yu Chou
IPC分类号： G11C5/14
CPC分类号： G11C11/413 , G11C5/147
摘要： Circuit and methods for providing the CVDD supply to the cells in an SRAM array while maintaining a desired VDD voltage. A circuit is described for tracking the VDD supply voltage and providing a CVDD supply for the SRAM cells that maintains an offset above VDD until a maximum voltage for the CVDD voltage is reached. The CVDD voltage supplies the word line drivers and the cells in an SRAM array, while the bit line precharge and the remaining circuitry is operated on the VDD supply. By maintaining a maximum offset between the voltage CVDD and the supply voltage VDD, the SRAM will have the required static noise margins for reliable operation, while a lowered VDD_min voltage may also be obtained. A method for supplying a CVDD voltage to an SRAM cell array is disclosed where the CVDD voltage tracks a VDD supply voltage plus a predetermined offset voltage.
摘要翻译：用于向SRAM阵列中的单元提供CVDD电源同时保持期望的VDD电压的电路和方法。描述了用于跟踪VDD电源电压并为SRAM单元提供CVDD电源的电路，其保持高于VDD的偏移，直到达到CVDD电压的最大电压。 CVDD电压为SRAM阵列中的字线驱动器和单元供电，而位线预充电和其余电路在VDD电源上工作。通过保持电压CVDD和电源电压VDD之间的最大偏移，SRAM将具有用于可靠运行的所需静态噪声容限，同时也可获得降低的VDD_min电压。公开了一种向SRAM单元阵列提供CVDD电压的方法，其中CVDD电压跟踪VDD电源电压加上预定的偏移电压。

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