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1. 发明申请

US20120195106A1 SRAM Timing Cell Apparatus and Methods 有权
标题翻译： SRAM定时单元设备和方法
公开(公告)号：US20120195106A1
公开(公告)日：2012-08-02
申请号：US13017793
申请日：2011-01-31
申请人： Li-Wen Wang , Shao-Yu Chou , Jihi-Yu Lin , Wei Min Chan , Yen-Huei Chen , Ping Wang
发明人： Li-Wen Wang , Shao-Yu Chou , Jihi-Yu Lin , Wei Min Chan , Yen-Huei Chen , Ping Wang
IPC分类号： G11C11/40 , G11C7/06
CPC分类号： G11C7/227 , G11C11/418
摘要： Apparatus and methods for providing SRAM timing tracking cell circuits are disclosed. In an embodiment, an apparatus comprises an SRAM array comprising static random access memory cells arranged in rows and columns; a plurality of word lines each coupled to memory cells along one of the rows; a clock generation circuit for outputting clock signals; a word line generation circuit for generating a pulse on the plurality of word lines responsive to one of the clock signals and for ending the pulse responsive to one of the clock signals; and a tracking cell for receiving a clock signal and for outputting a word line pulse end signal to the clock generation circuit, following an SRAM tracking time; wherein the tracking cell further comprises SRAM tracking circuits positioned in the SRAM array and coupled in series to provide a signal indicating the SRAM tracking time. Methods for SRAM timing are disclosed.
摘要翻译：公开了用于提供SRAM定时跟踪单元电路的装置和方法。在一个实施例中，一种装置包括一个SRAM阵列，它包括排列成行和列的静态随机存取存储单元; 多条字线，每条字线都沿着一条行与存储器单元耦合; 用于输出时钟信号的时钟发生电路; 字线生成电路，用于响应于所述时钟信号中的一个生成在所述多个字线上的脉冲，并响应于所述时钟信号之一来终止所述脉冲; 以及跟踪单元，用于接收时钟信号并用于在SRAM跟踪时间之后将时钟产生电路输出字线脉冲结束信号; 其中所述跟踪单元还包括位于所述SRAM阵列中并且串联耦合的SRAM跟踪电路，以提供指示所述SRAM跟踪时间的信号。公开了SRAM定时的方法。

2. 发明授权

US08477527B2 SRAM timing cell apparatus and methods 有权
标题翻译： SRAM定时单元装置和方法
公开(公告)号：US08477527B2
公开(公告)日：2013-07-02
申请号：US13017793
申请日：2011-01-31
申请人： Li-Wen Wang , Shao-Yu Chou , Jihi-Yu Lin , Wei Min Chan , Yen-Huei Chen , Ping Wang
发明人： Li-Wen Wang , Shao-Yu Chou , Jihi-Yu Lin , Wei Min Chan , Yen-Huei Chen , Ping Wang
IPC分类号： G11C11/00
CPC分类号： G11C7/227 , G11C11/418
摘要： Apparatus and methods for providing SRAM timing tracking cell circuits are disclosed. In an embodiment, an apparatus comprises an SRAM array comprising static random access memory cells arranged in rows and columns; a plurality of word lines each coupled to memory cells along one of the rows; a clock generation circuit for outputting clock signals; a word line generation circuit for generating a pulse on the plurality of word lines responsive to one of the clock signals and for ending the pulse responsive to one of the clock signals; and a tracking cell for receiving a clock signal and for outputting a word line pulse end signal to the clock generation circuit, following an SRAM tracking time; wherein the tracking cell further comprises SRAM tracking circuits positioned in the SRAM array and coupled in series to provide a signal indicating the SRAM tracking time. Methods for SRAM timing are disclosed.
摘要翻译：公开了用于提供SRAM定时跟踪单元电路的装置和方法。在一个实施例中，一种装置包括一个SRAM阵列，它包括排列成行和列的静态随机存取存储单元; 多条字线，每条字线都沿着一条行与存储器单元耦合; 用于输出时钟信号的时钟发生电路; 字线生成电路，用于响应于所述时钟信号中的一个生成在所述多个字线上的脉冲，并响应于所述时钟信号之一来终止所述脉冲; 以及跟踪单元，用于接收时钟信号并用于在SRAM跟踪时间之后将时钟产生电路输出字线脉冲结束信号; 其中所述跟踪单元还包括位于所述SRAM阵列中并且串联耦合的SRAM跟踪电路，以提供指示所述SRAM跟踪时间的信号。公开了SRAM定时的方法。

3. 发明授权

US08644087B2 Leakage-aware keeper for semiconductor memory 有权
标题翻译：用于半导体存储器的漏电保护器
公开(公告)号：US08644087B2
公开(公告)日：2014-02-04
申请号：US13177711
申请日：2011-07-07
申请人： Jihi-Yu Lin , Li-Wen Wang , Wei Min Chan , Yen-Huei Chen
发明人： Jihi-Yu Lin , Li-Wen Wang , Wei Min Chan , Yen-Huei Chen
IPC分类号： G11C7/10
CPC分类号： G11C7/04 , G11C11/417
摘要： A circuit includes a first circuit configured to sense a leakage of a first bit line and output a first signal in response, and a second circuit configured to receive the first signal output from the first circuit and in response supply current to a second bit line for maintaining a voltage level of the second bit line.
摘要翻译：电路包括被配置为感测第一位线的泄漏并响应地输出第一信号的第一电路，以及被配置为接收从第一电路输出的第一信号并响应于向第二位线提供电流的第二电路，维持第二位线的电压电平。

4. 发明申请

US20130010544A1 LEAKAGE-AWARE KEEPER FOR SEMICONDUCTOR MEMORY 有权
标题翻译：漏电保护器用于半导体存储器
公开(公告)号：US20130010544A1
公开(公告)日：2013-01-10
申请号：US13177711
申请日：2011-07-07
申请人： Jihi-Yu LIN , Li-Wen Wang , Wei Min Chan , Yen-Huei Chen
发明人： Jihi-Yu LIN , Li-Wen Wang , Wei Min Chan , Yen-Huei Chen
IPC分类号： G11C7/10 , G11C7/00
CPC分类号： G11C7/04 , G11C11/417
摘要： A circuit includes a first circuit configured to sense a leakage of a first bit line and output a first signal in response, and a second circuit configured to receive the first signal output from the first circuit and in response supply current to a second bit line for maintaining a voltage level of the second bit line.
摘要翻译：电路包括被配置为感测第一位线的泄漏并响应地输出第一信号的第一电路，以及被配置为接收从第一电路输出的第一信号并且响应于向第二位线提供电流的第二电路，维持第二位线的电压电平。

5. 发明授权

US08441885B2 Methods and apparatus for memory word line driver 有权
标题翻译：内存字线驱动程序的方法和装置
公开(公告)号：US08441885B2
公开(公告)日：2013-05-14
申请号：US13051681
申请日：2011-03-18
申请人： Wei Min Chan , Li-Wen Wang , Jihi-Yu Lin , Chen-Lin Yang , Shao-Yu Chou
发明人： Wei Min Chan , Li-Wen Wang , Jihi-Yu Lin , Chen-Lin Yang , Shao-Yu Chou
IPC分类号： G11C8/00
CPC分类号： G11C8/08 , G11C8/18 , G11C11/413
摘要： A word line driver circuit and corresponding methods are disclosed. An apparatus, comprising a decoder circuit coupled to receive address inputs, and having a decoder output; and a word line clock gating circuit coupled to the decoder output and to a word line clock signal, configured to selectively output a word line signal responsive to an edge on the word line clock signal; wherein the address inputs have a set up time requirement relative to the edge of the word line clock signal, and the address inputs have a zero or less hold time requirement relative to the edge of the word line clock signal. Methods for providing a word line signal from a word line driver are disclosed.
摘要翻译：公开了一种字线驱动电路及相应的方法。一种装置，包括被耦合以接收地址输入并具有解码器输出的解码器电路; 以及字线时钟选通电路，其耦合到所述解码器输出和字线时钟信号，被配置为响应于所述字线时钟信号上的边沿选择性地输出字线信号; 其中所述地址输入具有相对于所述字线时钟信号的边缘的建立时间要求，并且所述地址输入相对于所述字线时钟信号的边缘具有零或更小的保持时间要求。公开了从字线驱动器提供字线信号的方法。

6. 发明申请

US20120236675A1 Methods and Apparatus for Memory Word Line Driver 有权
标题翻译：内存字线驱动程序的方法和装置
公开(公告)号：US20120236675A1
公开(公告)日：2012-09-20
申请号：US13051681
申请日：2011-03-18
申请人： Wei Min Chan , Li-Wen Wang , Jihi-Yu Lin , Chen-Lin Yang , Shao-Yu Chou
发明人： Wei Min Chan , Li-Wen Wang , Jihi-Yu Lin , Chen-Lin Yang , Shao-Yu Chou
IPC分类号： G11C8/10
CPC分类号： G11C8/08 , G11C8/18 , G11C11/413
摘要： A word line driver circuit and corresponding methods are disclosed. An apparatus, comprising a decoder circuit coupled to receive address inputs, and having a decoder output; and a word line clock gating circuit coupled to the decoder output and to a word line clock signal, configured to selectively output a word line signal responsive to an edge on the word line clock signal; wherein the address inputs have a set up time requirement relative to the edge of the word line clock signal, and the address inputs have a zero or less hold time requirement relative to the edge of the word line clock signal. Methods for providing a word line signal from a word line driver are disclosed.
摘要翻译：公开了一种字线驱动电路及相应的方法。一种装置，包括被耦合以接收地址输入并具有解码器输出的解码器电路; 以及字线时钟选通电路，其耦合到所述解码器输出和字线时钟信号，被配置为响应于所述字线时钟信号上的边沿选择性地输出字线信号; 其中所述地址输入具有相对于所述字线时钟信号的边缘的建立时间要求，并且所述地址输入相对于所述字线时钟信号的边缘具有零或更小的保持时间要求。公开了从字线驱动器提供字线信号的方法。

7. 发明申请

US20100157692A1 Distributed VDC for SRAM Memory 有权
标题翻译：分布式VDC用于SRAM存储器
公开(公告)号：US20100157692A1
公开(公告)日：2010-06-24
申请号：US12338732
申请日：2008-12-18
申请人： Li-Wen Wang , Yen-Huei Chen , Chen-Lin Yang , Hsien-Yu Pan , Shao-Yu Chou , Hung-Jen Liao
发明人： Li-Wen Wang , Yen-Huei Chen , Chen-Lin Yang , Hsien-Yu Pan , Shao-Yu Chou , Hung-Jen Liao
IPC分类号： G11C7/00 , G11C5/14
CPC分类号： G11C11/413 , G11C5/04 , G11C5/147
摘要： An integrated circuit structure includes a memory. The memory includes a first memory macro and a second memory macro identical to the first memory macro. A first power block is connected to the first memory macro and is configured to provide a regulated voltage to the first memory macro. The first power block has a first input and a first output. A second power block substantially identical to the first power block is connected to the second memory macro and is configured to provide the regulated voltage to the second memory macro. The second power block has a second input and a second output. The first input and the second input are interconnected. The first output and the second output are interconnected.
摘要翻译：集成电路结构包括存储器。存储器包括与第一存储器宏相同的第一存储器宏和第二存储器宏。第一功率块连接到第一存储器宏，并被配置为向第一存储器宏提供调节电压。第一功率块具有第一输入和第一输出。基本上与第一功率块相同的第二功率块连接到第二存储器宏，并且被配置为向第二存储器宏提供调节电压。第二功率块具有第二输入和第二输出。第一输入和第二输入互连。第一个输出和第二个输出相互连接。

8. 发明授权

US08077517B2 Distributed VDC for SRAM memory 有权
标题翻译：分布式VDC用于SRAM存储器
公开(公告)号：US08077517B2
公开(公告)日：2011-12-13
申请号：US12338732
申请日：2008-12-18
申请人： Li-Wen Wang , Yen-Huei Chen , Chen-Lin Yang , Hsien-Yu Pan , Shao-Yu Chou , Hung-Jen Liao
发明人： Li-Wen Wang , Yen-Huei Chen , Chen-Lin Yang , Hsien-Yu Pan , Shao-Yu Chou , Hung-Jen Liao
IPC分类号： G11C11/34
CPC分类号： G11C11/413 , G11C5/04 , G11C5/147
摘要： An integrated circuit structure includes a memory. The memory includes a first memory macro and a second memory macro identical to the first memory macro. A first power block is connected to the first memory macro and is configured to provide a regulated voltage to the first memory macro. The first power block has a first input and a first output. A second power block substantially identical to the first power block is connected to the second memory macro and is configured to provide the regulated voltage to the second memory macro. The second power block has a second input and a second output. The first input and the second input are interconnected. The first output and the second output are interconnected.
摘要翻译：集成电路结构包括存储器。存储器包括与第一存储器宏相同的第一存储器宏和第二存储器宏。第一功率块连接到第一存储器宏，并被配置为向第一存储器宏提供调节电压。第一功率块具有第一输入和第一输出。基本上与第一功率块相同的第二功率块连接到第二存储器宏，并且被配置为向第二存储器宏提供调节电压。第二功率块具有第二输入和第二输出。第一输入和第二输入互连。第一个输出和第二个输出相互连接。

9. 发明授权

US08612907B2 High-speed SRAM 有权
标题翻译：高速SRAM
公开(公告)号：US08612907B2
公开(公告)日：2013-12-17
申请号：US13622419
申请日：2012-09-19
申请人： Li-Wen Wang , Jack Liu , Shao-Yu Chou
发明人： Li-Wen Wang , Jack Liu , Shao-Yu Chou
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5045
摘要： A method includes a) receiving a design for a static random access memory (SRAM) array including an SRAM cell having a read port cell, the read port cell including first and second MOS transistors each having an initial threshold voltage (Vth); b) adjusting one of a gate channel width (Wg) or a gate channel length (Lg) of one of the first and second MOS transistors to modify the Vth of at least one of the first and second MOS transistors; c) simulating a response of the SRAM array, the simulation providing response data for the SRAM array including the Vth for the first and second MOS transistors; and d) iteratively repeating steps b) and c) until a desired Vth is achieved.
摘要翻译：一种方法包括：a）接收包括具有读出端口单元的SRAM单元的静态随机存取存储器（SRAM）阵列的设计，所述读出端口单元包括具有初始阈值电压（Vth）的第一和第二MOS晶体管; b）调整第一和第二MOS晶体管之一的栅极沟道宽度（Wg）或栅极沟道长度（Lg）中的一个，以修改第一和第二MOS晶体管中的至少一个的Vth; c）模拟SRAM阵列的响应，该仿真提供包括第一和第二MOS晶体管的Vth的SRAM阵列的响应数据; 和d）重复地重复步骤b）和c），直到达到期望的Vth。

10. 发明授权

US08773923B2 Memory device and method for writing therefor 有权
标题翻译：存储器件及其写入方法
公开(公告)号：US08773923B2
公开(公告)日：2014-07-08
申请号：US13562222
申请日：2012-07-30
申请人： Yen-Huei Chen , Li-Wen Wang , Chih-Yu Lin
发明人： Yen-Huei Chen , Li-Wen Wang , Chih-Yu Lin
IPC分类号： G11C7/00 , G11C7/22 , G11C7/12
CPC分类号： G11C7/22 , G11C7/12 , G11C11/419
摘要： A method for writing a memory cell in a specific write cycle is provided. The method includes the following steps: providing a first signal having a first transition edge in the specific write cycle; providing a second signal having a second transition edge in the specific write cycle, wherein the second transition edge lags behind the first transition edge; providing a first voltage level to the memory cell; and lowering the first voltage level to a second voltage level in the specific write cycle for writing the memory cell in response to the second transition edge. A memory device is also provided.
摘要翻译：提供了一种用于在特定写入周期中写入存储器单元的方法。该方法包括以下步骤：提供在特定写周期中具有第一过渡边缘的第一信号; 提供在所述特定写周期中具有第二过渡边缘的第二信号，其中所述第二过渡边缘滞后于所述第一过渡边缘; 向所述存储器单元提供第一电压电平; 以及在所述特定写入周期中将所述第一电压电平降低到第二电压电平，以响应于所述第二过渡沿来写入所述存储器单元。还提供存储器件。

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