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11. 发明申请

US20060292800A1 ONO formation of semiconductor memory device and method of fabricating the same 有权
标题翻译： ONO形成半导体存储器件及其制造方法
公开(公告)号：US20060292800A1
公开(公告)日：2006-12-28
申请号：US11159269
申请日：2005-06-23
申请人： Yen-Hao Shih , Shih-Chin Lee , Jung-Yu Hsieh , Erh-Kun Lai , Kuang-Yeu Hsieh
发明人： Yen-Hao Shih , Shih-Chin Lee , Jung-Yu Hsieh , Erh-Kun Lai , Kuang-Yeu Hsieh
IPC分类号： H01L21/336
CPC分类号： H01L29/792 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/66833
摘要： A method of fabricating a non-volatile memory device at least comprises steps as follows. First, a substrate on which a bottom dielectric layer is formed is provided. Then, impurities are introduced through the bottom dielectric layer to the substrate, so as to form a plurality of spaced doped regions on the substrate. The structure is thermally annealed for pushing the spaced doped regions to diffuse outwardly. After annealing, a charge trapping layer is formed on the bottom dielectric layer, and a top dielectric layer is formed on the charge trapping layer. Finally, a gate structure (such as a polysilicon layer and a silicide) is formed on the top dielectric layer.
摘要翻译：一种制造非易失性存储器件的方法至少包括以下步骤。首先，提供形成有底部电介质层的基板。然后，通过底部电介质层将杂质引入衬底，以在衬底上形成多个间隔开的掺杂区域。该结构被热退火以推动间隔开的掺杂区域向外扩散。退火后，在底部电介质层上形成电荷捕捉层，在电荷捕获层上形成顶部电介质层。最后，在顶部电介质层上形成栅极结构（如多晶硅层和硅化物）。

12. 发明申请

US20060199361A1 MANUFACTURING METHOD OF ONE-TIME PROGRAMMABLE READ ONLY MEMORY 有权
标题翻译：一次性编程只读存储器的制造方法
公开(公告)号：US20060199361A1
公开(公告)日：2006-09-07
申请号：US11308550
申请日：2006-04-06
申请人： Chia-Hua Ho , Yen-Hao Shih , Hsiang-Lan Lung , Shih-Ping Hong , Shih-Chin Lee
发明人： Chia-Hua Ho , Yen-Hao Shih , Hsiang-Lan Lung , Shih-Ping Hong , Shih-Chin Lee
IPC分类号： G11C17/00 , H01L21/44
CPC分类号： H01L27/101 , G11C17/16 , H01L27/1021
摘要： An one-time programmable read only memory is provided. An N-type doping region and a first P-type doping layer are disposed in a P-type semiconductor substrate sequentially. A second P-type doping layer is disposed between the first P-type doping layer and the N-type doping region. The second P-type doping layer with higher doping level, which has a linear structure, is served as a bit line. An electrically conductive layer is disposed over the P-type semiconductor substrate. The electrically conductive layer also has a linear structure that crosses over the first P-type doping layer. The first N-type doping layer is disposed in the P-type semiconductor substrate between the electrically conductive layer and the first P-type doping layer. The arrangement of N-type and P-type doping layer is used to be selective diode device. An anti-fuse layer is disposed between the electrically conductive layer and the first N-type doping layer.
摘要翻译：提供一次性可编程只读存储器。顺序地在P型半导体衬底中设置N型掺杂区和第一P型掺杂层。第二P型掺杂层设置在第一P型掺杂层和N型掺杂区之间。具有线性结构的具有较高掺杂度的第二P型掺杂层用作位线。导电层设置在P型半导体衬底上。导电层还具有与第一P型掺杂层交叉的线性结构。第一N型掺杂层设置在P型半导体衬底之间的导电层和第一P型掺杂层之间。 N型和P型掺杂层的布置用作选择性二极管器件。在导电层和第一N型掺杂层之间设置反熔丝层。

13. 发明申请

US20090091983A1 NON-VOLATILE MEMORY STRUCTURE AND ARRAY THEREOF 有权
标题翻译：非易失性存储器结构及其阵列
公开(公告)号：US20090091983A1
公开(公告)日：2009-04-09
申请号：US11866756
申请日：2007-10-03
申请人： Shaw-Hung Ku , Shih-Chin Lee , Chia-Wei Wu , Shang-Wei Lin , Tzung-Ting Han , Ming-Shang Chen , Wen-Pin Lu
发明人： Shaw-Hung Ku , Shih-Chin Lee , Chia-Wei Wu , Shang-Wei Lin , Tzung-Ting Han , Ming-Shang Chen , Wen-Pin Lu
IPC分类号： G11C11/34
CPC分类号： H01L27/115 , H01L27/11521
摘要： A non-volatile memory structure including a substrate, stacked patterns and stress patterns is provided. The stacked patterns are disposed on the substrate. Each of the stacked patterns includes a charge storage structure and a gate from bottom to top. Here, the charge storage structure at least includes a charge storage layer. The stress patterns are disposed on the substrate between the two adjacent stacked patterns, respectively.
摘要翻译：提供了包括基板，堆叠图案和应力图案的非易失性存储器结构。层叠图案设置在基板上。每个堆叠图案包括电荷存储结构和从底部到顶部的栅极。这里，电荷存储结构至少包括电荷存储层。应力图案分别设置在两个相邻堆叠图案之间的基板上。

14. 发明申请

US20090213656A1 FLASH MEMORY HAVING INSULATING LINERS BETWEEN SOURCE/DRAIN LINES AND CHANNELS 有权
标题翻译：在源/排水管线和通道之间具有绝缘衬套的闪存
公开(公告)号：US20090213656A1
公开(公告)日：2009-08-27
申请号：US12038612
申请日：2008-02-27
申请人： Shaw Hung Ku , Teng Hao Yeh , Shih-Chin Lee , Shang-Wei Lin , Chia-Wei Wu , Tzung Ting Han , Ming Shang Chen , Wenpin Lu
发明人： Shaw Hung Ku , Teng Hao Yeh , Shih-Chin Lee , Shang-Wei Lin , Chia-Wei Wu , Tzung Ting Han , Ming Shang Chen , Wenpin Lu
IPC分类号： G11C11/34 , H01L21/8247
CPC分类号： H01L27/11568 , H01L2924/0002 , H01L2924/00
摘要： A memory array comprises a semiconductor body having a plurality of trenches aligned generally in parallel. The trenches contain semiconductor material, such as doped amorphous silicon, and act as source/drain lines for the memory array. Insulating liners lie between the semiconductor material within the trenches and the semiconductor body. A plurality of word lines overlie the plurality of trenches and channel regions in the semiconductor body in an array of cross points. Charge trapping structures lie between the word lines and the channel regions at the cross points, providing an array of flash memory cells. The charge trapping structures comprise dielectric charge trapping structures adapted to be programmed and erased to store data. A method for manufacturing such devices includes patterning and forming the sources/drain lines with insulating liners prior to formation of the charge trapping structure over the channel regions.
摘要翻译：存储器阵列包括具有大致平行对准的多个沟槽的半导体本体。沟槽包含诸如掺杂非晶硅的半导体材料，并且用作存储器阵列的源极/漏极线。绝缘衬垫位于沟槽内的半导体材料和半导体本体之间。多个字线以交叉点的阵列覆盖半导体本体中的多个沟槽和沟道区域。电荷捕获结构位于字线和交叉点处的通道区之间，提供闪存单元阵列。电荷捕获结构包括适于编程和擦除以存储数据的介电电荷俘获结构。制造这种器件的方法包括在通道区域上形成电荷俘获结构之前，利用绝缘衬垫图案化和形成源极/漏极线。

15. 发明授权

US07453127B2 Double-diffused-drain MOS device with floating non-insulator spacers 有权
标题翻译：双扩散漏极MOS器件，具有浮动非绝缘体间隔物
公开(公告)号：US07453127B2
公开(公告)日：2008-11-18
申请号：US11352791
申请日：2006-02-13
申请人： Hua-Shu Wu , Feng-Chi Hung , Hung-Lin Chen , Shih-Chin Lee
发明人： Hua-Shu Wu , Feng-Chi Hung , Hung-Lin Chen , Shih-Chin Lee
IPC分类号： H01L27/088
CPC分类号： H01L29/7887 , H01L29/402 , H01L29/7835
摘要： A double-diffused-drain metal-oxide-semiconductor device has a gate structure overlying a semiconductor substrate, a pair of insulator spacers on the sidewalls of the gate structure respectively, and a pair of floating non-insulator spacers embedded in the pair of insulator spacers respectively.
摘要翻译：双扩散漏极金属氧化物半导体器件具有覆盖半导体衬底的栅极结构，分别在栅极结构的侧壁上的一对绝缘体间隔物和嵌入在一对绝缘体中的一对浮动非绝缘体间隔物间隔物。

16. 发明授权

US08466508B2 Non-volatile memory structure including stress material between stacked patterns 有权
标题翻译：非易失性存储器结构，包括层叠图案之间的应力材料
公开(公告)号：US08466508B2
公开(公告)日：2013-06-18
申请号：US11866756
申请日：2007-10-03
申请人： Shaw-Hung Ku , Shih-Chin Lee , Chia-Wei Wu , Shang-Wei Lin , Tzung-Ting Han , Ming-Shang Chen , Wen-Pin Lu
发明人： Shaw-Hung Ku , Shih-Chin Lee , Chia-Wei Wu , Shang-Wei Lin , Tzung-Ting Han , Ming-Shang Chen , Wen-Pin Lu
IPC分类号： H01L29/792 , H01L29/788 , H01L21/762
CPC分类号： H01L27/115 , H01L27/11521
摘要： A non-volatile memory structure including a substrate, stacked patterns and stress patterns is provided. The stacked patterns are disposed on the substrate. Each of the stacked patterns includes a charge storage structure and a gate from bottom to top. Here, the charge storage structure at least includes a charge storage layer. The stress patterns are disposed on the substrate between the two adjacent stacked patterns, respectively.
摘要翻译：提供了包括基板，堆叠图案和应力图案的非易失性存储器结构。层叠图案设置在基板上。每个堆叠图案包括电荷存储结构和从底部到顶部的栅极。这里，电荷存储结构至少包括电荷存储层。应力图案分别设置在两个相邻堆叠图案之间的基板上。

17. 发明申请

US20110047061A1 Method for detecting abnormal transactions of financial assets and information processing device performing the method 审中-公开
标题翻译：检测金融资产异常交易的方法和执行该方法的信息处理装置
公开(公告)号：US20110047061A1
公开(公告)日：2011-02-24
申请号：US12801843
申请日：2010-06-29
申请人： Shih-Chin Lee , Hwai-Chung Ho , Hong-Wei Chuang
发明人： Shih-Chin Lee , Hwai-Chung Ho , Hong-Wei Chuang
IPC分类号： G06Q40/00
CPC分类号： G06Q40/04 , G06Q40/02
摘要： A method for detecting abnormal transactions of a financial asset and an information processing device performing the method are disclosed. The method is used for detecting whether a plurality of account data have a abnormal transaction, and the method comprises the steps of: receiving historic information, wherein the historic information comprises the account data and each number of trades made on each transaction day of each account within a period; establishing a plurality of information matrixes; choosing two of the plurality of information matrixes for making an inner product operation and acquiring an inner product value; constructing the threshold of the inner product value; determining whether the inner product value is greater than the threshold of the inner product value; and if yes, determining the two corresponding accounts of the information matrixes having the abnormal transaction.
摘要翻译：公开了一种用于检测金融资产的异常交易的方法和执行该方法的信息处理装置。该方法用于检测多个帐户数据是否具有异常交易，并且该方法包括以下步骤：接收历史信息，其中历史信息包括在每个账户的每个交易日进行的账户数据和每个交易行数在一段时间内建立多个信息矩阵; 选择所述多个信息矩阵中的两个用于进行内部产品操作并获取内部产品值; 构建内积值的阈值; 确定所述内积值是否大于所述内积值的阈值; 如果是，确定具有异常交易的信息矩阵的两个对应账户。

18. 发明申请

US20070187784A1 Double-diffused-drain MOS device with floating non-insulator spacer 有权
标题翻译：具有浮动非绝缘体间隔器的双扩散漏极MOS器件
公开(公告)号：US20070187784A1
公开(公告)日：2007-08-16
申请号：US11352791
申请日：2006-02-13
申请人： Hua-Shu Wu , Feng-Chi Hung , Hung-Lin Chen , Shih-Chin Lee
发明人： Hua-Shu Wu , Feng-Chi Hung , Hung-Lin Chen , Shih-Chin Lee
IPC分类号： H01L29/94
CPC分类号： H01L29/7887 , H01L29/402 , H01L29/7835
摘要： A double-diffused-drain metal-oxide-semiconductor device has a gate structure overlying a semiconductor substrate, a pair of insulator spacers on the sidewalls of the gate structure respectively, and a pair of floating non-insulator spacers embedded in the pair of insulator spacers respectively.
摘要翻译：双扩散漏极金属氧化物半导体器件具有覆盖半导体衬底的栅极结构，分别在栅极结构的侧壁上的一对绝缘体间隔物和嵌入在一对绝缘体中的一对浮动非绝缘体间隔物间隔物。

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