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11. 发明授权

US08440376B2 Exposure determining method, method of manufacturing semiconductor device, and computer program product 有权
标题翻译：曝光确定方法，制造半导体器件的方法和计算机程序产品
公开(公告)号：US08440376B2
公开(公告)日：2013-05-14
申请号：US13007238
申请日：2011-01-14
申请人： Toshiya Kotani , Kazuya Fukuhara , Michiya Takimoto , Hidefumi Mukai , Soichi Inoue
发明人： Toshiya Kotani , Kazuya Fukuhara , Michiya Takimoto , Hidefumi Mukai , Soichi Inoue
IPC分类号： G03F9/00 , G03C5/00
CPC分类号： G03F7/70425 , G03F7/70558
摘要： According to one embodiment, a deviation amount distribution of a two-dimensional shape parameter between a mask pattern formed on a mask and a desired mask pattern is acquired as a mask pattern map. Such that a deviation amount of the two-dimensional shape parameter between a pattern on substrate formed when the mask is subjected to exposure shot to form a pattern on a substrate and a desired pattern on substrate fits within a predetermined range, an exposure is determined for each position in the exposure shot in forming the pattern on substrate based on the mask pattern map.
摘要翻译：根据一个实施例，获取形成在掩模上的掩模图案与期望的掩模图案之间的二维形状参数的偏差量分布作为掩模图案图。使得当在掩模经受曝光拍摄以形成基板上的图案和在基板上形成图案之后形成的基板上的图案之间的二维形状参数的偏移量适合在预定范围内时，确定曝光基于掩模图案图，在基板上形成图案的曝光中的每个位置。

12. 发明申请

US20110177458A1 EXPOSURE DETERMINING METHOD, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND COMPUTER PROGRAM PRODUCT 有权
标题翻译：曝光测定方法，制造半导体器件的方法和计算机程序产品
公开(公告)号：US20110177458A1
公开(公告)日：2011-07-21
申请号：US13007238
申请日：2011-01-14
申请人： Toshiya KOTANI , Kazuya Fukuhara , Michiya Takimoto , Hidefumi Mukai , Soichi Inoue
发明人： Toshiya KOTANI , Kazuya Fukuhara , Michiya Takimoto , Hidefumi Mukai , Soichi Inoue
IPC分类号： G03F7/20 , G06F17/50
CPC分类号： G03F7/70425 , G03F7/70558
摘要： According to one embodiment, a deviation amount distribution of a two-dimensional shape parameter between a mask pattern formed on a mask and a desired mask pattern is acquired as a mask pattern map. Such that a deviation amount of the two-dimensional shape parameter between a pattern on substrate formed when the mask is subjected to exposure shot to form a pattern on a substrate and a desired pattern on substrate fits within a predetermined range, an exposure is determined for each position in the exposure shot in forming the pattern on substrate based on the mask pattern map.
摘要翻译：根据一个实施例，获取形成在掩模上的掩模图案与期望的掩模图案之间的二维形状参数的偏差量分布作为掩模图案图。使得当在掩模经受曝光拍摄以形成基板上的图案和在基板上形成图案之后形成的基板上的图案之间的二维形状参数的偏移量适合在预定范围内时，确定曝光基于掩模图案图，在基板上形成图案的曝光中的每个位置。

13. 发明申请

US20120174045A1 ACCEPTANCE DETERMINING METHOD OF BLANK FOR EUV MASK AND MANUFACTURING METHOD OF EUV MASK 有权
标题翻译： EUV掩模防护罩和EUV掩模制造方法的接受度测定方法
公开(公告)号：US20120174045A1
公开(公告)日：2012-07-05
申请号：US13237790
申请日：2011-09-20
申请人： Takeshi KOSHIBA , Hidefumi Mukai , Seiro Miyoshi , Kazunori IIda
发明人： Takeshi KOSHIBA , Hidefumi Mukai , Seiro Miyoshi , Kazunori IIda
IPC分类号： G06F17/50
CPC分类号： G03F1/22 , B82Y10/00 , B82Y40/00 , G03F1/70
摘要： According to one embodiment, an acceptance determining method of a blank for an EUV mask includes evaluating whether or not an integrated circuit device becomes defective, on the basis of information of a defect contained in a blank for an EUV mask and design information of a mask pattern to be formed on the blank. The integrated circuit device is to be manufactured by using the EUV mask. The EUV mask is manufactured by forming the mask pattern on the blank. And the blank is determined to be non-defective in a case that the integrated circuit device is not to be defective.
摘要翻译：根据一个实施例，用于EUV掩模的空白的接受确定方法包括基于包含在EUV掩码的空白中的缺陷的信息和掩模的设计信息来评估集成电路器件是否变得有缺陷图案要在空白上形成。集成电路器件将通过使用EUV掩模来制造。通过在空白上形成掩模图案来制造EUV掩模。在集成电路装置不具有缺陷的情况下，判断为无缺陷。

14. 发明授权

US08975178B2 Method of manufacturing a memory device using fine patterning techniques 有权
标题翻译：使用精细图案化技术制造存储器件的方法
公开(公告)号：US08975178B2
公开(公告)日：2015-03-10
申请号：US13602841
申请日：2012-09-04
申请人： Keisuke Kikutani , Satoshi Nagashima , Hidefumi Mukai , Takehiro Kondoh , Hisataka Meguro
发明人： Keisuke Kikutani , Satoshi Nagashima , Hidefumi Mukai , Takehiro Kondoh , Hisataka Meguro
IPC分类号： H01L21/4763 , H01L21/768 , H01L21/033 , H01L21/3213 , H01L27/115
CPC分类号： H01L21/76801 , H01L21/0337 , H01L21/0338 , H01L21/32139 , H01L27/11519 , H01L27/11524 , H01L27/11548 , H01L27/11565 , H01L27/1157 , H01L27/11575
摘要： According to one embodiment, a method of manufacturing a device, includes forming a first core including a line portion extending between first and second regions and having a first width and a fringe having a dimension larger than the first width, forming a mask on the fringe and on a first sidewall on the first core, removing the first core so that a remaining portion having a dimension larger than the first width is formed below the mask, forming a second sidewall on a pattern corresponding the first sidewall and the remaining portion, the second sidewall having a second width less than the first width and facing a first interval less than the first width in the first region and facing a second interval larger than the first interval in the second region.
摘要翻译：根据一个实施例，一种制造器件的方法包括形成包括在第一和第二区域之间延伸的线部分并具有第一宽度和具有大于第一宽度的尺寸的条纹的第一芯体，在边缘上形成掩模并且在所述第一芯上的第一侧壁上，移除所述第一芯，使得具有大于所述第一宽度的尺寸的剩余部分形成在所述掩模下方，在对应于所述第一侧壁和所述剩余部分的图案上形成第二侧壁，第二侧壁具有小于第一宽度的第二宽度并且面向小于第一区域中的第一宽度的第一间隔并且面向大于第二区域中的第一间隔的第二间隔。

15. 发明授权

US08423926B2 Acceptance determining method of blank for EUV mask and manufacturing method of EUV mask 有权
标题翻译： EUV掩模的掩模验证方法和EUV掩模的制造方法
公开(公告)号：US08423926B2
公开(公告)日：2013-04-16
申请号：US13237790
申请日：2011-09-20
申请人： Takeshi Koshiba , Hidefumi Mukai , Seiro Miyoshi , Kazunori Iida
发明人： Takeshi Koshiba , Hidefumi Mukai , Seiro Miyoshi , Kazunori Iida
IPC分类号： G06F17/50
CPC分类号： G03F1/22 , B82Y10/00 , B82Y40/00 , G03F1/70
摘要： According to one embodiment, an acceptance determining method of a blank for an EUV mask includes evaluating whether or not an integrated circuit device becomes defective, on the basis of information of a defect contained in a blank for an EUV mask and design information of a mask pattern to be formed on the blank. The integrated circuit device is to be manufactured by using the EUV mask. The EUV mask is manufactured by forming the mask pattern on the blank. And the blank is determined to be non-defective in a case that the integrated circuit device is not to be defective.
摘要翻译：根据一个实施例，用于EUV掩模的空白的接受确定方法包括基于包含在EUV掩码的空白中的缺陷的信息和掩模的设计信息来评估集成电路器件是否变得有缺陷图案要在空白上形成。集成电路器件将通过使用EUV掩模来制造。通过在空白上形成掩模图案来制造EUV掩模。在集成电路装置不具有缺陷的情况下，判断为无缺陷。

16. 发明授权

US08178366B2 Pattern forming method, manufacturing method of semiconductor device, and template manufacturing method 有权
标题翻译：图案形成方法，半导体器件的制造方法和模板制造方法
公开(公告)号：US08178366B2
公开(公告)日：2012-05-15
申请号：US13015351
申请日：2011-01-27
申请人： Seiro Miyoshi , Hidefumi Mukai , Takeshi Koshiba
发明人： Seiro Miyoshi , Hidefumi Mukai , Takeshi Koshiba
IPC分类号： H01L21/66
CPC分类号： G03F7/0002 , B82Y10/00 , B82Y40/00 , Y10S977/887
摘要： In the pattern forming method according to the embodiment, second templates are manufactured by an imprint technology using first templates manufactured by applying a predetermined misalignment distribution for each shot on a first substrate by an exposure apparatus. Then, an upper-layer-side pattern is formed by an imprint technology using a second template in which an inter-layer misalignment amount between a lower-layer-side pattern already formed above a second substrate and the upper-layer-side pattern to be formed above the second substrate becomes equal to or lower than a predetermined reference value.
摘要翻译：在根据实施例的图案形成方法中，通过压印技术制造第二模板，使用通过由曝光装置在第一基板上施加每次拍摄的预定的未对准分布而制造的第一模板。然后，通过使用第二模板的压印技术形成上层侧图案，其中在已经形成在第二基板上的下层侧图案与上层侧图案之间的层间未对准量与形成在第二基板的上方成为规定的基准值以下。

17. 发明申请

US20090246954A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20090246954A1
公开(公告)日：2009-10-01
申请号：US12406430
申请日：2009-03-18
申请人： Seiro Miyoshi , Hidefumi Mukai , Kazuyuki Masukawa
发明人： Seiro Miyoshi , Hidefumi Mukai , Kazuyuki Masukawa
IPC分类号： H01L21/308
CPC分类号： H01L21/31116 , H01L21/0337 , H01L21/32139
摘要： A method of manufacturing a semiconductor device, includes forming a plurality of core portions arranged in a predetermined direction, on a to-be-processed film, forming a stacked sidewall portion in which a first sidewall portion and a second sidewall portion are stacked in that order, on each of side surfaces, of each of the core portions, removing the core portions to form a structure having a first space between the adjacent first sidewall portions and a second space between the adjacent second sidewall portions, and retreating at least one of the first sidewall portion and the second sidewall portion by a desired retreat amount to slim the stacked sidewall portion, after removing the core portions.
摘要翻译：一种制造半导体器件的方法，包括在被处理的膜上形成沿预定方向布置的多个芯部，形成层叠的第一侧壁部和第二侧壁部的层叠侧壁部，在每个芯部分的每个侧表面上，顺序地移除芯部分以形成在相邻的第一侧壁部分之间具有第一空间的结构和在相邻的第二侧壁部分之间的第二空间，并且退回至少一个所述第一侧壁部分和所述第二侧壁部分在所述芯部分移除之后，使所述堆叠的侧壁部分变薄。

18. 发明申请

US20110143271A1 PATTERN GENERATING METHOD AND PROCESS DETERMINING METHOD 审中-公开
标题翻译：模式生成方法和过程确定方法
公开(公告)号：US20110143271A1
公开(公告)日：2011-06-16
申请号：US12822716
申请日：2010-06-24
申请人： Takeshi KOSHIBA , Hidefumi Mukai , Kazuhito Kobayashi , Takumi Ota
发明人： Takeshi KOSHIBA , Hidefumi Mukai , Kazuhito Kobayashi , Takumi Ota
IPC分类号： G03F7/20
CPC分类号： G03F7/0002 , B82Y10/00 , B82Y40/00
摘要： A pattern generating method includes obtaining an on-substrate pattern by performing a process for forming the on-substrate pattern by simulation or experiment based on a design pattern of the on-substrate pattern formed by an imprint process using a template, employing the design pattern when a comparison result of the design pattern and obtained on-substrate pattern satisfies a predetermined condition, and correcting the design pattern to satisfy the predetermined condition when the comparison result does not satisfy the predetermined condition.
摘要翻译：图案生成方法包括通过基于通过使用模板的压印处理形成的衬底上图案的设计图案通过模拟或实验进行用于形成衬底上图案的处理来获得衬底图案，采用设计图案当设计图案和获得的基板图案的比较结果满足预定条件时，并且当比较结果不满足预定条件时，校正设计图案以满足预定条件。

19. 发明授权

US07941767B2 Photomask management method and photomask wash limit generating method 有权
标题翻译：光掩模管理方法和光掩模清洗极限生成方法
公开(公告)号：US07941767B2
公开(公告)日：2011-05-10
申请号：US12112688
申请日：2008-04-30
申请人： Hidefumi Mukai , Shinji Yamaguchi , Yukiyasu Arisawa , Toshiya Kotani
发明人： Hidefumi Mukai , Shinji Yamaguchi , Yukiyasu Arisawa , Toshiya Kotani
IPC分类号： G06F17/50 , G06F19/00 , G01B7/00 , G06K9/00
CPC分类号： G03F1/82 , G03F1/86
摘要： A photomask is washed and at least one physical amount of transmittance and phase difference of the photomask, dimension of a pattern, height of the pattern and a sidewall shape of the pattern is measured. After this, the two-dimensional shape of a borderline pattern previously determined for the photomask is measured. Lithography tolerance is derived by performing a lithography simulation for the measured two-dimensional shape by use of the measured physical amount. Then, whether the photomask can be used or not is determined based on the derived lithography tolerance.
摘要翻译：洗涤光掩模，并且测量光掩模的透光率和相位差的至少一个物理量，图案的尺寸，图案的高度和图案的侧壁形状。之后，测量先前为光掩模确定的边界图案的二维形状。通过使用测量的物理量对所测量的二维形状进行光刻模拟，导出光刻容限。然后，是否可以使用光掩模是基于导出的平版印刷公差来确定的。

20. 发明申请

US20110012297A1 PATTERN TRANSFER METHOD 审中-公开
标题翻译：图案转移方法
公开(公告)号：US20110012297A1
公开(公告)日：2011-01-20
申请号：US12718778
申请日：2010-03-05
申请人： Ayumi KOBIKI , Takeshi Koshiba , Hidefumi Mukai , Seiro Miyoshi
发明人： Ayumi KOBIKI , Takeshi Koshiba , Hidefumi Mukai , Seiro Miyoshi
IPC分类号： B29C35/08 , B29C39/00
CPC分类号： G03F7/0002 , B82Y10/00 , B82Y40/00
摘要： A pattern transfer method for transferring an uneven pattern onto a resist material is disclosed. The uneven pattern is formed in a template having a through-groove in a predetermined region. The resist material is applied to a substrate. The template is made to come into contact with the resist material. The resist material is filled to concave portion in the uneven pattern. The residual resist material leaked from a gap between the substrate and the template to the outside is sucked through the through-groove in a state where the template is in contact with the resist material. The resist material is made to cure in a state where the template is in contact with the resist material after the suction of the residual resist material. The template is separated from the cured resist material.
摘要翻译：公开了一种用于将不均匀图案转印到抗蚀剂材料上的图案转印方法。不规则图案形成在具有预定区域中的通槽的模板中。将抗蚀剂材料施加到基底上。使模板与抗蚀剂材料接触。抗蚀剂材料以不均匀图案填充到凹部。在模板与抗蚀剂材料接触的状态下，从基板和模板之间的间隙向外部泄漏的残留抗蚀剂材料通过贯通槽进行吸引。抗蚀剂材料在残留抗蚀剂材料的吸附之后，在模板与抗蚀剂材料接触的状态下使其固化。将模板与固化的抗蚀剂材料分离。

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