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11. 发明授权

US6159845A Method for manufacturing dielectric layer 有权
标题翻译：电介质层制造方法
公开(公告)号：US6159845A
公开(公告)日：2000-12-12
申请号：US395906
申请日：1999-09-11
申请人： Tri-Rung Yew , Water Lur , Hsien-Ta Chung
发明人： Tri-Rung Yew , Water Lur , Hsien-Ta Chung
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76834 , H01L21/7681 , H01L21/7682 , H01L21/7684 , H01L21/76885
摘要： A dielectric layer in a dual-damascene interconnect is described. A dual-damascene interconnect structure is formed on a substrate. The dual-damascene interconnect structure has a first dielectric layer formed over the substrate, a second dielectric layer formed on the first dielectric layer, a first wire penetrating through the second dielectric layer and a second wire. The second wire penetrates through the second dielectric layer and is electrically coupled to the substrate. The second dielectric layer is removed. A barrier cap layer is formed conformally over the substrate. A third dielectric layer is formed on the barrier cap layer and an air gap is formed in a space enclosed by the third dielectric layer, the first and the second wires. A fourth dielectric layer is formed on the third dielectric layer. A planarizing process is performed to planarize the fourth dielectric layer.
摘要翻译：描述双镶嵌互连中的电介质层。在基板上形成双镶嵌互连结构。所述双镶嵌互连结构具有形成在所述基板上的第一电介质层，形成在所述第一电介质层上的第二电介质层，穿过所述第二电介质层的第一电线和第二导线。第二线穿透第二电介质层并且电耦合到衬底。去除第二介电层。保护层形成在衬底上。第三电介质层形成在阻挡盖层上，并且在由第三电介质层，第一和第二电线围绕的空间中形成气隙。在第三电介质层上形成第四电介质层。执行平面化处理以平坦化第四介电层。

12. 发明授权

US6140192A Method for fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US6140192A
公开(公告)日：2000-10-31
申请号：US346554
申请日：1999-06-30
申请人： Michael W C Huang , Hsiao-Ling Lu , Tri-Rung Yew
发明人： Michael W C Huang , Hsiao-Ling Lu , Tri-Rung Yew
IPC分类号： H01L21/28 , H01L21/336
CPC分类号： H01L29/6659 , H01L21/28061 , H01L21/28247 , H01L29/665
摘要： A method for fabricating a semiconductor device. A substrate having a gate is provided. An ion implantation process is performed to form lightly doped source/drain region in the substrate. A liner layer and an insulation layer are formed over a substrate in sequence. A portion of the insulation layer is removed by an anisotropic etching process. The insulation layer remaining on sidewalls of the gate is used as a spacer. A top of the spacer is substantially level with an upper surface of the liner layer. An ion implantation process is performed to form heavily doped source/drain region in the substrate. A portion of the spacer is removed by wet etching. As a result, a top surface of the spacer is lower than the upper surface of the gate. The method can increase the exposed surface of the gate and maintain sufficient width of the lightly doped source/drain region to prevent the hot carrier effect and the short channel effect.
摘要翻译：一种半导体器件的制造方法。提供具有栅极的基板。执行离子注入工艺以在衬底中形成轻掺杂的源极/漏极区域。依次在衬底上形成衬垫层和绝缘层。通过各向异性蚀刻工艺去除绝缘层的一部分。留在栅极侧壁上的绝缘层用作间隔物。间隔件的顶部与衬里层的上表面基本一致。执行离子注入工艺以在衬底中形成重掺杂的源极/漏极区域。通过湿蚀刻去除间隔物的一部分。结果，间隔件的顶表面比门的上表面低。该方法可以增加栅极的暴露表面，并保持轻掺杂源极/漏极区域的足够宽度，以防止热载流子效应和短沟道效应。

13. 发明授权

US6087262A Method for manufacturing shallow trench isolation structure 有权
标题翻译：浅沟槽隔离结构的制造方法
公开(公告)号：US6087262A
公开(公告)日：2000-07-11
申请号：US189140
申请日：1998-11-09
申请人： Gwo-Shii Yang , Kuo-Tai Huang , Tri-Rung Yew , Water Lur
发明人： Gwo-Shii Yang , Kuo-Tai Huang , Tri-Rung Yew , Water Lur
IPC分类号： H01L21/3105 , H01L21/762 , H01L21/00
CPC分类号： H01L21/31053 , H01L21/76229
摘要： A method for manufacturing shallow trench isolation structure includes the steps of fabricating a self-aligned silicon nitride mask over the trench region so that a kink effect due to the misalignment of mask during a conventional mask-making process can be avoided. Moreover, the silicon nitride mask requires fewer steps and less complicated operations to construct than a conventional reverse tone mask.
摘要翻译：用于制造浅沟槽隔离结构的方法包括以下步骤：在沟槽区域上制造自对准氮化硅掩模，从而可以避免在常规掩模制造工艺期间由于掩模的未对准而产生的扭结效应。此外，与传统的反向色调掩模相比，氮化硅掩模需要更少的步骤和更少的复杂操作来构造。

14. 发明授权

US6069066A Method of forming bonding pad 有权
标题翻译：形成焊盘的方法
公开(公告)号：US6069066A
公开(公告)日：2000-05-30
申请号：US208025
申请日：1998-12-09
申请人： Yimin Huang , Tri-Rung Yew
发明人： Yimin Huang , Tri-Rung Yew
IPC分类号： H01L21/60 , H01L23/485 , H01L21/44
CPC分类号： H01L24/05 , H01L24/03 , H01L24/11 , H01L2224/0401 , H01L2224/05546 , H01L2224/05647 , H01L2224/13099 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/14
摘要： A method of forming a bonding pad is provided. A substrate is provided and a multi-metal layer is formed on the substrate. An inter-metal dielectric layer with a trench is formed on the multi-metal layer. A conformal barrier layer is formed on the inter-metal dielectric layer. A first metal layer is formed on the barrier layer to fill a part of the trench. A second metal layer is formed on the first metal layer to fill the trench. A part of the first metal layer and a part of the second metal layer flowing out the trench are removed to expose the inter-metal dielectric layer. A cap layer is formed on the inter-metal dielectric layer. A passivation layer is formed on the cap layer. A part of the passivation and a part of the cap layer are removed to form a bonding pad window by a defined masking layer.
摘要翻译：提供一种形成接合焊盘的方法。设置基板，在基板上形成多金属层。在多金属层上形成具有沟槽的金属间介电层。在金属间电介质层上形成保形阻挡层。在阻挡层上形成第一金属层以填充沟槽的一部分。在第一金属层上形成第二金属层以填充沟槽。去除第一金属层的一部分和流出沟槽的第二金属层的一部分，以露出金属间介电层。在金属间介电层上形成盖层。在盖层上形成钝化层。通过限定的掩模层去除钝化部分和覆盖层的一部分以形成焊盘窗口。

15. 发明授权

US06027994A Method to fabricate a dual metal-damascene structure in a substrate 失效
标题翻译：在基材中制造双金属镶嵌结构的方法
公开(公告)号：US06027994A
公开(公告)日：2000-02-22
申请号：US102083
申请日：1998-06-22
申请人： Yimin Huang , Tri-Rung Yew
发明人： Yimin Huang , Tri-Rung Yew
IPC分类号： H01L21/768 , H01L23/522 , H01L21/4763
CPC分类号： H01L21/76808 , H01L23/5226 , H01L2221/1031 , H01L2924/0002
摘要： A method to fabricate a dual damascene structure in a substrate is disclosed in the present invention. A first silicon oxide layer is deposited over the substrate and a silicon nitride layer is formed on the first silicon oxide layer. The first silicon oxide layer and the silicon nitride layer are etched in order to form a via hole on the substrate. Afterwards, a second silicon oxide layer is deposited to refill into the via hole and to cover the silicon nitride layer. A dry etching process is performed to remove the second silicon oxide layer in the via hole and to form a metal trench in the second silicon oxide layer on the silicon nitride layer and a metal trench in the second silicon oxide layer above the via hole. After the formation of the metal trenches, a portion of the second silicon oxide layer is remained on the sidewalls and the bottom of the via hole. A dry etching process is performed to remove the remaining portion of the second silicon oxide layer. At last, metal material is deposited to refill into the via hole and the metal trench, it is followed by the metal CMP processs to remove the excess metal over the silicon oxide. The dual metal-damascene structure on the substrate is complete.
摘要翻译：在本发明中公开了一种在衬底中制造双镶嵌结构的方法。在衬底上沉积第一氧化硅层，在第一氧化硅层上形成氮化硅层。蚀刻第一氧化硅层和氮化硅层以在基板上形成通孔。然后，沉积第二氧化硅层以重新填充到通孔中并覆盖氮化硅层。进行干蚀刻处理以去除通孔中的第二氧化硅层，并且在氮化硅层上的第二氧化硅层中形成金属沟槽，在通孔上方的第二氧化硅层中形成金属沟槽。在形成金属沟槽之后，第二氧化硅层的一部分残留在通孔的侧壁和底部。执行干蚀刻处理以去除第二氧化硅层的剩余部分。最后，沉积金属材料以再填充到通孔和金属沟槽中，之后是金属CMP工艺以除去氧化硅上的多余金属。基板上的双金属镶嵌结构完整。

16. 发明授权

US6020258A Method for unlanded via etching using etch stop 失效
标题翻译：使用蚀刻停止法进行无衬底通孔蚀刻的方法
公开(公告)号：US6020258A
公开(公告)日：2000-02-01
申请号：US982266
申请日：1997-12-01
申请人： Tri-Rung Yew , Water Lur , Shih-Wei Sun
发明人： Tri-Rung Yew , Water Lur , Shih-Wei Sun
IPC分类号： H01L21/311 , H01L21/768 , H01L21/44
CPC分类号： H01L21/76802 , H01L21/31116 , H01L21/76834 , Y10S438/97
摘要： A multilevel interconnect structure is formed in a manner that reduces the problems associated with the formation and subsequent filling of unlanded vias. A first level wiring line is provided on the surface of an interlayer dielectric. The upper surface and sidewalls of the first level wiring line are covered with an etch stop material that is different from the intermetal dielectric used to separate the first level of wiring line from upper levels of wiring lines. The intermetal dielectric layer is deposited over the first level wiring line and a via is etched through the intermetal dielectric to expose the etch stop material above the wiring line, with the via etch stopping on the etch stop material. Etch stop material is removed to expose a portion of the upper surface of the wiring line and a metal plug is formed within the via and then an upper level wiring line is formed in contact with the metal plug.
摘要翻译：形成多层互连结构，其方法是减少与无衬层通孔的形成和随后填充有关的问题。在层间电介质的表面上设置一级布线。第一级布线的上表面和侧壁被不同于用于将第一级布线与上层布线分开的金属间电介质的蚀刻停止材料覆盖。金属间电介质层沉积在第一层布线上，并通过金属间电介质蚀刻通孔，以使布线线上方的蚀刻停止材料露出，同时蚀刻停止材料上的通孔蚀刻停止。去除蚀刻停止材料以露出布线的上表面的一部分，并且在通孔内形成金属塞，然后形成与金属塞接触的上层布线。

17. 发明授权

US6017817A Method of fabricating dual damascene 有权
标题翻译：双镶嵌方法
公开(公告)号：US6017817A
公开(公告)日：2000-01-25
申请号：US309186
申请日：1999-05-10
申请人： Hsien-Ta Chung , Tri-Rung Yew , Water Lur
发明人： Hsien-Ta Chung , Tri-Rung Yew , Water Lur
IPC分类号： H01L21/768 , H01L21/4763 , H01L21/311
CPC分类号： H01L21/76807
摘要： A method of fabricating a dual damascene structure. A low k dielectric layer and a cap layer are successively formed on a substrate having an active region. A first photoresist layer is formed on the cap layer and the cap layer is then patterned to expose a portion of the low k dielectric layer. The first photoresist layer and a portion of the low k dielectric layer are simultaneously removed to form a wiring line opening. A second photoresist layer is formed on the cap layer to cover a portion of the wiring line opening. When the step of removing the second photoresist layer is performed, a via hole is formed to expose the active region by simultaneously removing the exposed low k dielectric layer. The via hole and the wiring line opening are filled with a metal layer to form a wiring line and a via.
摘要翻译：一种制造双镶嵌结构的方法。在具有有源区的基板上依次形成低k电介质层和盖层。在盖层上形成第一光致抗蚀剂层，然后对盖层进行图案化以暴露低k电介质层的一部分。同时去除第一光致抗蚀剂层和低k电介质层的一部分以形成布线开口。在盖层上形成第二光致抗蚀剂层以覆盖布线开口的一部分。当执行去除第二光致抗蚀剂层的步骤时，形成通孔，以通过同时去除暴露的低k电介质层来暴露有源区。通孔和布线开口填充有金属层以形成布线和通孔。

18. 发明授权

US5994181A Method for forming a DRAM cell electrode 失效
标题翻译：用于形成DRAM单元电极的方法
公开(公告)号：US5994181A
公开(公告)日：1999-11-30
申请号：US858398
申请日：1997-05-19
申请人： Wen-Yi Hsieh , Tri-Rung Yew
发明人： Wen-Yi Hsieh , Tri-Rung Yew
IPC分类号： H01L21/02 , H01L21/8242
CPC分类号： H01L27/10852 , H01L28/60 , H01L28/82
摘要： A polysilicon layer is subsequently deposited on the dielectric layer by using CVD. Next, photolithography and etching process are used to etch the doped polysilicon layer, and form a bottom electrode of DRAM cell capacitor with U shape in cross section view. The next step of the formation is the deposition of a dielectric film along the surface of the bottom electrode of DRAM cell capacitor. Typically, the dielectric film is preferably formed of high dielectric film such as tantalum oxide (Ta.sub.2 0.sub.5). A conductive layer is deposited over the dielectric film. The conductive layer is used as the top storage node and is formed of titanium nitride(TiN). The methods of forming the top storage node, including sputtered-TiN, collimated-sputtering TiN, and CVD/MOCVD-TiN deposition. The purposes of sputtered-TiN and collimated-sputtering TiN processes can improve the poor step coverage of deep well of bottom electrode of DRAM cell capacitor and protect the Ta.sub.2 0.sub.5 from C, Cl, F contamination during CVD/MOCVD-TiN deposition process.
摘要翻译：随后通过使用CVD将多晶硅层沉积在电介质层上。接下来，使用光刻和蚀刻工艺来蚀刻掺杂多晶硅层，并且在横截面图中形成具有U形的DRAM单元电容器的底部电极。形成的下一步是沿着DRAM单元电容器的底部电极的表面沉积电介质膜。通常，电介质膜优选由诸如氧化钽（Ta 2 O 5）的高介电膜形成。导电层沉积在电介质膜上。导电层用作顶部存储节点并且由氮化钛（TiN）形成。形成顶部存储节点的方法包括溅射TiN，准直溅射TiN和CVD / MOCVD-TiN沉积。溅射TiN和准直溅射TiN工艺的目的可以改善DRAM单元电容器底部电极深阱的差的覆盖范围，并在CVD / MOCVD-TiN沉积过程中保护Ta205不受C，Cl，F污染。

19. 发明授权

US5960299A Method of fabricating a shallow-trench isolation structure in integrated circuit 失效
标题翻译：在集成电路中制造浅沟槽隔离结构的方法
公开(公告)号：US5960299A
公开(公告)日：1999-09-28
申请号：US181466
申请日：1998-10-28
申请人： Tri-Rung Yew , Water Lur , Shih-Wei Sun
发明人： Tri-Rung Yew , Water Lur , Shih-Wei Sun
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76229 , Y10S148/05
摘要： A semiconductor fabrication method is provided for fabricating a shallow-trench isolation (STI) structure in an integrated circuit, which can prevent the occurrence of microscratches in the oxide plugs of the STI structure, thus further preventing the occurrence of a bridging effect and short-circuits between the circuit components that are intended to be electrically isolated by the STI structure. This method is characterized by the use of a laser annealing process to remove the microscratches that formed on the top surface of the oxide plugs during the chemical-mechanical polishing (CMP) process used to remove the upper part of the oxide layer to form the oxide plugs This method can therefore prevent the occurrence of a bridging effect and short-circuits due to the forming of the microscratches that would otherwise occur in the prior art.
摘要翻译：提供了一种用于在集成电路中制造浅沟槽隔离（STI）结构的半导体制造方法，其可以防止在STI结构的氧化物塞中发生微细纹理，从而进一步防止桥接效应的发生，要通过STI结构电隔离的电路元件之间的电路。该方法的特征在于使用激光退火工艺来除去在用于去除氧化物层的上部以形成氧化物的化学机械抛光（CMP）工艺期间在氧化物塞的顶表面上形成的微观尺度堵塞该方法因此可以防止桥接效应的发生和由于形成在现有技术中将会出现的微纹理造成的短路。

20. 发明申请

US20130307520A1 MICROELECTRODE ARRAY AND METHOD FOR MODIFYING CARBON NANOTUBE ELECTRODE INTERFACE OF THE SAME ARRAY 有权
标题翻译：微电极阵列和修改同一阵列碳纳米管电极接口的方法
公开(公告)号：US20130307520A1
公开(公告)日：2013-11-21
申请号：US12638429
申请日：2009-12-15
申请人： Shiang-Jie YEN , Huan-Chieh Su , Tri-Rung Yew , Yen-Chung Chang , Wei-Lun Hsu , Shih-Rung Yeh
发明人： Shiang-Jie YEN , Huan-Chieh Su , Tri-Rung Yew , Yen-Chung Chang , Wei-Lun Hsu , Shih-Rung Yeh
IPC分类号： C01B31/02 , A61N1/05
CPC分类号： C01B31/0273 , A61N1/0502 , A61N1/0551 , B82Y15/00 , B82Y30/00 , B82Y40/00 , C01B32/174
摘要： The present invention discloses a method for modifying a carbon nanotube electrode interface, which modifies carbon nanotubes used as a neuron-electrode interface by performing three stages of modifications and comprises the steps of: carboxylating carbon nanotubes to provide carboxyl functional groups and improve the hydrophilicity of the carbon nanotubes; acyl-chlorinating the carboxylated carbon nanotubes to replace the hydroxyl functional groups of the carboxyl functional groups with chlorine atoms; and aminating the acyl-chlorinated carbon nanotubes to replace the chlorine atoms with a derivative having amine functional groups at the terminal thereof. The modified carbon nanotubes used as the neuron-electrode interface has lower impedance and higher adherence to nerve cells. Thus is improved the quality of neural signal measurement. The present invention also discloses a microelectrode array, wherein the neuron-electrode interface uses carbon nanotubes modified according to the method of the present invention.
摘要翻译：本发明公开了一种修饰碳纳米管电极界面的方法，其通过进行三个阶段的修饰来改变用作神经元 - 电极界面的碳纳米管，并且包括以下步骤：使碳纳米管羧化以提供羧基官能团并提高其亲水性碳纳米管; 酰化氯化羧化碳纳米管以用氯原子代替羧基官能团的羟基官能团; 并将酰基氯化碳纳米管胺化以在其末端具有胺官能团的衍生物代替氯原子。用作神经元 - 电极界面的改性碳纳米管具有较低的阻抗和较高的对神经细胞的依从性。因此提高了神经信号测量的质量。本发明还公开了一种微电极阵列，其中神经电极界面使用根据本发明的方法改性的碳纳米管。

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