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    • 12. 发明申请
    • SIMULTANEOUS SWITCHING OF MULTIPLE TIME SLOTS IN AN OPTICAL NETWORK NODE
    • 光网络节点中多个时隙的同时切换
    • US20110055491A1
    • 2011-03-03
    • US12550497
    • 2009-08-31
    • Chung Kuang ChinShankar VenkataramanSwaroop Raghunatha
    • Chung Kuang ChinShankar VenkataramanSwaroop Raghunatha
    • G06F12/00
    • H04L49/9036
    • A switching frame buffer is described in which data units within a sequence of time slots, of a frame, may be simultaneously input and output at ports of the switching frame buffer. In one implementation, a write port may receive data units within a single cycle of the switch. A number of memories may be provided, where first selected ones of the memories constitute memory groups and second selected ones of the memories constitute a memory subsets, each of the memory groups including a corresponding one of the memory subsets. The write port may supply each of a number of copies of the data units to a corresponding one of the memory subsets. Multiplexers may be associated with the groups of the memories and a read port may receive one of the copies of a number of the data units from different ones of the multiplexers.
    • 描述了一种切换帧缓冲器,其中帧的时隙序列内的数据单元可以同时在切换帧缓冲器的端口输入和输出。 在一个实现中,写入端口可以在交换机的单个周期内接收数据单元。 可以提供多个存储器,其中存储器中的第一选定存储器构成存储器组,并且存储器中的第二选定存储器构成存储器子集,每个存储器组包括对应的一个存储器子集。 写入端口可以将数据单元的多个副本中的每一个提供给相应的一个存储器子集。 多路复用器可以与存储器组相关联,并且读取端口可以从不同的多路复用器接收多个数据单元的一个副本。
    • 17. 发明授权
    • Streamlined cache coherency protocol system and method for a multiple processor single chip device
    • 用于多处理器单芯片器件的简化高速缓存一致性协议系统和方法
    • US06918012B2
    • 2005-07-12
    • US09942328
    • 2001-08-28
    • Padmanabha I. VenkitakrishnanShankar VenkataramanStuart C. Siu
    • Padmanabha I. VenkitakrishnanShankar VenkataramanStuart C. Siu
    • G06F12/08G06F12/14
    • G06F12/0831
    • A streamlined cache coherency protocol system and method for a multiple processor single chip device. There are three primary memory unit (e.g., a cache line) states (modified, shared, and invalid) and three intermediate memory unit pending states. The pending states are used by the present invention to prevent race conditions that may develop during the completion of a transaction. The pending states “lock out” the memory unit (e.g., prevent access by other agents to a cache line) whose state is in transition between two primary states, thus ensuring coherency protocol correctness. Transitions between states are governed by a series of request and reply or acknowledgment messages. The memory unit is placed in a pending state while appropriate measures are taken to ensure access takes place at an appropriate time. For example, a modification occurs only when other agents can not access the particular memory unit (e.g., a cache line).
    • 用于多处理器单芯片器件的精简缓存一致性协议系统和方法。 存在三个主存储器单元(例如,高速缓存行)状态(修改,共享和无效)和三个中间存储器单元挂起状态。 本发明使用待决状态来防止在交易完成期间可能发展的种族条件。 挂起状态“锁定”其状态在两个主状态之间转换的存储器单元(例如,阻止其他代理到高速缓存行的访问),从而确保一致性协议的正确性。 状态之间的转换由一系列请求和回复或确认消息来管理。 存储单元处于待机状态,同时采取适当措施确保在适当的时间进行访问。 例如,仅当其他代理不能访问特定存储器单元(例如,高速缓存行)时才进行修改。