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11. 发明授权

US08438578B2 Network on chip with an I/O accelerator 失效
标题翻译：使用I / O加速器的网络芯片
公开(公告)号：US08438578B2
公开(公告)日：2013-05-07
申请号：US12135364
申请日：2008-06-09
申请人： Russell D. Hoover , Jon K. Kriegel , Eric O. Mejdrich
发明人： Russell D. Hoover , Jon K. Kriegel , Eric O. Mejdrich
IPC分类号： G06F3/00 , G06F9/44 , G06F9/46 , G06F13/00 , G06F15/00
CPC分类号： G06F9/546 , G06F15/7825 , H04L45/00
摘要： Data processing on a network on chip (‘NOC’) that includes IP blocks, routers, memory communications controllers, and network interface controllers; each IP block adapted to a router through a memory communications controller and a network interface controller; each memory communications controller controlling communication between an IP block and memory; each network interface controller controlling inter-IP block communications through routers; each IP block adapted to the network by a low latency, high bandwidth application messaging interconnect comprising an inbox and an outbox; a computer software application segmented into stages, each stage comprising a flexibly configurable module of computer program instructions identified by a stage ID with each stage executing on a thread of execution on an IP block; and at least one of the IP blocks comprising an input/output (‘I/O’) accelerator that administers at least some data communications traffic to and from the at least one IP block.
摘要翻译：芯片上的数据处理（“NOC”）包括IP块，路由器，存储器通信控制器和网络接口控制器; 每个IP块通过存储器通信控制器和网络接口控制器适应于路由器; 每个存储器通信控制器控制IP块和存储器之间的通信; 每个网络接口控制器通过路由器控制IP间块通信; 每个IP块通过包括收件箱和发件箱的低延迟，高带宽应用消息互连来适应于网络; 每个阶段包括由阶段ID标识的计算机程序指令的灵活可配置模块，每个阶段在IP块上的执行线程上执行; 并且所述IP块中的至少一个包括对至少一个IP块执行至少一些数据通信业务的输入/输出（“I / O”）加速器。

12. 发明授权

US08429377B2 Optimizing TLB entries for mixed page size storage in contiguous memory 有权
标题翻译：优化连续内存中混合页大小存储的TLB条目
公开(公告)号：US08429377B2
公开(公告)日：2013-04-23
申请号：US12684642
申请日：2010-01-08
申请人： Dong Chen , Alan Gara , Mark E. Giampapa , Philip Heidelberger , Jon K. Kriegel , Martin Ohmacht , Burkhard Steinmacher-Burow
发明人： Dong Chen , Alan Gara , Mark E. Giampapa , Philip Heidelberger , Jon K. Kriegel , Martin Ohmacht , Burkhard Steinmacher-Burow
IPC分类号： G06F12/06
CPC分类号： G06F12/1027 , G06F2212/652 , G06F2212/654
摘要： A system and method for accessing memory are provided. The system comprises a lookup buffer for storing one or more page table entries, wherein each of the one or more page table entries comprises at least a virtual page number and a physical page number; a logic circuit for receiving a virtual address from said processor, said logic circuit for matching the virtual address to the virtual page number in one of the page table entries to select the physical page number in the same page table entry, said page table entry having one or more bits set to exclude a memory range from a page.
摘要翻译：提供了一种访问存储器的系统和方法。该系统包括用于存储一个或多个页表条目的查找缓冲器，其中所述一个或多个页表条目中的每一个包括至少虚拟页码和物理页号; 用于从所述处理器接收虚拟地址的逻辑电路，所述逻辑电路用于将所述虚拟地址与所述页表项之一中的虚拟页号进行匹配，以选择所述同一页表项中的所述物理页号，所述页表项具有一个或多个位被设置为从页面排除存储器范围。

13. 发明申请

US20130024648A1 TLB EXCLUSION RANGE 有权
标题翻译： TLB排除范围
公开(公告)号：US20130024648A1
公开(公告)日：2013-01-24
申请号：US13618730
申请日：2012-09-14
申请人： Dong Chen , Alan Gara , Mark E. Giampapa , Philip Heidelberger , Jon K. Kriegel , Martin Ohmacht , Burkhard Steinmacher-Burow
发明人： Dong Chen , Alan Gara , Mark E. Giampapa , Philip Heidelberger , Jon K. Kriegel , Martin Ohmacht , Burkhard Steinmacher-Burow
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F2212/652 , G06F2212/654
摘要： A system and method for accessing memory are provided. The system comprises a lookup buffer for storing one or more page table entries, wherein each of the one or more page table entries comprises at least a virtual page number and a physical page number; a logic circuit for receiving a virtual address from said processor, said logic circuit for matching the virtual address to the virtual page number in one of the page table entries to select the physical page number in the same page table entry, said page table entry having one or more bits set to exclude a memory range from a page.
摘要翻译：提供了一种访问存储器的系统和方法。该系统包括用于存储一个或多个页表条目的查找缓冲器，其中所述一个或多个页表条目中的每一个包括至少虚拟页码和物理页号; 用于从所述处理器接收虚拟地址的逻辑电路，所述逻辑电路用于将所述虚拟地址与所述页表项之一中的虚拟页号进行匹配，以选择所述同一页表项中的所述物理页号，所述页表项具有一个或多个位被设置为从页面排除存储器范围。

14. 发明申请

US20090287885A1 Administering Non-Cacheable Memory Load Instructions 失效
标题翻译：管理不可缓存的内存加载指令
公开(公告)号：US20090287885A1
公开(公告)日：2009-11-19
申请号：US12121222
申请日：2008-05-15
申请人： Jon K. Kriegel , Jamie R. Kuesel
发明人： Jon K. Kriegel , Jamie R. Kuesel
IPC分类号： G06F12/08
CPC分类号： G06F12/0804 , G06F9/30043 , G06F9/3824 , G06F12/0837 , G06F12/0897
摘要： Administering non-cacheable memory load instructions in a computing environment where cacheable data is produced and consumed in a coherent manner without harming performance of a producer, the environment including a hierarchy of computer memory that includes one or more caches backed by main memory, the caches controlled by a cache controller, at least one of the caches configured as a write-back cache. Embodiments of the present invention include receiving, by the cache controller, a non-cacheable memory load instruction for data stored at a memory address, the data treated by the producer as cacheable; determining by the cache controller from a cache directory whether the data is cached; if the data is cached, returning the data in the memory address from the write-back cache without affecting the write-back cache's state; and if the data is not cached, returning the data from main memory without affecting the write-back cache's state.
摘要翻译：在计算环境中管理不可缓存的存储器加载指令，其中以一致的方式产生和消耗可缓存数据，而不损害生产者的性能，该环境包括计算机存储器的层次结构，其包括由主存储器支持的一个或多个缓存，高速缓存由缓存控制器控制，配置为回写高速缓存的至少一个高速缓存。本发明的实施例包括由高速缓存控制器接收存储在存储器地址中的数据的不可缓存的存储器加载指令，由生产者处理的数据可缓存; 由缓存控制器从高速缓存目录确定数据是否被高速缓存; 如果数据被缓存，则从写回缓存返回存储器地址中的数据，而不影响回写缓存的状态; 并且如果数据没有缓存，则从主存储器返回数据，而不会影响回写缓存的状态。

15. 发明申请

US20090210883A1 Network On Chip Low Latency, High Bandwidth Application Messaging Interconnect 有权
标题翻译：网络片上低延迟，高带宽应用程序消息传递互连
公开(公告)号：US20090210883A1
公开(公告)日：2009-08-20
申请号：US12031738
申请日：2008-02-15
申请人： Russell D. Hoover , Jon K. Kriegel , Eric O. Mejdrich , Robert A. Shearer
发明人： Russell D. Hoover , Jon K. Kriegel , Eric O. Mejdrich , Robert A. Shearer
IPC分类号： G06F9/54
CPC分类号： G06F15/7825
摘要： Data processing on a network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, with each IP block adapted to a router through a memory communications controller and a network interface controller, where each memory communications controller controlling communications between an IP block and memory, each network interface controller controlling inter-IP block communications through routers, with each IP block also adapted to the network by a low latency, high bandwidth application messaging interconnect comprising an inbox and an outbox.
摘要翻译：包括集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器的片上网络（“NOC”）上的数据处理，每个IP块通过存储器通信控制器和网络适配于路由器接口控制器，其中每个存储器通信控制器控制IP块和存储器之间的通信，每个网络接口控制器控制通过路由器的IP间块通信，每个IP块还通过低延迟的高带宽应用消息传送互连来适应于网络，包括收件箱和发件箱。

16. 发明授权

US07577794B2 Low latency coherency protocol for a multi-chip multiprocessor system 失效
标题翻译：用于多芯片多处理器系统的低延迟一致性协议
公开(公告)号：US07577794B2
公开(公告)日：2009-08-18
申请号：US10961751
申请日：2004-10-08
申请人： Bruce L. Beukema , Russell D. Hoover , Jon K. Kriegel , Eric O. Mejdrich , Sandra S. Woodward
发明人： Bruce L. Beukema , Russell D. Hoover , Jon K. Kriegel , Eric O. Mejdrich , Sandra S. Woodward
IPC分类号： G06F12/00
CPC分类号： G06F12/0828
摘要： Methods and apparatus for reducing the amount of latency involved when accessing, by a remote device, data residing in a cache of a processor are provided. For some embodiments, virtual channels may be utilized to conduct request/response transactions between the remote device and processor that satisfy a set of associated coherency rules.
摘要翻译：提供了用于减少由远程设备访问驻留在处理器的高速缓存中的数据所涉及的等待时间量的方法和装置。对于一些实施例，虚拟信道可以用于在满足一组相关联的一致性规则的远程设备和处理器之间进行请求/响应事务。

17. 发明授权

US08856490B2 Optimizing TLB entries for mixed page size storage in contiguous memory 有权
标题翻译：优化连续内存中混合页大小存储的TLB条目
公开(公告)号：US08856490B2
公开(公告)日：2014-10-07
申请号：US13618730
申请日：2012-09-14
申请人： Dong Chen , Alan Gara , Mark E. Giampapa , Philip Heidelberger , Jon K. Kriegel , Martin Ohmacht , Burkhard Steinmacher-Burow
发明人： Dong Chen , Alan Gara , Mark E. Giampapa , Philip Heidelberger , Jon K. Kriegel , Martin Ohmacht , Burkhard Steinmacher-Burow
IPC分类号： G06F12/06 , G06F12/10
CPC分类号： G06F12/1027 , G06F2212/652 , G06F2212/654
摘要： A system and method for accessing memory are provided. The system comprises a lookup buffer for storing one or more page table entries, wherein each of the one or more page table entries comprises at least a virtual page number and a physical page number; a logic circuit for receiving a virtual address from said processor, said logic circuit for matching the virtual address to the virtual page number in one of the page table entries to select the physical page number in the same page table entry, said page table entry having one or more bits set to exclude a memory range from a page.
摘要翻译：提供了一种访问存储器的系统和方法。该系统包括用于存储一个或多个页表条目的查找缓冲器，其中所述一个或多个页表条目中的每一个包括至少虚拟页码和物理页号; 用于从所述处理器接收虚拟地址的逻辑电路，所述逻辑电路用于将所述虚拟地址与所述页表项之一中的虚拟页号进行匹配，以选择所述同一页表项中的所述物理页号，所述页表项具有一个或多个位被设置为从页面排除存储器范围。

18. 发明申请

US20110173411A1 TLB EXCLUSION RANGE 有权
标题翻译： TLB排除范围
公开(公告)号：US20110173411A1
公开(公告)日：2011-07-14
申请号：US12684642
申请日：2010-01-08
申请人： Dong Chen , Alan Gara , Mark E. Giampapa , Philip Heidelberger , Jon K. Kriegel , Martin Ohmacht , Burkhard Steinmacher-Burow
发明人： Dong Chen , Alan Gara , Mark E. Giampapa , Philip Heidelberger , Jon K. Kriegel , Martin Ohmacht , Burkhard Steinmacher-Burow
IPC分类号： G06F12/10 , G06F12/00 , G06F12/08
CPC分类号： G06F12/1027 , G06F2212/652 , G06F2212/654
摘要： A system and method for accessing memory are provided. The system comprises a lookup buffer for storing one or more page table entries, wherein each of the one or more page table entries comprises at least a virtual page number and a physical page number; a logic circuit for receiving a virtual address from said processor, said logic circuit for matching the virtual address to the virtual page number in one of the page table entries to select the physical page number in the same page table entry, said page table entry having one or more bits set to exclude a memory range from a page.
摘要翻译：提供了一种访问存储器的系统和方法。该系统包括用于存储一个或多个页表条目的查找缓冲器，其中所述一个或多个页表条目中的每一个包括至少虚拟页码和物理页号; 用于从所述处理器接收虚拟地址的逻辑电路，所述逻辑电路用于将所述虚拟地址与所述页表项之一中的虚拟页号进行匹配，以选择所述同一页表项中的所述物理页号，所述页表项具有一个或多个位被设置为从页面排除存储器范围。

19. 发明授权

US07681020B2 Context switching and synchronization 失效
标题翻译：上下文切换和同步
公开(公告)号：US07681020B2
公开(公告)日：2010-03-16
申请号：US11736936
申请日：2007-04-18
申请人： Jon K. Kriegel , Eric Oliver Mejdrich
发明人： Jon K. Kriegel , Eric Oliver Mejdrich
IPC分类号： G06F9/00
CPC分类号： G06F9/4812 , G06F9/461 , G06F9/463 , G06F9/5016 , G06F9/5027 , G06F12/0837 , G06F12/0842 , G06F12/1054 , G06F12/126 , G06F2209/481 , G06F2209/5018
摘要： A method, computer-readable medium, and apparatus for context switching between a first thread and a second thread. The method includes detecting an exception, wherein the exception is generated in response to receiving a packet of information directed to one of the first thread and the second thread, and in response to detecting the exception, invoking an exception handler. The exception handler is configured to execute one or more instructions removing access to at least a portion of a processor cache. The portion of the processor cache contains cached information for the first thread using a first address translation. Removing access to the portion of the processor cache prevents the second thread using a second address translation from accessing the cached information in the processor cache. The exception handler is also configured to branch to at least one of the first thread and the second thread.
摘要翻译：一种用于第一线程和第二线程之间的上下文切换的方法，计算机可读介质和装置。该方法包括检测异常，其中响应于接收到针对第一线程和第二线程之一的信息的分组而产生异常，并且响应于检测到该异常，调用异常处理程序。异常处理程序被配置为执行一个或多个指令，以移除对处理器高速缓存的至少一部分的访问。处理器缓存的部分包含使用第一个地址转换的第一个线程的缓存信息。去除对处理器高速缓存部分的访问阻止使用第二地址转换的第二线程访问处理器高速缓存中的缓存信息。异常处理程序还被配置为分支到第一线程和第二线程中的至少一个。

20. 发明申请

US20090049272A1 METHOD FOR IMPROVING THE PERFORMANCE OF SOFTWARE-MANAGED TLB 审中-公开
标题翻译：改进软件管理TLB性能的方法
公开(公告)号：US20090049272A1
公开(公告)日：2009-02-19
申请号：US11837929
申请日：2007-08-13
申请人： Jose R. Brunheroto , Jon K. Kriegel , Edi Shmueli
发明人： Jose R. Brunheroto , Jon K. Kriegel , Edi Shmueli
IPC分类号： G06F9/34
CPC分类号： G06F12/121 , G06F12/1027 , G06F12/123 , G06F2212/1021 , G06F2212/684
摘要： Exemplary embodiments of the present invention comprise a method for the utilization of entry-replacement index hint information within a software-managed TLB. The method comprises receiving an address translation request at a TLB and retrieving the address translation information from a page table in the event of a miss lookup event at the TLB. The method further comprises retrieving index replacement hint information from a hardware component, wherein the hardware component is configured to execute a predetermined replacement algorithm and writing the address translation information to a TLB index referenced within the index replacement hint information.
摘要翻译：本发明的示例性实施例包括一种在软件管理的TLB内利用入口替换索引提示信息的方法。该方法包括在TLB处接收地址转换请求并在TLB发生未命中查找事件的情况下从页表中检索地址转换信息。该方法还包括从硬件组件检索索引替换提示信息，其中硬件组件被配置为执行预定的替换算法，并将地址转换信息写入到在索引替换提示信息中引用的TLB索引。

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