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1. 发明申请

US20090287885A1 Administering Non-Cacheable Memory Load Instructions 失效
标题翻译：管理不可缓存的内存加载指令
公开(公告)号：US20090287885A1
公开(公告)日：2009-11-19
申请号：US12121222
申请日：2008-05-15
申请人： Jon K. Kriegel , Jamie R. Kuesel
发明人： Jon K. Kriegel , Jamie R. Kuesel
IPC分类号： G06F12/08
CPC分类号： G06F12/0804 , G06F9/30043 , G06F9/3824 , G06F12/0837 , G06F12/0897
摘要： Administering non-cacheable memory load instructions in a computing environment where cacheable data is produced and consumed in a coherent manner without harming performance of a producer, the environment including a hierarchy of computer memory that includes one or more caches backed by main memory, the caches controlled by a cache controller, at least one of the caches configured as a write-back cache. Embodiments of the present invention include receiving, by the cache controller, a non-cacheable memory load instruction for data stored at a memory address, the data treated by the producer as cacheable; determining by the cache controller from a cache directory whether the data is cached; if the data is cached, returning the data in the memory address from the write-back cache without affecting the write-back cache's state; and if the data is not cached, returning the data from main memory without affecting the write-back cache's state.
摘要翻译：在计算环境中管理不可缓存的存储器加载指令，其中以一致的方式产生和消耗可缓存数据，而不损害生产者的性能，该环境包括计算机存储器的层次结构，其包括由主存储器支持的一个或多个缓存，高速缓存由缓存控制器控制，配置为回写高速缓存的至少一个高速缓存。本发明的实施例包括由高速缓存控制器接收存储在存储器地址中的数据的不可缓存的存储器加载指令，由生产者处理的数据可缓存; 由缓存控制器从高速缓存目录确定数据是否被高速缓存; 如果数据被缓存，则从写回缓存返回存储器地址中的数据，而不影响回写缓存的状态; 并且如果数据没有缓存，则从主存储器返回数据，而不会影响回写缓存的状态。

2. 发明申请

US20120215988A1 Administering Non-Cacheable Memory Load Instructions 审中-公开
标题翻译：管理不可缓存的内存加载指令
公开(公告)号：US20120215988A1
公开(公告)日：2012-08-23
申请号：US13461913
申请日：2012-05-02
申请人： Jon K. Kriegel , Jamie R. Kuesel
发明人： Jon K. Kriegel , Jamie R. Kuesel
IPC分类号： G06F12/08
CPC分类号： G06F12/0804 , G06F9/30043 , G06F9/30185 , G06F9/3824 , G06F12/0837 , G06F12/0897
摘要： Administering non-cacheable memory load instructions in a computing environment where cacheable data is produced and consumed in a coherent manner without harming performance of a producer, the environment including a hierarchy of computer memory that includes one or more caches backed by main memory, the caches controlled by a cache controller, at least one of the caches configured as a write-back cache. Embodiments of the present invention include receiving, by the cache controller, a non-cacheable memory load instruction for data stored at a memory address, the data treated by the producer as cacheable; determining by the cache controller from a cache directory whether the data is cached; if the data is cached, returning the data in the memory address from the write-back cache without affecting the write-back cache's state; and if the data is not cached, returning the data from main memory without affecting the write-back cache's state.
摘要翻译：在计算环境中管理不可缓存的存储器加载指令，其中以一致的方式产生和消耗可缓存数据，而不损害生产者的性能，该环境包括计算机存储器的层次结构，其包括由主存储器支持的一个或多个缓存，高速缓存由缓存控制器控制，配置为回写高速缓存的至少一个高速缓存。本发明的实施例包括由高速缓存控制器接收存储在存储器地址中的数据的不可缓存的存储器加载指令，由生产者处理的数据可缓存; 由缓存控制器从高速缓存目录确定数据是否被高速缓存; 如果数据被缓存，则从写回缓存返回存储器地址中的数据，而不影响回写缓存的状态; 并且如果数据没有缓存，则从主存储器返回数据，而不会影响回写缓存的状态。

3. 发明授权

US08230179B2 Administering non-cacheable memory load instructions 失效
标题翻译：管理不可缓存的内存加载指令
公开(公告)号：US08230179B2
公开(公告)日：2012-07-24
申请号：US12121222
申请日：2008-05-15
申请人： Jon K. Kriegel , Jamie R. Kuesel
发明人： Jon K. Kriegel , Jamie R. Kuesel
IPC分类号： G06F9/00
CPC分类号： G06F12/0804 , G06F9/30043 , G06F9/3824 , G06F12/0837 , G06F12/0897
摘要： Administering non-cacheable memory load instructions in a computing environment where cacheable data is produced and consumed in a coherent manner without harming performance of a producer, the environment including a hierarchy of computer memory that includes one or more caches backed by main memory, the caches controlled by a cache controller, at least one of the caches configured as a write-back cache. Embodiments of the present invention include receiving, by the cache controller, a non-cacheable memory load instruction for data stored at a memory address, the data treated by the producer as cacheable; determining by the cache controller from a cache directory whether the data is cached; if the data is cached, returning the data in the memory address from the write-back cache without affecting the write-back cache's state; and if the data is not cached, returning the data from main memory without affecting the write-back cache's state.
摘要翻译：在计算环境中管理不可缓存的存储器加载指令，其中以一致的方式产生和消耗可缓存数据，而不损害生产者的性能，该环境包括计算机存储器的层次结构，其包括由主存储器支持的一个或多个缓存，高速缓存由缓存控制器控制，配置为回写高速缓存的至少一个高速缓存。本发明的实施例包括由高速缓存控制器接收存储在存储器地址中的数据的不可缓存的存储器加载指令，由生产者处理的数据可缓存; 由缓存控制器从高速缓存目录确定数据是否被高速缓存; 如果数据被缓存，则从写回缓存返回存储器地址中的数据，而不影响回写缓存的状态; 并且如果数据没有缓存，则从主存储器返回数据，而不会影响回写缓存的状态。

4. 发明授权

US07840757B2 Method and apparatus for providing high speed memory for a processing unit 有权
标题翻译：用于为处理单元提供高速存储器的方法和装置
公开(公告)号：US07840757B2
公开(公告)日：2010-11-23
申请号：US10901600
申请日：2004-07-29
申请人： Bruce L. Beukema , Russell D. Hoover , Jon K. Kriegel , Jamie R. Kuesel , Eric O. Mejdrich , Robert A. Shearer , Bruce M. Walk
发明人： Bruce L. Beukema , Russell D. Hoover , Jon K. Kriegel , Jamie R. Kuesel , Eric O. Mejdrich , Robert A. Shearer , Bruce M. Walk
IPC分类号： G06F12/00
CPC分类号： G06F12/0888
摘要： Computer systems with direct updating of cache (e.g., primary L1 cache) memories of a processor, such as a central processing unit (CPU) or graphics processing unit (GPU). Special addresses are reserved for high speed memory. Memory access requests involving these reserved addresses are routed directly to the high speed memory. Memory access requests not involving these reserved addresses are routed to memory external to the processor.
摘要翻译：具有直接更新诸如中央处理单元（CPU）或图形处理单元（GPU）的处理器的高速缓存（例如，主要L1高速缓存）存储器的计算机系统。专用地址保留给高速存储器。涉及这些保留地址的存储器访问请求直接路由到高速存储器。不涉及这些保留地址的存储器访问请求被路由到处理器外部的存储器。

5. 发明授权

US07752413B2 Method and apparatus for communicating between threads 有权
标题翻译：用于在线程之间进行通信的方法和装置
公开(公告)号：US07752413B2
公开(公告)日：2010-07-06
申请号：US11567882
申请日：2006-12-07
申请人： Russell Dean Hoover , Jon K. Kriegel , Eric Oliver Mejdrich , Robert Allen Shearer
发明人： Russell Dean Hoover , Jon K. Kriegel , Eric Oliver Mejdrich , Robert Allen Shearer
IPC分类号： G06F12/00
CPC分类号： G06T15/50 , G06T15/06
摘要： A method and apparatus for communicating between threads in a processor. The method includes reserving a first portion of a cache in a processor for an inbox. The inbox is associated with a first thread being executed by the processor. The method also includes receiving a packet from a second thread, wherein the packet includes an access request. The method further includes using inbox control circuitry for the inbox to process the received packet and determine whether to grant the access request included in the packet.
摘要翻译：一种用于在处理器中的线程之间进行通信的方法和装置。该方法包括在收件箱的处理器中预留高速缓存的第一部分。收件箱与由处理器执行的第一个线程相关联。该方法还包括从第二线程接收分组，其中分组包括接入请求。该方法还包括使用收件箱控制电路来收件箱来处理接收到的分组并且确定是否授予包含在分组中的接入请求。

6. 发明申请

US20090307714A1 NETWORK ON CHIP WITH AN I/O ACCELERATOR 失效
标题翻译：使用I / O加速器的芯片上的网络
公开(公告)号：US20090307714A1
公开(公告)日：2009-12-10
申请号：US12135364
申请日：2008-06-09
申请人： Russell D. Hoover , Jon K. Kriegel , Eric O. Mejdrich
发明人： Russell D. Hoover , Jon K. Kriegel , Eric O. Mejdrich
IPC分类号： G06F9/54
CPC分类号： G06F9/546 , G06F15/7825 , H04L45/00
摘要： Data processing on a network on chip (‘NOC’) that includes IP blocks, routers, memory communications controllers, and network interface controllers; each IP block adapted to a router through a memory communications controller and a network interface controller; each memory communications controller controlling communication between an IP block and memory; each network interface controller controlling inter-IP block communications through routers; each IP block adapted to the network by a low latency, high bandwidth application messaging interconnect comprising an inbox and an outbox; a computer software application segmented into stages, each stage comprising a flexibly configurable module of computer program instructions identified by a stage ID with each stage executing on a thread of execution on an IP block; and at least one of the IP blocks comprising an input/output (‘I/O’) accelerator that administers at least some data communications traffic to and from the at least one IP block.
摘要翻译：芯片上的数据处理（“NOC”）包括IP块，路由器，存储器通信控制器和网络接口控制器; 每个IP块通过存储器通信控制器和网络接口控制器适应于路由器; 每个存储器通信控制器控制IP块和存储器之间的通信; 每个网络接口控制器通过路由器控制IP间块通信; 每个IP块通过包括收件箱和发件箱的低延迟，高带宽应用消息互连来适应于网络; 每个阶段包括由阶段ID标识的计算机程序指令的灵活可配置模块，每个阶段在IP块上的执行线程上执行; 并且所述IP块中的至少一个包括向所述至少一个IP块执行至少一些数据通信业务的输入/输出（'I / O'）加速器。

7. 发明申请

US20090210592A1 Network On Chip With A Low Latency, High Bandwidth Application Messaging Interconnect 有权
标题翻译：网络片上低延迟，高带宽应用程序消息传递互连
公开(公告)号：US20090210592A1
公开(公告)日：2009-08-20
申请号：US12031733
申请日：2008-02-15
申请人： Russell D. Hoover , Jon K. Kriegel , Eric O. Mejdrich
发明人： Russell D. Hoover , Jon K. Kriegel , Eric O. Mejdrich
IPC分类号： G06F13/42 , G06F13/38
CPC分类号： G06F13/4027
摘要： A network on chip (‘NOC’) and methods of data processing on the NOC, the NOC including integrated processor (‘IP’) blocks, a data communications bus (110), memory communications controllers (106), and bus interface controllers (108); each IP block adapted to the data communications bus through a memory communications controller and a bus interface controller; each memory communications controller, in conjunction with one of the bus interface controllers, controlling memory addressed communications between an IP block and memory; each memory communications controller, in conjunction with one of the bus interface controllers, controlling memory addressed communications between one of the IP blocks and other IP blocks; each IP block adapted to the data communications bus by a low latency, high bandwidth application messaging interconnect comprising an inbox and an outbox.
摘要翻译：片上网络（NOC）和NOC数据处理方法，NOC包括集成处理器（IP）块，数据通信总线（110），存储器通信控制器（106）和总线接口控制器 108）; 每个IP块通过存储器通信控制器和总线接口控制器适应于数据通信总线; 每个存储器通信控制器与一个总线接口控制器一起控制IP块和存储器之间的存储器寻址通信; 每个存储器通信控制器与一个总线接口控制器一起控制IP块和其它IP块之一之间的存储器寻址通信; 每个IP块通过包括收件箱和发件箱的低延迟，高带宽应用消息互连来适应数据通信总线。

8. 发明授权

US07089341B2 Method and apparatus for supporting interrupt devices configured for a particular architecture on a different platform 失效
标题翻译：用于支持在不同平台上为特定架构配置的中断装置的方法和装置
公开(公告)号：US07089341B2
公开(公告)日：2006-08-08
申请号：US10815247
申请日：2004-03-31
申请人： Jon K. Kriegel
发明人： Jon K. Kriegel
IPC分类号： G06F13/24 , G06F3/00
CPC分类号： G06F13/24
摘要： Method and apparatus for supporting interrupt devices configured for a specific architecture (e.g., APIC-based software and hardware) on a different platform (e.g., a PowerPC platform). One embodiment provides an apparatus for passing interrupts from one or more devices configured for a specific interrupt architecture to one or more processors not designed for the specific interrupt architecture, comprising: an abstraction layer comprising a first plurality of registers conforming to the specific interrupt architecture; and an implementation dependent layer, disposed in communication between the abstraction layer and the one or more processors, comprising a second plurality of registers which correspond to the first plurality of registers, wherein the implementation dependent layer is configured to receive interrupts and forward received interrupts to the one or more processors and to read and write data to the second plurality of registers in response to interrupts processed through the one or more processor.
摘要翻译：用于支持在不同平台（例如，PowerPC平台）上为特定架构（例如，基于APIC的软件和硬件）配置的中断设备的方法和装置。一个实施例提供了一种用于将针对特定中断架构配置的一个或多个设备的中断的中断传送到不为特定中断体系结构设计的一个或多个处理器的装置，包括：抽象层，包括符合特定中断架构的第一多个寄存器; 以及设置在所述抽象层和所述一个或多个处理器之间的通信中的实现依赖层，包括对应于所述第一多个寄存器的第二多个寄存器，其中所述实现相关层被配置为接收中断并将接收的中断转发到所述一个或多个处理器并且响应于通过所述一个或多个处理器处理的中断而将数据读取和写入到所述第二多个寄存器。

9. 发明授权

US08438578B2 Network on chip with an I/O accelerator 失效
标题翻译：使用I / O加速器的网络芯片
公开(公告)号：US08438578B2
公开(公告)日：2013-05-07
申请号：US12135364
申请日：2008-06-09
申请人： Russell D. Hoover , Jon K. Kriegel , Eric O. Mejdrich
发明人： Russell D. Hoover , Jon K. Kriegel , Eric O. Mejdrich
IPC分类号： G06F3/00 , G06F9/44 , G06F9/46 , G06F13/00 , G06F15/00
CPC分类号： G06F9/546 , G06F15/7825 , H04L45/00
摘要： Data processing on a network on chip (‘NOC’) that includes IP blocks, routers, memory communications controllers, and network interface controllers; each IP block adapted to a router through a memory communications controller and a network interface controller; each memory communications controller controlling communication between an IP block and memory; each network interface controller controlling inter-IP block communications through routers; each IP block adapted to the network by a low latency, high bandwidth application messaging interconnect comprising an inbox and an outbox; a computer software application segmented into stages, each stage comprising a flexibly configurable module of computer program instructions identified by a stage ID with each stage executing on a thread of execution on an IP block; and at least one of the IP blocks comprising an input/output (‘I/O’) accelerator that administers at least some data communications traffic to and from the at least one IP block.
摘要翻译：芯片上的数据处理（“NOC”）包括IP块，路由器，存储器通信控制器和网络接口控制器; 每个IP块通过存储器通信控制器和网络接口控制器适应于路由器; 每个存储器通信控制器控制IP块和存储器之间的通信; 每个网络接口控制器通过路由器控制IP间块通信; 每个IP块通过包括收件箱和发件箱的低延迟，高带宽应用消息互连来适应于网络; 每个阶段包括由阶段ID标识的计算机程序指令的灵活可配置模块，每个阶段在IP块上的执行线程上执行; 并且所述IP块中的至少一个包括对至少一个IP块执行至少一些数据通信业务的输入/输出（“I / O”）加速器。

10. 发明授权

US08429377B2 Optimizing TLB entries for mixed page size storage in contiguous memory 有权
标题翻译：优化连续内存中混合页大小存储的TLB条目
公开(公告)号：US08429377B2
公开(公告)日：2013-04-23
申请号：US12684642
申请日：2010-01-08
申请人： Dong Chen , Alan Gara , Mark E. Giampapa , Philip Heidelberger , Jon K. Kriegel , Martin Ohmacht , Burkhard Steinmacher-Burow
发明人： Dong Chen , Alan Gara , Mark E. Giampapa , Philip Heidelberger , Jon K. Kriegel , Martin Ohmacht , Burkhard Steinmacher-Burow
IPC分类号： G06F12/06
CPC分类号： G06F12/1027 , G06F2212/652 , G06F2212/654
摘要： A system and method for accessing memory are provided. The system comprises a lookup buffer for storing one or more page table entries, wherein each of the one or more page table entries comprises at least a virtual page number and a physical page number; a logic circuit for receiving a virtual address from said processor, said logic circuit for matching the virtual address to the virtual page number in one of the page table entries to select the physical page number in the same page table entry, said page table entry having one or more bits set to exclude a memory range from a page.
摘要翻译：提供了一种访问存储器的系统和方法。该系统包括用于存储一个或多个页表条目的查找缓冲器，其中所述一个或多个页表条目中的每一个包括至少虚拟页码和物理页号; 用于从所述处理器接收虚拟地址的逻辑电路，所述逻辑电路用于将所述虚拟地址与所述页表项之一中的虚拟页号进行匹配，以选择所述同一页表项中的所述物理页号，所述页表项具有一个或多个位被设置为从页面排除存储器范围。

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