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11. 发明申请

US20060121664A1 Method for forming self-aligned dual salicide in CMOS technologies 失效
公开(公告)号：US20060121664A1
公开(公告)日：2006-06-08
申请号：US11254929
申请日：2005-10-20
申请人： Sunfei Fang , Cyril Cabral , Chester Dziobkowski , John Ellis-Monaghan , Christian Lavoie , Zhijiong Luo , James Nakos , An Steegen , Clement Wann
发明人： Sunfei Fang , Cyril Cabral , Chester Dziobkowski , John Ellis-Monaghan , Christian Lavoie , Zhijiong Luo , James Nakos , An Steegen , Clement Wann
IPC分类号： H01L21/8238 , H01L21/3205 , H01L21/44
CPC分类号： H01L21/28518 , H01L21/823814 , H01L21/823835
摘要： A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region in a semiconductor substrate for accommodation of a first type semiconductor device; forming a second well region in the semiconductor substrate for accommodation of a second type semiconductor device; shielding the first type semiconductor device with a mask; depositing a first metal layer over the second type semiconductor device; performing a first salicide formation on the second type semiconductor device; removing the mask; depositing a second metal layer over the first and second type semiconductor devices; and performing a second salicide formation on the first type semiconductor device. The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different silicide material over different devices.

12. 发明授权

US08039331B2 Opto-thermal annealing methods for forming metal gate and fully silicided gate-field effect transistors 有权
标题翻译：用于形成金属栅极和全硅化栅场效应晶体管的光热退火方法
公开(公告)号：US08039331B2
公开(公告)日：2011-10-18
申请号：US12120286
申请日：2008-05-14
申请人： Scott D. Allen , Cyril Cabral, Jr. , Kevin K. Dezfulian , Sunfei Fang , Brian J. Greene , Rajarao Jammy , Christian Lavoie , Zhijiong Luo , Hung Ng , Chun-Yung Sung , Clement H. Wann , Huilong Zhu
发明人： Scott D. Allen , Cyril Cabral, Jr. , Kevin K. Dezfulian , Sunfei Fang , Brian J. Greene , Rajarao Jammy , Christian Lavoie , Zhijiong Luo , Hung Ng , Chun-Yung Sung , Clement H. Wann , Huilong Zhu
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L21/268 , H01L21/2686 , H01L21/28079 , H01L21/28088 , H01L21/28097 , H01L21/28176 , H01L21/324 , H01L29/517 , H01L29/665
摘要： An opto-thermal annealing method for forming a field effect transistor uses a reflective metal gate so that electrical properties of the metal gate and also interface between the metal gate and a gate dielectric are not compromised when opto-thermal annealing a source/drain region adjacent the metal gate. Another opto-thermal annealing method may be used for simultaneously opto-thermally annealing: (1) a silicon layer and a silicide forming metal layer to form a fully silicided gate; and (2) a source/drain region to form an annealed source/drain region. An additional opto-thermal annealing method may use a thermal insulator layer in conjunction with a thermal absorber layer to selectively opto-thermally anneal a silicon layer and a silicide forming metal layer to form a fully silicide gate.
摘要翻译：用于形成场效应晶体管的光热退火方法使用反射金属栅极，使得当相邻的源极/漏极区域进行光热退火时，金属栅极的电特性以及金属栅极和栅极电介质之间的界面不受损害金属门。另一种光热退火方法可以用于同时光热退火：（1）硅层和形成硅化物的金属层以形成完全硅化的栅极; 和（2）源/漏区以形成退火的源/漏区。附加的光热退火方法可以使用与热吸收层结合的热绝缘体层来选择性地使硅层和形成硅化物的金属层光退火以形成完全硅化物栅极。

13. 发明申请

US20070249131A1 Opto-thermal annealing methods for forming metal gate and fully silicided gate field effect transistors 有权
标题翻译：用于形成金属栅极和全硅化栅场效应晶体管的光热退火方法
公开(公告)号：US20070249131A1
公开(公告)日：2007-10-25
申请号：US11408522
申请日：2006-04-21
申请人： Scott Allen , Cyril Cabral , Kevin Dezfulian , Sunfei Fang , Brian Greene , Rajarao Jammy , Christian Lavoie , Zhijiong Luo , Hung Ng , Chun-Yung Sung , Clement Wann , Huilong Zhu
发明人： Scott Allen , Cyril Cabral , Kevin Dezfulian , Sunfei Fang , Brian Greene , Rajarao Jammy , Christian Lavoie , Zhijiong Luo , Hung Ng , Chun-Yung Sung , Clement Wann , Huilong Zhu
IPC分类号： H01L21/336 , H01L21/44
CPC分类号： H01L21/268 , H01L21/2686 , H01L21/28079 , H01L21/28088 , H01L21/28097 , H01L21/28176 , H01L21/324 , H01L29/517 , H01L29/665
摘要： An opto-thermal annealing method for forming a field effect transistor uses a reflective metal gate so that electrical properties of the metal gate and also interface between the metal gate and a gate dielectric are not compromised when opto-thermal annealing a source/drain region adjacent the metal gate. Another opto-thermal annealing method may be used for simultaneously opto-thermally annealing: (1) a silicon layer and a silicide forming metal layer to form a fully silicided gate; and (2) a source/drain region to form an annealed source/drain region. An additional opto-thermal annealing method may use a thermal insulator layer in conjunction with a thermal absorber layer to selectively opto-thermally anneal a silicon layer and a silicide forming metal layer to form a fully silicide gate.
摘要翻译：用于形成场效应晶体管的光热退火方法使用反射金属栅极，使得当相邻的源极/漏极区域进行光热退火时，金属栅极的电特性以及金属栅极和栅极电介质之间的界面不受损害金属门。另一种光热退火方法可以用于同时光热退火：（1）硅层和形成硅化物的金属层以形成完全硅化的栅极; 和（2）源/漏区以形成退火的源/漏区。附加的光热退火方法可以使用与热吸收层结合的热绝缘体层来选择性地使硅层和形成硅化物的金属层光退火以形成完全硅化物栅极。

14. 发明授权

US07122472B2 Method for forming self-aligned dual fully silicided gates in CMOS devices 失效
标题翻译：在CMOS器件中形成自对准双完全硅化栅的方法
公开(公告)号：US07122472B2
公开(公告)日：2006-10-17
申请号：US10904885
申请日：2004-12-02
申请人： Sunfei Fang , Cyril Cabral, Jr. , Chester T. Dziobkowski , Christian Lavoie , Clement H. Wann
发明人： Sunfei Fang , Cyril Cabral, Jr. , Chester T. Dziobkowski , Christian Lavoie , Clement H. Wann
IPC分类号： H01L21/44
CPC分类号： H01L21/823835
摘要： A method of forming a dual self-aligned fully silicided gate in a CMOS device requiring only one lithography level, wherein the method comprises forming a first type semiconductor device having a first well region in a semiconductor substrate, first source/drain silicide areas in the first well region, and a first type gate isolated from the first source/drain silicide areas; forming a second type semiconductor device having a second well region in the semiconductor substrate, second source/drain silicide areas in the second well region, and a second type gate isolated from the second source/drain silicide areas; selectively forming a first metal layer over the second type semiconductor device; performing a first fully silicided (FUSI) gate formation on only the second type gate; depositing a second metal layer over the first and second type semiconductor devices; and performing a second FUSI gate formation on only the first type gate.
摘要翻译：一种在仅需要一个光刻级别的CMOS器件中形成双自对准全硅化栅的方法，其中所述方法包括在半导体衬底中形成具有第一阱区的第一类型半导体器件，其中第一源极/漏极硅化物区域第一阱区域和从第一源极/漏极硅化物区域隔离的第一类型栅极; 形成在所述半导体衬底中具有第二阱区域的第二类型半导体器件，所述第二阱区域中的第二源极/漏极硅化物区域和与所述第二源极/漏极硅化物区域隔离的第二类型栅极; 在所述第二类型半导体器件上选择性地形成第一金属层; 仅在第二型栅极上执行第一完全硅化（FUSI）栅极形成; 在所述第一和第二类型半导体器件上沉积第二金属层; 以及仅在第一类型栅极上执行第二FUSI栅极形成。

15. 发明申请

US20060121665A1 METHOD FOR FORMING SELF-ALIGNED DUAL SALICIDE IN CMOS TECHNOLOGIES 有权
标题翻译：在CMOS技术中形成自对准双重杀菌剂的方法
公开(公告)号：US20060121665A1
公开(公告)日：2006-06-08
申请号：US11254934
申请日：2005-10-20
申请人： Sunfei Fang , Cyril Cabral , Chester Dziobkowski , John Ellis-Monaghan , Christian Lavoie , Zhijiong Luo , James Nakos , An Steegen , Clement Wann
发明人： Sunfei Fang , Cyril Cabral , Chester Dziobkowski , John Ellis-Monaghan , Christian Lavoie , Zhijiong Luo , James Nakos , An Steegen , Clement Wann
IPC分类号： H01L21/8238 , H01L21/44
CPC分类号： H01L21/28518 , H01L21/823814 , H01L21/823835
摘要： A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region in a semiconductor substrate for accommodation of a first type semiconductor device; forming a second well region in the semiconductor substrate for accommodation of a second type semiconductor device; shielding the first type semiconductor device with a mask; depositing a first metal layer over the second type semiconductor device; performing a first salicide formation on the second type semiconductor device; removing the mask; depositing a second metal layer over the first and second type semiconductor devices; and performing a second salicide formation on the first type semiconductor device. The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different silicide material over different devices.
摘要翻译：一种制造互补金属氧化物半导体（CMOS）器件的方法，其中所述方法包括在用于容纳第一类型半导体器件的半导体衬底中形成第一阱区; 在所述半导体衬底中形成用于容纳第二类型半导体器件的第二阱区; 用掩模屏蔽第一类型半导体器件; 在所述第二类型半导体器件上沉积第一金属层; 在所述第二类型半导体器件上执行第一自对准硅化物形成; 去除面膜; 在所述第一和第二类型半导体器件上沉积第二金属层; 以及在所述第一类型半导体器件上执行第二自对准硅化物形成。该方法仅需要一个图案级别，并且消除图案覆盖，因为它也简化了在不同设备上形成不同硅化物材料的工艺。

16. 发明申请

US20060121663A1 METHOD FOR FORMING SELF-ALIGNED DUAL FULLY SILICIDED GATES IN CMOS DEVICES 失效
标题翻译：在CMOS器件中形成自对准的双完全硅化物门的方法
公开(公告)号：US20060121663A1
公开(公告)日：2006-06-08
申请号：US10904885
申请日：2004-12-02
申请人： Sunfei Fang , Cyril Cabral , Chester Dziobkowski , Christian Lavoie , Clement Wann
发明人： Sunfei Fang , Cyril Cabral , Chester Dziobkowski , Christian Lavoie , Clement Wann
IPC分类号： H01L21/8238
CPC分类号： H01L21/823835
摘要： A method of forming a dual self-aligned fully silicided gate in a CMOS device requiring only one lithography level, wherein the method comprises forming a first type semiconductor device having a first well region in a semiconductor substrate, first source/drain silicide areas in the first well region, and a first type gate isolated from the first source/drain silicide areas; forming a second type semiconductor device having a second well region in the semiconductor substrate, second source/drain silicide areas in the second well region, and a second type gate isolated from the second source/drain silicide areas; selectively forming a first metal layer over the second type semiconductor device; performing a first fully silicided (FUSI) gate formation on only the second type gate; depositing a second metal layer over the first and second type semiconductor devices; and performing a second FUSI gate formation on only the first type gate.
摘要翻译：一种在仅需要一个光刻级别的CMOS器件中形成双自对准全硅化栅的方法，其中所述方法包括在半导体衬底中形成具有第一阱区的第一类型半导体器件，其中第一源极/漏极硅化物区域第一阱区域和从第一源极/漏极硅化物区域隔离的第一类型栅极; 形成在所述半导体衬底中具有第二阱区域的第二类型半导体器件，所述第二阱区域中的第二源极/漏极硅化物区域和与所述第二源极/漏极硅化物区域隔离的第二类型栅极; 在所述第二类型半导体器件上选择性地形成第一金属层; 仅在第二型栅极上执行第一完全硅化（FUSI）栅极形成; 在所述第一和第二类型半导体器件上沉积第二金属层; 以及仅在第一类型栅极上执行第二FUSI栅极形成。

17. 发明授权

US06916729B2 Salicide formation method 有权
标题翻译：自杀剂形成方法
公开(公告)号：US06916729B2
公开(公告)日：2005-07-12
申请号：US10409516
申请日：2003-04-08
申请人： Sunfei Fang , Keith Kwong Hon Wong , Paul D. Agnello , Christian Lavoie , Lawrence A. Clevenger , Chester T. Dziobkowski , Richard J. Murphy , Patrick W. DeHaven , Nivo Rovedo , Hsiang-Jen Huang
发明人： Sunfei Fang , Keith Kwong Hon Wong , Paul D. Agnello , Christian Lavoie , Lawrence A. Clevenger , Chester T. Dziobkowski , Richard J. Murphy , Patrick W. DeHaven , Nivo Rovedo , Hsiang-Jen Huang
IPC分类号： H01L21/28 , H01L21/283 , H01L21/285 , H01L21/3205 , H01L21/321 , H01L21/336 , H01L21/44 , H01L21/4763 , H01L21/8238 , H01L27/092 , H01L29/78
CPC分类号： H01L29/665 , H01L21/28052 , H01L21/28518
摘要： A method of forming a salicide on a semiconductor device includes depositing a first refractory metal layer over a silicon region of a substrate, depositing a near-noble metal layer over the first refractory metal layer, and depositing a second refractory metal layer over the near-noble metal layer. The semiconductor device is annealed in a first annealing process to form a silicide layer abutting the doped region of the semiconductor device. Un-reacted portions of the near-noble metal layer and the second refractory metal layer are removed. The device may be annealed in an optional second annealing process to convert the silicide layer to a low resistance phase silicide material. Junction leakage and bridging are minimized or eliminated by embodiments of the present invention, and a smoother silicided surface is achieved.
摘要翻译：在半导体器件上形成硅化物的方法包括在衬底的硅区域上沉积第一难熔金属层，在第一耐火金属层上沉积近贵金属层，以及在第二耐火金属层的近旁沉积第二难熔金属层，贵金属层。半导体器件在第一退火工艺中退火以形成邻接半导体器件的掺杂区域的硅化物层。除去近贵金属层和第二难熔金属层的未反应部分。该器件可以在任选的第二退火工艺中进行退火，以将硅化物层转换成低电阻相位硅化物材料。通过本发明的实施例使结漏电和桥接最小化或消除，并且实现更平滑的硅化表面。

18. 发明授权

US08445974B2 Asymmetric FET including sloped threshold voltage adjusting material layer and method of fabricating same 有权
标题翻译：包括倾斜阈值电压调节材料层的不对称FET及其制造方法
公开(公告)号：US08445974B2
公开(公告)日：2013-05-21
申请号：US12683602
申请日：2010-01-07
申请人： Dureseti Chidambarrao , Sunfei Fang , Yue Liang , Xiaojun Yu , Jun Yuan
发明人： Dureseti Chidambarrao , Sunfei Fang , Yue Liang , Xiaojun Yu , Jun Yuan
IPC分类号： H01L21/02
CPC分类号： H01L27/092 , H01L21/823857 , H01L29/42368 , H01L29/513 , H01L29/517 , H01L29/66545 , H01L29/66583 , H01L29/78
摘要： A semiconductor structure is provided that includes at least one asymmetric gate stack located on a surface of a semiconductor structure. The at least one asymmetric gate stack includes, from bottom to top, a high k gate dielectric, a sloped threshold voltage adjusting material layer and a gate conductor. A method of forming such a semiconductor structure is also provided in which a line of sight deposition process is used in forming the sloped threshold voltage adjusting material layer in which the deposition is tilted within respect to a horizontal surface of a semiconductor structure.
摘要翻译：提供一种半导体结构，其包括位于半导体结构的表面上的至少一个非对称栅极堆叠。所述至少一个非对称栅极堆叠包括从底部到顶部的高k栅极电介质，倾斜阈值电压调节材料层和栅极导体。还提供了一种形成这种半导体结构的方法，其中在形成相对于半导体结构的水平表面倾斜的沉积倾斜的阈值电压调节材料层中使用视线沉积工艺。

19. 发明授权

US07923365B2 Methods of forming field effect transistors having stress-inducing sidewall insulating spacers thereon 有权
标题翻译：在其上形成具有应力诱导侧壁绝缘间隔物的场效应晶体管的方法
公开(公告)号：US07923365B2
公开(公告)日：2011-04-12
申请号：US11874118
申请日：2007-10-17
申请人： Jun-jung Kim , Sang-jine Park , Min-ho Lee , Thomas W. Dyer , Sunfei Fang , O-sung Kwon , Johnny Widodo
发明人： Jun-jung Kim , Sang-jine Park , Min-ho Lee , Thomas W. Dyer , Sunfei Fang , O-sung Kwon , Johnny Widodo
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L29/7833 , H01L29/665 , H01L29/6653 , H01L29/7843
摘要： Methods of forming integrated circuit devices include forming a field effect transistor having a gate electrode, a sacrificial spacer on a sidewall of the gate electrode and silicided source/drain regions. The sacrificial spacer is used as an implantation mask when forming highly doped portions of the source/drain regions. The sacrificial spacer is then removed from the sidewall of the gate electrode. A stress-inducing electrically insulating layer, which is configured to induce a net tensile stress (for NMOS transistors) or compressive stress (for PMOS transistors) in a channel region of the field effect transistor, is then formed on the sidewall of the gate electrode.
摘要翻译：形成集成电路器件的方法包括形成具有栅电极的场效应晶体管，栅电极的侧壁上的牺牲隔离物和硅化源/漏区。当形成源极/漏极区域的高掺杂部分时，牺牲间隔物用作注入掩模。然后从栅电极的侧壁去除牺牲隔离物。然后，在栅电极的侧壁上形成应力诱导电绝缘层，其被配置为在场效应晶体管的沟道区域中引起净拉伸应力（用于NMOS晶体管）或压应力（用于PMOS晶体管）。

20. 发明授权

US07863693B2 Forming conductive stud for semiconductive devices 有权
标题翻译：形成用于半导体器件的导电螺柱
公开(公告)号：US07863693B2
公开(公告)日：2011-01-04
申请号：US12013622
申请日：2008-01-14
申请人： Thomas W. Dyer , Sunfei Fang , Jiang Yan
发明人： Thomas W. Dyer , Sunfei Fang , Jiang Yan
IPC分类号： H01L21/02
CPC分类号： H01L21/823871 , H01L21/76895 , H01L21/76897 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/6659 , H01L29/7843
摘要： Embodiments of the present invention provide a method of forming a conductive stud contacting a semiconductor device. The method includes forming a protective layer covering the semiconductor device; selectively etching an opening down through the protective layer reaching a contact area of the semiconductor device, the opening being away from a protected area of the semiconductor device; and filling the opening with a conductive material to form the conductive stud. One embodiment may further include forming a dielectric liner directly on top of the semiconductor device, and forming the protective layer on top of the dielectric liner. Embodiments of the present invention also provide a semiconductor device made thereof.
摘要翻译：本发明的实施例提供一种形成与半导体器件接触的导电柱的方法。该方法包括形成覆盖半导体器件的保护层; 选择性地将开口向下蚀刻通过保护层到达半导体器件的接触区域，该开口远离半导体器件的保护区域; 并用导电材料填充开口以形成导电柱。一个实施例还可以包括直接在半导体器件的顶部上形成电介质衬垫，以及在电介质衬垫的顶部上形成保护层。本发明的实施例还提供由其制成的半导体器件。

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