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11. 发明申请

US20060082417A1 Phase locked loop and method for phase correction of a frequency controllable oscillator 有权
标题翻译：锁相环和频率可控振荡器相位校正方法
公开(公告)号：US20060082417A1
公开(公告)日：2006-04-20
申请号：US11086039
申请日：2005-03-22
申请人： Burkhard Neurauter , Gunter Marzinger , Christian Munker , Roland Vuketich
发明人： Burkhard Neurauter , Gunter Marzinger , Christian Munker , Roland Vuketich
IPC分类号： H03L7/00
CPC分类号： H03L7/1974
摘要： A phase locked loop is disclosed and includes a frequency divider circuit with a settable division ratio in a feedback path. The division ratio is produced using a control circuit which, besides an input for supplying the integer and fractional components for the frequency division ratio which is to be set, includes an input for supplying a phase correction signal. To produce the phase correction signal, the phase locked loop further includes a phase correction apparatus. The phase correction signal preferably contains a signal component with an exponential profile, and is supplied to the control circuit for producing a frequency division ratio for the frequency divider circuit such that it compensates for a phase drift in the output signal from the voltage controlled oscillator in the phase locked loop.
摘要翻译：公开了一种锁相环，并且包括在反馈路径中具有可设置的分频比的分频器电路。使用控制电路产生分频比，除了用于提供要被设置的分频比的整数和分数分量的输入外，还包括用于提供相位校正信号的输入。为了产生相位校正信号，锁相环还包括相位校正装置。相位校正信号优选地包含具有指数曲线的信号分量，并且被提供给控制电路以产生分频器电路的分频比，使得其补偿来自压控振荡器的输出信号中的相位漂移锁相环。

12. 发明申请

US20050104669A1 Two-point modulator arrangement 有权
标题翻译：两点调制器布置
公开(公告)号：US20050104669A1
公开(公告)日：2005-05-19
申请号：US10947847
申请日：2004-09-23
申请人： Stefan Herzinger , Gunter Marzinger , Burkhard Neurauter , Robert Weigel
发明人： Stefan Herzinger , Gunter Marzinger , Burkhard Neurauter , Robert Weigel
IPC分类号： H03C3/09 , H03L7/00
CPC分类号： H03C3/0975 , H03C3/0925 , H03C3/0933 , H03C3/0941
摘要： A two-point modulator arrangement is specified, said arrangement being developed with respect to conventional two-point modulators to the effect that the high-pass coupling-in point of the modulator that comprises a phase locked loop is formed by an expanded loop filter. In accordance with the present principle, the expanded loop filter comprises a coupling-in element, at which the modulation signal is combined with the output signal of a phase comparator. A voltage-controlled oscillator having only one tuning input can thus advantageously be used.
摘要翻译：指定了两点调制器布置，所述布置相对于传统的两点调制器被展开，使得包括锁相环的调制器的高通耦合点由扩展环路滤波器形成。根据本原理，扩展环路滤波器包括耦合入元件，其中调制信号与相位比较器的输出信号组合。因此，可以有利地使用仅具有一个调谐输入的压控振荡器。

13. 发明授权

US07831224B2 Radio-frequency IC for a mobile radio transmitter 有权
标题翻译：用于移动无线电发射机的射频IC
公开(公告)号：US07831224B2
公开(公告)日：2010-11-09
申请号：US11380549
申请日：2006-04-27
申请人： Burkhard Neurauter , Guenter Maerzinger , Clemens Troebinger , Thorsten Tracht
发明人： Burkhard Neurauter , Guenter Maerzinger , Clemens Troebinger , Thorsten Tracht
IPC分类号： H04B1/04
CPC分类号： H04L25/03038 , H04L25/03343 , H04L27/2042 , H04L27/227 , H04L2027/0038
摘要： A radio-frequency IC (3) for a mobile radio transmitter (1) has an analogue/digital converter unit (5) for digitizing baseband signals (AB), a recovery unit (6, 7, 8, 9, 10) for recovering determined data information (Rot, TxSymbPhase) on which the baseband signals (AB) are based, a digital/analogue converter unit (11) and a frequency converter unit for producing transmitted signals on the basis of the signals produced by the digital/analogue converter unit (11).
摘要翻译：用于移动无线电发射机（1）的射频IC（3）具有用于数字化基带信号（AB）的模拟/数字转换器单元（5），用于恢复的恢复单元（6,7,8,9,10）基于所述基带信号（AB）的确定的数据信息（Rot，TxSymbPhase），数/模转换器单元（11）和用于根据由数/模转换器产生的信号产生发送信号的变频器单元单位（11）。

14. 发明申请

US20120140685A1 SIMPLIFIED ADAPTIVE FILTER ALGORITHM FOR THE CANCELLATION OF TX-INDUCED EVEN ORDER INTERMODULATION PRODUCTS 审中-公开
标题翻译：简化自适应滤波算法，用于取消TX诱导的即时交互产品
公开(公告)号：US20120140685A1
公开(公告)日：2012-06-07
申请号：US12957612
申请日：2010-12-01
申请人： Christian Lederer , Huemer Mario , Stefan Herzinger , Gernot Hueber , Burkhard Neurauter , Andreas Mayer
发明人： Christian Lederer , Huemer Mario , Stefan Herzinger , Gernot Hueber , Burkhard Neurauter , Andreas Mayer
IPC分类号： H04B3/20 , G06F17/10
CPC分类号： H04L27/3854 , H04L25/03057
摘要： One embodiment of the present invention relates to an adaptive filtering apparatus comprising first and second real valued adaptive filters, respectively configured to receive an adaptive filter input signal based upon a transmission signal in a transmission path. The first real valued adaptive filter is configured to operate a real valued adaptive filter algorithm on the input signal to estimate a first intermodulation noise component (e.g., an in-phase component) in a desired signal and to cancel the estimated noise. The second real valued adaptive filter is configured to operate a real valued adaptive filter algorithm on the input signal to estimate a second intermodulation noise component (e.g., a quadrature phase component) in the desired signal and to cancel the estimated noise. Accordingly, each filter operates a real valued adaptive algorithm to cancel a noise component, thereby removing complex cross terms between the components from the adaptive filtering process.
摘要翻译：本发明的一个实施例涉及一种包括第一和第二实值自适应滤波器的自适应滤波装置，分别被配置为基于传输路径中的传输信号接收自适应滤波器输入信号。第一实值自适应滤波器被配置为在输入信号上操作实值自适应滤波器算法以估计期望信号中的第一互调噪声分量（例如，同相分量）并消除所估计的噪声。第二实值自适应滤波器被配置为在输入信号上操作实值自适应滤波器算法以估计期望信号中的第二互调噪声分量（例如，正交相位分量）并消除所估计的噪声。因此，每个滤波器操作实值自适应算法以消除噪声分量，从而从自适应滤波处理中去除组件之间的复杂交叉项。

15. 发明申请

US20080191759A1 Loop filter and phase-locked loop 有权
标题翻译：环路滤波器和锁相环路
公开(公告)号：US20080191759A1
公开(公告)日：2008-08-14
申请号：US11704544
申请日：2007-02-09
申请人： Burkhard Neurauter , Harald Pretl , Rastislav Vazny , Thomas Greifeneder
发明人： Burkhard Neurauter , Harald Pretl , Rastislav Vazny , Thomas Greifeneder
IPC分类号： H03L7/08
CPC分类号： H03L7/0895 , H03D13/004 , H03L7/0891 , H03L7/093 , H03L7/1976
摘要： A loop filter includes an input terminal, an output terminal, and a control terminal for a selection signal. At least one low pass filter is disposed between that input terminal and that output terminal. The loop filter is adapted to select a configuration out of a first configuration and at least one second configuration in response to the selection signal. In the first configuration, the loop filter comprises a non-integrating transfer characteristic in operation. In the second configuration, the loop filter comprises an integrating signal transfer characteristic in operation.
摘要翻译：环路滤波器包括输入端子，输出端子和用于选择信号的控制端子。在该输入端子和该输出端子之间设置至少一个低通滤波器。环路滤波器适于响应于选择信号从第一配置和至少一个第二配置中选择配置。在第一配置中，环路滤波器包括操作中的非积分传递特性。在第二配置中，环路滤波器包括操作中的积分信号传输特性。

16. 发明申请

US20060258307A1 Radio-Frequency IC for a Mobile Radio Transmitter 有权
标题翻译：用于移动无线电发射机的射频IC
公开(公告)号：US20060258307A1
公开(公告)日：2006-11-16
申请号：US11380549
申请日：2006-04-27
申请人： Burkhard Neurauter , Guenter Maerzinger , Clemens Troebinger , Thorsten Tracht
发明人： Burkhard Neurauter , Guenter Maerzinger , Clemens Troebinger , Thorsten Tracht
IPC分类号： H04B1/04 , H01Q11/12
CPC分类号： H04L25/03038 , H04L25/03343 , H04L27/2042 , H04L27/227 , H04L2027/0038
摘要： A radio-frequency IC (3) for a mobile radio transmitter (1) has an analogue/digital converter unit (5) for digitizing baseband signals (AB), a recovery unit (6, 7, 8, 9, 10) for recovering determined data information (Rot, TxSymbPhase) on which the baseband signals (AB) are based, a digital/analogue converter unit (11) and a frequency converter unit for producing transmitted signals on the basis of the signals produced by the digital/analogue converter unit (11).
摘要翻译：用于移动无线电发射机（1）的射频IC（3）具有用于数字化基带信号（AB）的模/数转换器单元（5），用于恢复的恢复单元（6,7,8,9,10）基于信号（AB）的确定的数据信息（Rot，TxSymbPhase），数/模转换器单元（11）和用于根据数/模转换器产生的信号产生发送信号的变频器单元单位（11）。

17. 发明申请

US20050258878A1 Frequency-dividing circuit arrangement and phase locked loop employing such circuit arrangement 有权
标题翻译：采用这种电路装置的分频电路装置和锁相环
公开(公告)号：US20050258878A1
公开(公告)日：2005-11-24
申请号：US11114960
申请日：2005-04-26
申请人： Burkhard Neurauter , Markus Scholz
发明人： Burkhard Neurauter , Markus Scholz
IPC分类号： H03K23/66 , H03K23/68 , H03L7/197 , H03K21/00
CPC分类号： H03K23/667 , H03K23/68 , H03L7/1974
摘要： A frequency-dividing circuit arrangement is disclosed that includes a divider chain having a plurality of frequency divider stages. The frequency dividers can be changed over between the division ratios 2 and 3. At least that frequency divider that is arranged on the output side of the divider chain has an additional through-switching input that makes it possible to switch through the input signal to the output of the divider stage without influencing the delay-time effects of the divider stage. The advantages of a cascaded 2/3 divider chain, such as a high cut-off frequency, a simple design and the ability to arbitrarily expand, are thus achieved without accepting a lower limit of the range of possible division values.
摘要翻译：公开了一种分频电路装置，其包括具有多个分频器级的分压器链。分频比可以在分频比2和3之间进行切换。至少分频器输出侧的分频器至少有一个额外的通过切换输入，可以通过输入信号切换到分频器的输出，而不影响分频器的延迟时间效应。因此，在不接受可能的分割值的范围的下限的情况下，实现了级联2/3分频器链的优点，例如高截止频率，简单设计和任意扩展的能力。

18. 发明授权

US07586994B2 Interface apparatus and method for data recovery and synchronization 失效
标题翻译：用于数据恢复和同步的接口设备和方法
公开(公告)号：US07586994B2
公开(公告)日：2009-09-08
申请号：US11055740
申请日：2005-02-10
申请人： Stefan Herzinger , Christian Münker , Burkhard Neurauter
发明人： Stefan Herzinger , Christian Münker , Burkhard Neurauter
IPC分类号： H04L27/20
CPC分类号： H04L27/0014 , H04L2027/0016 , H04L2027/0018
摘要： The invention provides an interface apparatus for data recovery which supplies an analog signal (applied to the input and containing data in line with a coding) having a first component and a second component to a signal processor. From this, the signal processor produces a continuous, demodulated data stream. The data stream is supplied to a connected delay unit, whose output is designed to provide the stored data symbols and whose delay in provision can be set by a signal at a control input. The interface allows a digital modulator to be connected to an analog I/Q interface on a baseband unit.
摘要翻译：本发明提供了一种用于数据恢复的接口装置，其向信号处理器提供具有第一分量和第二分量的模拟信号（应用于输入并包含符合编码的数据）。由此，信号处理器产生连续的解调数据流。数据流被提供给连接的延迟单元，其输出被设计为提供所存储的数据符号，并且可以通过控制输入端的信号设置其提供延迟。该接口允许将数字调制器连接到基带单元上的模拟I / Q接口。

19. 发明授权

US07394320B2 Phase-locked loop and method for operating a phase-locked-loop 失效
标题翻译：锁相环和操作锁相环的方法
公开(公告)号：US07394320B2
公开(公告)日：2008-07-01
申请号：US11584318
申请日：2006-10-20
申请人： Linus Maurer , Thomas Mayer , Burkhard Neurauter , Christian Wicpalek
发明人： Linus Maurer , Thomas Mayer , Burkhard Neurauter , Christian Wicpalek
IPC分类号： H03L7/00
CPC分类号： H03L7/18 , H03L7/081 , H03L7/091
摘要： A phase-locked loop suitable for mobile radio communications and a method for operating the same is disclosed. One embodiment of the phase-locked loop comprises an oscillator, a counter, a comparator, and a delay arrangement. The counter comprises a first input connected to the oscillator, a second input connected to a reference frequency terminal, and an output. An input of the comparator is connected to the output of the counter and an output of the comparator to the oscillator. The delay arrangement is connected between the oscillator and the first input of the counter or between the reference frequency terminal and the second input of the counter. The delay arrangement delays an input signal sent to an input of the delay arrangement, as a function of a sequence signal and makes a delayed signal available at an output of the delay arrangement.
摘要翻译：公开了一种适用于移动无线电通信的锁相环路及其操作方法。锁相环的一个实施例包括振荡器，计数器，比较器和延迟装置。计数器包括连接到振荡器的第一输入端，连接到参考频率端子的第二输入端和输出端。比较器的输入端连接到计数器的输出端和比较器的输出端连接到振荡器。延迟装置连接在振荡器和计数器的第一输入端之间或连接在基准频率端子和计数器的第二输入端之间。延迟装置将发送到延迟装置的输入的输入信号作为序列信号的函数进行延迟，并使延迟信号在延迟装置的输出处可用。

20. 发明申请

US20070096833A1 Phase-locked loop and method for operating a phase-locked-loop 失效
标题翻译：锁相环和操作锁相环的方法
公开(公告)号：US20070096833A1
公开(公告)日：2007-05-03
申请号：US11584318
申请日：2006-10-20
申请人： Linus Maurer , Thomas Mayer , Burkhard Neurauter , Christian Wicpalek
发明人： Linus Maurer , Thomas Mayer , Burkhard Neurauter , Christian Wicpalek
IPC分类号： H03L7/085
CPC分类号： H03L7/18 , H03L7/081 , H03L7/091
摘要： A phase-locked loop suitable for mobile radio communications and a method for operating the same is disclosed. One embodiment of the phase-locked loop comprises an oscillator, a counter, a comparator, and a delay arrangement. The counter comprises a first input connected to the oscillator, a second input connected to a reference frequency terminal, and an output. An input of the comparator is connected to the output of the counter and an output of the comparator to the oscillator. The delay arrangement is connected between the oscillator and the first input of the counter or between the reference frequency terminal and the second input of the counter. The delay arrangement delays an input signal sent to an input of the delay arrangement, as a function of a sequence signal and makes a delayed signal available at an output of the delay arrangement.
摘要翻译：公开了一种适用于移动无线电通信的锁相环路及其操作方法。锁相环的一个实施例包括振荡器，计数器，比较器和延迟装置。计数器包括连接到振荡器的第一输入端，连接到参考频率端子的第二输入端和输出端。比较器的输入端连接到计数器的输出端和比较器的输出端连接到振荡器。延迟装置连接在振荡器和计数器的第一输入端之间或连接在基准频率端子和计数器的第二输入端之间。延迟装置将发送到延迟装置的输入的输入信号作为序列信号的函数进行延迟，并使延迟信号在延迟装置的输出处可用。

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