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11. 发明申请

US20130011961A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130011961A1
公开(公告)日：2013-01-10
申请号：US13539907
申请日：2012-07-02
申请人： Akihiro ISHIZUKA , Kazuya HANAOKA , Shinya SASAGAWA , Sho NAGAMATSU
发明人： Akihiro ISHIZUKA , Kazuya HANAOKA , Shinya SASAGAWA , Sho NAGAMATSU
IPC分类号： H01L21/36
CPC分类号： H01L21/02422 , H01L21/02488 , H01L21/02554 , H01L21/02565 , H01L21/02658 , H01L21/02661 , H01L21/3105 , H01L29/66969 , H01L29/78636 , H01L29/7869
摘要： An object is to provide a semiconductor device having excellent characteristics, in which a channel layer includes an oxide semiconductor with high crystallinity. In addition, a semiconductor device including a base film with improved planarity is provided. CMP treatment is performed on the base film of the transistor and plasma treatment is performed thereon after the CMP treatment, whereby the base film can have a center line average roughness Ra75 of less than 0.1 nm. The oxide semiconductor layer with high crystallinity is formed over the base film having planarity, which is obtained by the combination of the plasma treatment and the CMP treatment, thereby improving the characteristics of the semiconductor device.
摘要翻译：目的在于提供具有优异特性的半导体器件，其中沟道层包括具有高结晶度的氧化物半导体。此外，提供了包括具有改善的平面度的基膜的半导体器件。在晶体管的基膜上进行CMP处理，在CMP处理之后进行等离子体处理，由此基膜的中心线平均粗糙度Ra75可以小于0.1nm。在通过等离子体处理和CMP处理的组合获得的具有平坦度的基膜上形成具有高结晶度的氧化物半导体层，从而提高半导体器件的特性。

12. 发明申请

US20120052661A1 ETCHING METHOD AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：用于制造半导体器件的蚀刻方法和方法
公开(公告)号：US20120052661A1
公开(公告)日：2012-03-01
申请号：US13213130
申请日：2011-08-19
申请人： Shinya SASAGAWA , Hiroshi FUJIKI , Shinobu FURUKAWA , Hidekazu MIYAIRI
发明人： Shinya SASAGAWA , Hiroshi FUJIKI , Shinobu FURUKAWA , Hidekazu MIYAIRI
IPC分类号： H01L21/20
CPC分类号： H01L21/32137 , H01L29/6675 , H01L29/66765 , H01L29/78663 , H01L29/78669 , H01L29/78672 , H01L29/78678 , H01L29/78687
摘要： A method for etching is provided in which the etching selectivity of an amorphous semiconductor film to a crystalline semiconductor film is high. Part of a stacked semiconductor film in which an amorphous semiconductor film is provided on a crystalline semiconductor film is etched using a mixed gas of a Br-based gas, a F-based gas, and an oxygen gas, so that part of the crystalline semiconductor film provided in the stacked semiconductor film is exposed. Reduction in the film thickness of the exposed portion can be suppressed by performing the etching in such a manner. Moreover, when etching for forming a back channel portion of a thin film transistor is performed with the method for etching, favorable electric characteristics of the thin film transistor can be obtained. An insulating layer is preferably provided over the thin film transistor.
摘要翻译：提供了一种用于蚀刻的方法，其中非晶半导体膜对结晶半导体膜的蚀刻选择性高。使用Br基气体，F系气体和氧气的混合气体蚀刻在结晶半导体膜上设置非晶半导体膜的层叠半导体膜的一部分，使得部分结晶半导体提供在堆叠的半导体膜中的膜被暴露。可以通过以这种方式进行蚀刻来抑制曝光部分的膜厚度的降低。此外，当利用蚀刻方法进行用于形成薄膜晶体管的背沟道部分的蚀刻时，可以获得薄膜晶体管的良好的电特性。绝缘层优选设置在薄膜晶体管的上方。

13. 发明申请

US20110272816A1 WIRING OVER SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHODS FOR MANUFACTURING THEREOF 有权
标题翻译：基板接线，半导体器件及其制造方法
公开(公告)号：US20110272816A1
公开(公告)日：2011-11-10
申请号：US13187746
申请日：2011-07-21
申请人： Shinya SASAGAWA , Satoru OKAMOTO , Shigeharu MONOE
发明人： Shinya SASAGAWA , Satoru OKAMOTO , Shigeharu MONOE
IPC分类号： H01L23/48 , H05K1/11
CPC分类号： H01L27/3276 , G02F2001/13629 , H01L21/32136 , H01L21/32137 , H01L21/32139 , H01L51/0021 , H01L51/0023 , H01L51/5281 , H01L2924/0002 , H05K3/06 , H05K2203/0315 , H05K2203/0346 , H05K2203/095 , H05K2203/1476 , H01L2924/00
摘要： A wiring over a substrate capable of reducing particles between wirings and a method for manufacturing the wiring is disclosed. A wiring over a substrate capable of preventing short-circuiting between wirings due to big difference in projection and depression between wirings and a method for manufacturing the wiring is also disclosed. Further, a wiring over a substrate capable of preventing cracks in the insulating layer due to stress at the edge of a wiring or particles and a method for manufacturing the wiring is also disclosed. According to the present invention, a method for manufacturing a wiring over a substrate is provided that comprises the steps of: forming a first conductive layer over an insulating surface; forming a first mask pattern over the first conductive layer; forming a second mask pattern by etching the first mask pattern under a first condition, simultaneously, forming a second conductive layer having a side having an angle of inclination cross-sectionally by etching the first conductive layer; and forming a third conductive layer and a third mask pattern by etching the second conductive layer and the second mask pattern under a second condition; wherein a selective ratio under the first condition of the first conductive layer to the first mask pattern is in a range of 0.25 to 4, and a selective ratio under the second condition of the second conductive layer to the second mask pattern is larger than that under the first condition.
摘要翻译：公开了一种能够减少布线之间的颗粒的基板上的布线和用于制造布线的方法。还公开了一种能够防止布线之间的大的差异和配线间的凹陷之间的布线之间的短路的布线和布线的制造方法。此外，还公开了能够防止由于布线或颗粒的边缘处的应力导致的绝缘层中的裂纹的基板上的布线以及布线的制造方法。根据本发明，提供了一种用于在衬底上制造布线的方法，包括以下步骤：在绝缘表面上形成第一导电层; 在所述第一导电层上形成第一掩模图案; 通过在第一条件下蚀刻第一掩模图案形成第二掩模图案，同时通过蚀刻第一导电层形成具有横截面为倾斜角的一侧的第二导电层; 以及通过在第二条件下蚀刻所述第二导电层和所述第二掩模图案来形成第三导电层和第三掩模图案; 其中在第一导电层与第一掩模图案的第一条件下的选择比在0.25至4的范围内，并且在第二导电层与第二掩模图案的第二条件下的选择比大于第一个条件。

14. 发明申请

US20110147755A1 THIN FILM TRANSISTOR 有权
标题翻译：薄膜晶体管
公开(公告)号：US20110147755A1
公开(公告)日：2011-06-23
申请号：US12972994
申请日：2010-12-20
申请人： Hidekazu MIYAIRI , Shinya SASAGAWA , Motomu KURATA
发明人： Hidekazu MIYAIRI , Shinya SASAGAWA , Motomu KURATA
IPC分类号： H01L29/786
CPC分类号： H01L29/78678 , H01L29/66765 , H01L29/78618 , H01L29/78648
摘要： A thin film transistor having favorable electric characteristics with high productively is provided. The thin film transistor includes a gate insulating layer covering a gate electrode, a semiconductor layer in contact with the gate insulating layer, an impurity semiconductor layer which is in contact with part of the semiconductor layer and functions as a source region and a drain region, and a wiring in contact with the impurity semiconductor layer. The semiconductor layer includes a microcrystalline semiconductor region having a concave-convex shape, which is formed on the gate insulating layer side, and an amorphous semiconductor region in contact with the microcrystalline semiconductor region. A barrier region is provided between the semiconductor layer and the wiring.
摘要翻译：提供了具有良好的电特性的高效生产的薄膜晶体管。薄膜晶体管包括覆盖栅极的栅极绝缘层，与栅极绝缘层接触的半导体层，与半导体层的一部分接触并用作源极区域和漏极区域的杂质半导体层，以及与杂质半导体层接触的布线。半导体层包括形成在栅绝缘层侧的具有凹凸形状的微晶半导体区域和与微晶半导体区域接触的非晶半导体区域。在半导体层和布线之间设置有阻挡区域。

15. 发明申请

US20100283105A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100283105A1
公开(公告)日：2010-11-11
申请号：US12840442
申请日：2010-07-21
申请人： Shunpei YAMAZAKI , Hideomi SUZAWA , Shinya SASAGAWA , Motomu KURATA
发明人： Shunpei YAMAZAKI , Hideomi SUZAWA , Shinya SASAGAWA , Motomu KURATA
IPC分类号： H01L29/786
CPC分类号： H01L29/41733 , H01L21/76804 , H01L21/76805 , H01L23/485 , H01L27/124 , H01L2924/0002 , H01L2924/00
摘要： A technique of manufacturing a semiconductor device in which etching in formation of a contact hole can be easily controlled is proposed. A semiconductor device includes at least a semiconductor layer formed over an insulating surface; a first insulating layer formed over the semiconductor layer; a gate electrode formed over the first insulating layer; a second insulating layer formed over the gate electrode; and a conductive layer formed over the second insulating layer connected to the semiconductor layer via an opening which is formed at least in the semiconductor layer and the second insulating layer and partially exposes the insulating surface. The conductive layer is electrically connected to the semiconductor layer at the side surface of the opening which is formed in the semiconductor layer.
摘要翻译：提出了可以容易地控制形成接触孔的蚀刻的半导体器件的制造技术。半导体器件至少包括形成在绝缘表面上的半导体层; 形成在所述半导体层上的第一绝缘层; 形成在所述第一绝缘层上的栅电极; 形成在所述栅电极上的第二绝缘层; 以及形成在所述第二绝缘层之上的导电层，所述导电层经由至少在所述半导体层和所述第二绝缘层中形成并且部分地暴露所述绝缘表面的开口连接到所述半导体层。导电层在形成于半导体层的开口的侧面与半导体层电连接。

16. 发明申请

US20100047997A1 METHOD FOR MANUFACTURING SOI SUBSTRATE 有权
标题翻译：制造SOI衬底的方法
公开(公告)号：US20100047997A1
公开(公告)日：2010-02-25
申请号：US12505020
申请日：2009-07-17
申请人： Akihiro ISHIZUKA , Shinya SASAGAWA , Motomu KURATA , Atsushi HIKOSAKA , Taiga MURAOKA , Hitoshi NAKAYAMA
发明人： Akihiro ISHIZUKA , Shinya SASAGAWA , Motomu KURATA , Atsushi HIKOSAKA , Taiga MURAOKA , Hitoshi NAKAYAMA
IPC分类号： H01L21/762
CPC分类号： H01L21/76254
摘要： It is an object of the preset invention to increase adhesiveness of a semiconductor layer and a base substrate and to reduce defective bonding. An oxide film is formed on a semiconductor substrate and the semiconductor substrate is irradiated with accelerated ions through the oxide film, whereby an embrittled region is formed at a predetermined depth from a surface of the semiconductor substrate. Plasma treatment is performed on the oxide film on the semiconductor substrate and the base substrate by applying a bias voltage, the surface of the semiconductor substrate and a surface of the base substrate are disposed opposite to each other, a surface of the oxide film is bonded to the surface of the base substrate, heat treatment is performed after the surface of the oxide film is bonded to the surface of the base substrate, and separation is caused along the embrittled region, whereby a semiconductor layer is formed over the base substrate with the oxide film interposed therebetween.
摘要翻译：本发明的一个目的是增加半导体层和基底衬底的粘附性并减少不良接合。在半导体衬底上形成氧化物膜，半导体衬底通过氧化膜照射加速离子，从而在半导体衬底的表面形成预定深度的脆化区域。通过施加偏置电压对半导体衬底和基底衬底上的氧化物膜进行等离子体处理，半导体衬底的表面和基底衬底的表面彼此相对设置，氧化膜的表面被接合在基底表面上进行热处理之后，在氧化膜的表面接合到基底表面之后进行热处理，沿脆化区域分离，由此在基底基板上形成半导体层氧化膜。

17. 发明申请

US20120319101A1 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US20120319101A1
公开(公告)日：2012-12-20
申请号：US13484742
申请日：2012-05-31
申请人： Shinya SASAGAWA , Hiroshi FUJIKI , Yoshinori IEDA
发明人： Shinya SASAGAWA , Hiroshi FUJIKI , Yoshinori IEDA
IPC分类号： H01L21/36 , H01L29/786
CPC分类号： H01L29/66969 , H01L21/02164 , H01L21/02178 , H01L21/02554 , H01L21/02565 , H01L21/47573 , H01L29/41733 , H01L29/66742 , H01L29/7869
摘要： A first insulating film in contact with an oxide semiconductor film and a second insulating film are stacked in this order over an electrode film of a transistor including the oxide semiconductor film, an etching mask is formed over the second insulating film, an opening portion exposing the electrode film is formed by etching a portion of the first insulating film and a portion of the second insulating film, the opening portion exposing the electrode film is exposed to argon plasma, the etching mask is removed, and a conductive film is formed in the opening portion exposing the electrode film. The first insulating film is an insulating film whose oxygen is partly released by heating. The second insulating film is less easily etched than the first insulating film and has a lower gas-permeability than the first insulating film.
摘要翻译：与氧化物半导体膜和第二绝缘膜接触的第一绝缘膜依次层叠在包含氧化物半导体膜的晶体管的电极膜上，在第二绝缘膜上形成蚀刻掩模，通过蚀刻第一绝缘膜的一部分和第二绝缘膜的一部分形成电极膜，将暴露于电极膜的开口部暴露于氩等离子体中，除去蚀刻掩模，并且在开口中形成导电膜部分暴露电极膜。第一绝缘膜是其氧气通过加热部分释放的绝缘膜。第二绝缘膜比第一绝缘膜不易蚀刻，并且具有比第一绝缘膜更低的透气性。

18. 发明申请

US20120319100A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120319100A1
公开(公告)日：2012-12-20
申请号：US13483078
申请日：2012-05-30
申请人： Kyoko YOSHIOKA , Junichi KOEZUKA , Shinji OHNO , Yuichi SATO , Shinya SASAGAWA
发明人： Kyoko YOSHIOKA , Junichi KOEZUKA , Shinji OHNO , Yuichi SATO , Shinya SASAGAWA
IPC分类号： H01L29/786 , H01L21/44
CPC分类号： H01L29/7869 , H01L21/324 , H01L29/66969
摘要： A miniaturized semiconductor device in which an increase in power consumption is suppressed and a method for manufacturing the semiconductor device are provided. A highly reliable semiconductor device having stable electric characteristics and a method for manufacturing the semiconductor device are provided. An oxide semiconductor film is irradiated with ions accelerated by an electric field in order to reduce the average surface roughness of a surface of the oxide semiconductor film. Consequently, an increase in the leakage current and power consumption of a transistor can be suppressed. Moreover, by performing heat treatment so that the oxide semiconductor film includes a crystal having a c-axis substantially perpendicular to the surface of the oxide semiconductor film, a change in electric characteristics of the oxide semiconductor film due to irradiation with visible light or ultraviolet light can be suppressed.
摘要翻译：提供抑制功耗增加的小型化半导体装置及其制造方法。提供了一种具有稳定电特性的高度可靠的半导体器件及其半导体器件的制造方法。为了降低氧化物半导体膜的表面的平均表面粗糙度，用电场加速的离子照射氧化物半导体膜。因此，可以抑制晶体管的漏电流和功耗的增加。此外，通过进行热处理使得氧化物半导体膜包括具有与氧化物半导体膜的表面基本垂直的c轴的晶体，由于可见光或紫外线的照射而导致的氧化物半导体膜的电特性的变化可以抑制。

19. 发明申请

US20120286261A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120286261A1
公开(公告)日：2012-11-15
申请号：US13466583
申请日：2012-05-08
申请人： Shinya SASAGAWA , Akihiro ISHIZUKA , Takehisa HATANO
发明人： Shinya SASAGAWA , Akihiro ISHIZUKA , Takehisa HATANO
IPC分类号： H01L29/12 , H01L21/336
CPC分类号： H01L21/8252 , H01L21/8256 , H01L27/0605 , H01L27/1225 , H01L29/78603 , H01L29/7869 , H01L29/78696
摘要： In a transistor including a wide band gap semiconductor layer as a semiconductor layer, a wide band gap semiconductor layer is separated into an island shape by an insulating layer with passivation properties for preventing atmospheric components from permeating. The edge portion of the island shape wide band gap semiconductor layer is in contact with the insulating film; thus, moisture or atmospheric components can be prevented from entering from the edge portion of the semiconductor layer to the wide band gap semiconductor layer.
摘要翻译：在包括作为半导体层的宽带隙半导体层的晶体管中，通过具有防止大气成分渗透的钝化特性的绝缘层将宽带隙半导体层分离成岛状。岛状宽带隙半导体层的边缘部分与绝缘膜接触; 因此，可以防止水分或大气成分从半导体层的边缘部分进入宽带隙半导体层。

20. 发明申请

US20120193625A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件和半导体器件的方法
公开(公告)号：US20120193625A1
公开(公告)日：2012-08-02
申请号：US13357902
申请日：2012-01-25
申请人： Shinya SASAGAWA , Motomu KURATA
发明人： Shinya SASAGAWA , Motomu KURATA
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/66969 , H01L21/441 , H01L29/41733 , H01L29/7869
摘要： An object is to provide a semiconductor device in which defects are reduced and miniaturization is achieved while favorable characteristics are maintained. A semiconductor layer is formed; a first conductive layer is formed over the semiconductor layer; the first conductive layer is etched with use of a first resist mask to form a second conductive layer having a recessed portion; the first resist mask is reduced in size to form a second resist mask; the second conductive layer is etched with use of the second resist mask to form source and drain electrodes each having a projecting portion with a tapered shape at the peripheries; a gate insulating layer is formed over the source and drain electrodes to be in contact with part of the semiconductor layer; and a gate electrode is formed in a portion over the gate insulating layer and overlapping with the semiconductor layer.
摘要翻译：本发明的目的是提供一种在保持有利特性的同时减小缺陷并实现小型化的半导体器件。形成半导体层; 在半导体层上形成第一导电层; 使用第一抗蚀剂掩模蚀刻第一导电层以形成具有凹部的第二导电层; 第一抗蚀剂掩模的尺寸减小以形成第二抗蚀剂掩模; 使用第二抗蚀剂掩模蚀刻第二导电层，以形成在周边具有锥形形状的突出部分的源极和漏极; 在源极和漏极上形成栅极绝缘层以与半导体层的一部分接触; 并且栅极电极形成在栅极绝缘层上方并与半导体层重叠的部分。

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