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1. 发明申请

US20090206494A1 WIRING OVER SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHODS FOR MANUFACTURING THEREOF 有权
标题翻译：基板接线，半导体器件及其制造方法
公开(公告)号：US20090206494A1
公开(公告)日：2009-08-20
申请号：US12431170
申请日：2009-04-28
申请人： Shinya SASAGAWA , Satoru OKAMOTO , Shigeharu MONOE
发明人： Shinya SASAGAWA , Satoru OKAMOTO , Shigeharu MONOE
IPC分类号： H01L23/52 , C23F1/00 , H01L21/3205 , H05K1/00
CPC分类号： H01L27/3276 , G02F2001/13629 , H01L21/32136 , H01L21/32137 , H01L21/32139 , H01L51/0021 , H01L51/0023 , H01L51/5281 , H01L2924/0002 , H05K3/06 , H05K2203/0315 , H05K2203/0346 , H05K2203/095 , H05K2203/1476 , H01L2924/00
摘要： A wiring over a substrate capable of reducing particles between wirings and a method for manufacturing the wiring is disclosed. A wiring over a substrate capable of preventing short-circuiting between wirings due to big difference in projection and depression between wirings and a method for manufacturing the wiring is also disclosed. Further, a wiring over a substrate capable of preventing cracks in the insulating layer due to stress at the edge of a wiring or particles and a method for manufacturing the wiring is also disclosed. According to the present invention, a method for manufacturing a wiring over a substrate is provided that comprises the steps of: forming a first conductive layer over an insulating surface; forming a first mask pattern over the first conductive layer; forming a second mask pattern by etching the first mask pattern under a first condition, simultaneously, forming a second conductive layer having a side having an angle of inclination cross-sectionally by etching the first conductive layer; and forming a third conductive layer and a third mask pattern by etching the second conductive layer and the second mask pattern under a second condition; wherein a selective ratio under the first condition of the first conductive layer to the first mask pattern is in a range of 0.25 to 4, and a selective ratio under the second condition of the second conductive layer to the second mask pattern is larger than that under the first condition.
摘要翻译：公开了一种能够减少布线之间的颗粒的基板上的布线和用于制造布线的方法。还公开了一种能够防止布线之间的大的差异和配线间的凹陷之间的布线之间的短路的布线和布线的制造方法。此外，还公开了能够防止由于布线或颗粒的边缘处的应力导致的绝缘层中的裂纹的基板上的布线以及布线的制造方法。根据本发明，提供了一种用于在衬底上制造布线的方法，包括以下步骤：在绝缘表面上形成第一导电层; 在所述第一导电层上形成第一掩模图案; 通过在第一条件下蚀刻第一掩模图案形成第二掩模图案，同时通过蚀刻第一导电层形成具有横截面为倾斜角的一侧的第二导电层; 以及通过在第二条件下蚀刻所述第二导电层和所述第二掩模图案来形成第三导电层和第三掩模图案; 其中在第一导电层与第一掩模图案的第一条件下的选择比在0.25至4的范围内，并且在第二导电层与第二掩模图案的第二条件下的选择比大于第一个条件。

2. 发明申请

US20110272816A1 WIRING OVER SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHODS FOR MANUFACTURING THEREOF 有权
标题翻译：基板接线，半导体器件及其制造方法
公开(公告)号：US20110272816A1
公开(公告)日：2011-11-10
申请号：US13187746
申请日：2011-07-21
申请人： Shinya SASAGAWA , Satoru OKAMOTO , Shigeharu MONOE
发明人： Shinya SASAGAWA , Satoru OKAMOTO , Shigeharu MONOE
IPC分类号： H01L23/48 , H05K1/11
CPC分类号： H01L27/3276 , G02F2001/13629 , H01L21/32136 , H01L21/32137 , H01L21/32139 , H01L51/0021 , H01L51/0023 , H01L51/5281 , H01L2924/0002 , H05K3/06 , H05K2203/0315 , H05K2203/0346 , H05K2203/095 , H05K2203/1476 , H01L2924/00
摘要： A wiring over a substrate capable of reducing particles between wirings and a method for manufacturing the wiring is disclosed. A wiring over a substrate capable of preventing short-circuiting between wirings due to big difference in projection and depression between wirings and a method for manufacturing the wiring is also disclosed. Further, a wiring over a substrate capable of preventing cracks in the insulating layer due to stress at the edge of a wiring or particles and a method for manufacturing the wiring is also disclosed. According to the present invention, a method for manufacturing a wiring over a substrate is provided that comprises the steps of: forming a first conductive layer over an insulating surface; forming a first mask pattern over the first conductive layer; forming a second mask pattern by etching the first mask pattern under a first condition, simultaneously, forming a second conductive layer having a side having an angle of inclination cross-sectionally by etching the first conductive layer; and forming a third conductive layer and a third mask pattern by etching the second conductive layer and the second mask pattern under a second condition; wherein a selective ratio under the first condition of the first conductive layer to the first mask pattern is in a range of 0.25 to 4, and a selective ratio under the second condition of the second conductive layer to the second mask pattern is larger than that under the first condition.
摘要翻译：公开了一种能够减少布线之间的颗粒的基板上的布线和用于制造布线的方法。还公开了一种能够防止布线之间的大的差异和配线间的凹陷之间的布线之间的短路的布线和布线的制造方法。此外，还公开了能够防止由于布线或颗粒的边缘处的应力导致的绝缘层中的裂纹的基板上的布线以及布线的制造方法。根据本发明，提供了一种用于在衬底上制造布线的方法，包括以下步骤：在绝缘表面上形成第一导电层; 在所述第一导电层上形成第一掩模图案; 通过在第一条件下蚀刻第一掩模图案形成第二掩模图案，同时通过蚀刻第一导电层形成具有横截面为倾斜角的一侧的第二导电层; 以及通过在第二条件下蚀刻所述第二导电层和所述第二掩模图案来形成第三导电层和第三掩模图案; 其中在第一导电层与第一掩模图案的第一条件下的选择比在0.25至4的范围内，并且在第二导电层与第二掩模图案的第二条件下的选择比大于第一个条件。

3. 发明申请

US20110104892A1 ETCHING METHOD AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件的蚀刻方法和制造方法
公开(公告)号：US20110104892A1
公开(公告)日：2011-05-05
申请号：US13004234
申请日：2011-01-11
申请人： Shinya SASAGAWA , Shigeharu MONOE
发明人： Shinya SASAGAWA , Shigeharu MONOE
IPC分类号： H01L21/768
CPC分类号： H01L27/1288 , H01L21/31116 , H01L27/1214 , H01L29/78621
摘要： The present invention discloses technique of etching selectively a layer containing siloxane. The present invention provides a semiconductor device with reduced operation deterioration due to etching failure. A method for manufacturing a semiconductor device comprises steps of forming a conductive layer electrically connecting to a transistor, an insulating layer covering the conductive layer, and a mask formed over the insulating layer; and etching the insulating layer with a processing gas including a hydrogen bromide gas.
摘要翻译：本发明公开了选择性地蚀刻含有硅氧烷的层的技术。本发明提供一种半导体器件，其由于蚀刻失效而导致操作劣化减小。一种制造半导体器件的方法包括以下步骤：形成电连接到晶体管的导电层，覆盖导电层的绝缘层和形成在绝缘层上的掩模; 并用包括溴化氢气体的处理气体蚀刻绝缘层。

4. 发明申请

US20070001225A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070001225A1
公开(公告)日：2007-01-04
申请号：US11425545
申请日：2006-06-21
申请人： Hideto OHNUMA , Shigeharu MONOE
发明人： Hideto OHNUMA , Shigeharu MONOE
IPC分类号： H01L21/84 , H01L27/12
CPC分类号： H01L27/1214 , H01L27/124 , H01L27/127 , H01L27/1288 , H01L29/78624
摘要： To provide a manufacturing method in which LDD regions with different widths are formed in a self-aligned manner, and the respective widths are precisely controlled in accordance with each circuit. By using a photomask or a reticle provided with an auxiliary pattern having a light intensity reduction function formed of a diffraction grating pattern or a semi-transparent film, the width of a region with a small thickness of a gate electrode can be freely set, and the widths of two LDD regions capable of being formed in a self-aligned manner with the gate electrode as a mask can be different in accordance with each circuit. In one TFT, both of two LDD regions with different widths overlap a gate electrode.
摘要翻译：为了提供以自对准方式形成具有不同宽度的LDD区域的制造方法，并且根据每个电路精确地控制各个宽度。通过使用具有由衍射光栅图案或半透明膜形成的具有光强度降低功能的辅助图案的光掩模或掩模版，可以自由地设定栅电极厚度的区域的宽度，并且能够以与栅电极为掩模的自对准方式形成的两个LDD区域的宽度可以根据每个电路而不同。在一个TFT中，具有不同宽度的两个LDD区域都与栅电极重叠。

5. 发明申请

US20060278875A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20060278875A1
公开(公告)日：2006-12-14
申请号：US11421922
申请日：2006-06-02
申请人： Hideto OHNUMA , Shigeharu MONOE , Shunpei YAMAZAKI
发明人： Hideto OHNUMA , Shigeharu MONOE , Shunpei YAMAZAKI
IPC分类号： H01L29/76
CPC分类号： H01L27/1214 , H01L27/124 , H01L27/1288 , H01L29/66757 , H01L29/78624
摘要： The present invention provides a TFT including at least one LDD region in a self-alignment manner without forming a sidewall spacer and increasing the number of manufacturing steps. A photomask or a reticle provided with an assist pattern that is formed of a diffraction grating pattern or a semi-transmitting film and has a function of reducing light intensity is employed in a photolithography step of forming a gate electrode, an asymmetrical resist pattern having a region with a thick thickness and a region with a thickness thinner than that of the above region on one side is formed, a gate electrode having a stepped portion is formed, and an LDD region is formed in a self-alignment manner by injecting an impurity element to the semiconductor layer through the region with a thin thickness of the gate electrode.
摘要翻译：本发明提供一种TFT，其以自对准方式提供至少一个LDD区域，而不形成侧壁间隔物并增加制造步骤的数量。在形成栅电极的光刻步骤中使用具有由衍射光栅图案或半透射膜形成的辅助图案并具有降低光强度的功能的光掩模或掩模版，具有形成厚度厚的区域和具有比一面上述区域的厚度薄的区域，形成具有台阶部分的栅电极，并且通过注入杂质以自对准方式形成LDD区域元件通过具有薄的栅电极厚度的区域到半导体层。

6. 发明申请

US20110204424A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110204424A1
公开(公告)日：2011-08-25
申请号：US13099840
申请日：2011-05-03
申请人： Ryo ARASAWA , Aya MIYAZAKI , Shigeharu MONOE , Shunpei YAMAZAKI
发明人： Ryo ARASAWA , Aya MIYAZAKI , Shigeharu MONOE , Shunpei YAMAZAKI
IPC分类号： H01L29/78
CPC分类号： H01L27/1266 , H01L27/124 , H01L29/78603 , H01L29/78606
摘要： An object is to provide a semiconductor device in which damages of an element such as a transistor are reduced even when physical force such as bending is externally applied to generate stress in the semiconductor device. A semiconductor device includes a semiconductor film including a channel formation region and an impurity region, which is provided over a substrate, a first conductive film provided over the channel formation region with a gate insulating film interposed therebetween, a first interlayer insulating film provided to cover the first conductive film, a second conductive film provided over the first interlayer insulating film so as to overlap with at least part of the impurity region, a second interlayer insulating film provided over the second conductive film, and a third conductive film provided over the second interlayer insulating film so as to be electrically connected to the impurity region through an opening.
摘要翻译：本发明的目的是提供一种半导体器件，其中即使当外部施加诸如弯曲的物理力在半导体器件中产生应力时，诸如晶体管的元件的损伤也减小。半导体器件包括：设置在基板上的沟道形成区域和杂质区域的半导体膜，设置在沟道形成区域上的栅极绝缘膜之间的第一导电膜，设置成覆盖的第一层间绝缘膜所述第一导电膜，设置在所述第一层间绝缘膜上以与所述杂质区的至少一部分重叠的第二导电膜，设置在所述第二导电膜上的第二层间绝缘膜，以及设置在所述第二导电膜上的第二导电膜层间绝缘膜，以通过开口与杂质区电连接。

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