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11. 发明申请

US20090111265A1 SELECTIVE SILICIDE FORMATION USING RESIST ETCHBACK 有权
标题翻译：选择性硅化物形成使用电阻蚀刻
公开(公告)号：US20090111265A1
公开(公告)日：2009-04-30
申请号：US11924823
申请日：2007-10-26
申请人： Kyunghoon Min , Angela Hui , Hiroyuki Kinoshita , Ning Cheng , Mark Chang
发明人： Kyunghoon Min , Angela Hui , Hiroyuki Kinoshita , Ning Cheng , Mark Chang
IPC分类号： H01L21/4763
CPC分类号： H01L27/115 , H01L21/28518 , H01L21/31144 , H01L27/105 , H01L27/1052 , H01L27/11534 , H01L27/11568 , H01L29/665
摘要： Methods of selectively forming metal silicides on a memory device are provided. The methods can include forming a mask layer over the memory device; forming a patterned resist over the mask layer; removing upper portions of the patterned resist; forming a patterned mask layer by removing portions of the mask layer that are not covered by the patterned resist; and forming metal silicides on the memory device by a chemical reaction of a metal layer formed on the memory device with portions of the memory device that are not covered by the patterned mask layer. By preventing silicidation of underlying silicon containing layers/components of the memory device that are covered by the patterned mask layer, the methods can selectively form the metal silicides on the desired portions of the memory device.
摘要翻译：提供了在存储器件上选择性地形成金属硅化物的方法。所述方法可以包括在存储器件上形成掩模层; 在掩模层上形成图案化的抗蚀剂; 去除图案化抗蚀剂的上部; 通过去除未被图案化抗蚀剂覆盖的掩模层的部分来形成图案化掩模层; 以及通过形成在存储器件上的金属层与未被图案化掩模层覆盖的存储器件的部分的化学反应在存储器件上形成金属硅化物。通过防止由图案化掩模层覆盖的存储器件的下层含硅层/部件的硅化，该方法可以选择性地在存储器件的期望部分上形成金属硅化物。

12. 发明授权

US06764929B1 Method and system for providing a contact hole in a semiconductor device 失效
标题翻译：用于在半导体器件中提供接触孔的方法和系统
公开(公告)号：US06764929B1
公开(公告)日：2004-07-20
申请号：US10151625
申请日：2002-05-16
申请人： Angela Hui , Chi Chang , Mark Chang
发明人： Angela Hui , Chi Chang , Mark Chang
IPC分类号： H01L21425
CPC分类号： H01L21/76897 , H01L21/265
摘要： A method and system for providing a contact hole between structures for a semiconductor device is disclosed. The method and system comprises etching a resist material on the semiconductor device to expose a surface of the structures; providing an implant to the surface of the structures; and removing the resist material from a gap between the structures. The method and system includes annealing the semiconductor device to cause the implant to adhere to the treated surface; and providing dielectric material within the gap. Finally, the method and system includes etching the contact hole in the gap between the structures. The contact hole can then be etched without damaging the structures. Accordingly, by providing an implant treated surface and then providing an anneal process the implant is bonded to the appropriate portion of the semiconductor structure. Due to the etch difference between the implant treated device and the non-treated surface, it is possible to etch down to the bottom of the semiconductor device without damaging the gate. Since the surface around the gate structure is treated, the etch stop layer etch at a much slower rate. Therefore, there is a much larger process margin for misalignment allowance and the contact size can be larger because the dielectric material and the surface treatment protects the gate area.
摘要翻译：公开了一种用于在半导体器件的结构之间提供接触孔的方法和系统。该方法和系统包括在半导体器件上蚀刻抗蚀剂材料以暴露结构的表面; 向所述结构的表面提供植入物; 以及从结构之间的间隙去除抗蚀剂材料。该方法和系统包括退火半导体器件以使植入物粘附到被处理的表面上; 并在间隙内提供电介质材料。最后，该方法和系统包括蚀刻结构之间的间隙中的接触孔。然后可以蚀刻接触孔而不损坏结构。因此，通过提供植入物处理的表面，然后提供退火工艺，将植入物结合到半导体结构的适当部分。由于植入物处理的设备和未处理的表面之间的蚀刻差异，可以在不损坏栅极的情况下向下蚀刻到半导体器件的底部。由于栅极结构周围的表面被处理，蚀刻停止层以较慢的速率蚀刻。因此，由于介电材料和表面处理保护了栅极区域，所以对于不对准余量有更大的处理余量，并且接触尺寸可以更大。

13. 发明授权

US5635423A Simplified dual damascene process for multi-level metallization and interconnection structure 失效
标题翻译：用于多层次金属化和互连结构的简化双镶嵌工艺
公开(公告)号：US5635423A
公开(公告)日：1997-06-03
申请号：US320516
申请日：1994-10-11
申请人： Richard J. Huang , Angela Hui , Robin Cheung , Mark Chang , Ming-Ren Lin
发明人： Richard J. Huang , Angela Hui , Robin Cheung , Mark Chang , Ming-Ren Lin
IPC分类号： H01L21/768 , H01L21/44
CPC分类号： H01L21/7681 , H01L21/76807 , H01L21/76813
摘要： A semiconductor device containing an interconnection structure having a reduced interwiring spacing is produced by a modified dual damascene process. In one embodiment, an opening for a via is initially formed in a second insulative layer above a first insulative layer with an etch stop layer therebetween. A larger opening for a trench is then formed in the second insulative layer while simultaneously extending the via opening through the etch stop layer and first insulative layer. The trench and via are then simultaneously filled with conductive material.
摘要翻译：通过改进的双镶嵌工艺产生包含具有减小的布线间距的互连结构的半导体器件。在一个实施例中，用于通孔的开口最初形成在第一绝缘层之上的第二绝缘层中，其间具有蚀刻停止层。然后在第二绝缘层中形成用于沟槽的较大开口，同时使通孔开口延伸穿过蚀刻停止层和第一绝缘层。沟槽和通孔然后同时填充导电材料。

14. 发明授权

US06399446B1 Process for fabricating high density memory cells using a metallic hard mask 有权
标题翻译：使用金属硬掩模制造高密度记忆单元的方法
公开(公告)号：US06399446B1
公开(公告)日：2002-06-04
申请号：US09429722
申请日：1999-10-29
申请人： Bharath Rangarajan , David K. Foote , Fei Wang , Dawn M. Hopper , Stephen K. Park , Jack Thomas , Mark Chang , Mark Ramsbey
发明人： Bharath Rangarajan , David K. Foote , Fei Wang , Dawn M. Hopper , Stephen K. Park , Jack Thomas , Mark Chang , Mark Ramsbey
IPC分类号： H01L218247
CPC分类号： H01L27/11568 , H01L27/115 , Y10S438/945
摘要： A process for fabricating a memory cell in a two-bit EEPROM device including forming an ONO layer overlying a semiconductor substrate, depositing a hard mask overlying the ONO layer, and patterning the hard mask. The hard mask is made from tungsten, titanium, or titanium nitride. The process further includes doping the semiconductor substrate with boron causing p-type regions to form in the semiconductor substrate, and doping the semiconductor substrate with n-type dopants, such as arsenic, causing n-type regions to form in the semiconductor substrate. The exposed ONO layer is then etched to expose part of the semiconductor substrate, and a bit-line oxide region is formed overlying the semiconductor substrate. The hard mask is then stripped, preferably using an H2O2 solution.
摘要翻译：一种用于在二位EEPROM器件中制造存储单元的方法，包括形成覆盖在半导体衬底上的ONO层，沉积覆盖在ONO层上的硬掩模，以及对该硬掩模进行构图。硬掩模由钨，钛或氮化钛制成。该工艺还包括用硼掺杂导致在半导体衬底中形成p型区域的半导体衬底，并且用诸如砷的n型掺杂剂掺杂半导体衬底，从而在半导体衬底中形成n型区域。然后对暴露的ONO层进行蚀刻以暴露半导体衬底的一部分，并且在半导体衬底上形成位线氧化物区域。然后将硬掩模剥离，优选使用H 2 O 2溶液。

15. 发明授权

US06486029B1 Integration of an ion implant hard mask structure into a process for fabricating high density memory cells 有权
标题翻译：将离子注入硬掩模结构集成到用于制造高密度存储器单元的工艺中
公开(公告)号：US06486029B1
公开(公告)日：2002-11-26
申请号：US09627563
申请日：2000-07-28
申请人： David K. Foote , Bharath Rangarajan , Stephan K. Park , Fei Wang , Dawn M. Hopper , Jack Thomas , Mark Chang , Mark Ramsbey
发明人： David K. Foote , Bharath Rangarajan , Stephan K. Park , Fei Wang , Dawn M. Hopper , Jack Thomas , Mark Chang , Mark Ramsbey
IPC分类号： H01L218247
CPC分类号： H01L27/11568 , H01L27/115 , Y10S438/954
摘要： A process for fabricating a memory cell in a two-bit EEPROM device, the process includes forming an ONO layer overlying a semiconductor substrate, depositing a hard mask overlying the ONO layer, and patterning the hard mask. Preferably, the hard mask includes a material selected from the group consisting of tungsten, titanium, titanium nitride, polysilicon, silicon, silicon nitride, silicon oxi-nitride, and silicon rich nitride. In one preferred embodiment, the process further includes implanting the semiconductor substrate with a p-type dopant at an angle substantially normal to the principal surface of the semiconductor substrate and annealing the semiconductor substrate upon implanting the semiconductor substrate with a p-type dopant. In one preferred embodiment, the process further includes implanting the semiconductor substrate with an n-type dopant.
摘要翻译：一种用于在2位EEPROM器件中制造存储单元的工艺，该工艺包括形成覆盖半导体衬底的ONO层，沉积覆盖在ONO层上的硬掩模，以及对该硬掩模进行构图。优选地，硬掩模包括选自钨，钛，氮化钛，多晶硅，硅，氮化硅，氧化氮化硅和富氮的氮化物的材料。在一个优选实施例中，该方法还包括以基本上垂直于半导体衬底的主表面的角度注入具有p型掺杂剂的半导体衬底，并在用p型掺杂剂注入半导体衬底时退火半导体衬底。在一个优选实施例中，该工艺还包括用n型掺杂剂注入半导体衬底。

16. 发明授权

US06436766B1 Process for fabricating high density memory cells using a polysilicon hard mask 有权
标题翻译：使用多晶硅硬掩模制造高密度存储单元的方法
公开(公告)号：US06436766B1
公开(公告)日：2002-08-20
申请号：US09430493
申请日：1999-10-29
申请人： Bharath Rangarajan , David K. Foote , Fei Wang , Dawn M. Hopper , Stephen K. Park , Jack Thomas , Mark Chang , Mark Ramsbey
发明人： Bharath Rangarajan , David K. Foote , Fei Wang , Dawn M. Hopper , Stephen K. Park , Jack Thomas , Mark Chang , Mark Ramsbey
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , H01L27/115
摘要： A process for fabricating a memory cell in a two-bit EEPROM device including forming an ONO layer overlying a semiconductor substrate, depositing a hard mask overlying the ONO layer, and patterning the hard mask. The hard mask is preferably made from polysilicon or silicon. The process further includes doping the semiconductor substrate with boron causing p-type regions to form in the semiconductor substrate, and doping the semiconductor substrate with n-type dopants, such as arsenic, causing n-type regions to form in the semiconductor substrate. The exposed ONO layer is then etched to expose part of the semiconductor substrate, and a bit-line oxide region is formed overlying the semiconductor substrate. The hard mask is then removed, preferably using a plasma etch process.
摘要翻译：一种用于在二位EEPROM器件中制造存储单元的方法，包括形成覆盖在半导体衬底上的ONO层，沉积覆盖在ONO层上的硬掩模，以及对该硬掩模进行构图。硬掩模优选由多晶硅或硅制成。该工艺还包括用硼掺杂导致在半导体衬底中形成p型区域的半导体衬底，并且用诸如砷的n型掺杂剂掺杂半导体衬底，从而在半导体衬底中形成n型区域。然后对暴露的ONO层进行蚀刻以暴露半导体衬底的一部分，并且在半导体衬底上形成位线氧化物区域。然后去除硬掩模，优选使用等离子体蚀刻工艺。

17. 发明申请

US20060223305A1 Etch process for CD reduction of arc material 有权
标题翻译：电弧材料的CD还原蚀刻工艺
公开(公告)号：US20060223305A1
公开(公告)日：2006-10-05
申请号：US11098049
申请日：2005-04-04
申请人： Phillip Jones , Mark Chang , Scott Bell
发明人： Phillip Jones , Mark Chang , Scott Bell
IPC分类号： H01L21/4763
CPC分类号： H01L21/32139 , H01L21/3088 , H01L21/31144
摘要： A method of reducing critical dimensions of a feature in a anti-reflective coating layer structure can utilize a polymerizing agent. The anti-reflective coating structure can be utilized to form various integrated circuit structures. The anti-reflective coating can be utilized to form gate stacks comprised of polysilicon and a dielectric layer, conductive lines, or other IC structure. The polymerizing agent can include carbon, hydrogen and fluorine.
摘要翻译：降低抗反射涂层结构中的特征的关键尺寸的方法可以利用聚合剂。抗反射涂层结构可用于形成各种集成电路结构。抗反射涂层可用于形成由多晶硅和电介质层，导电线或其它IC结构组成的栅叠层。聚合剂可以包括碳，氢和氟。

18. 发明申请

US20050092983A1 Sidewall formation for high density polymer memory element array 有权
标题翻译：用于高密度聚合物存储元件阵列的侧壁形成
公开(公告)号：US20050092983A1
公开(公告)日：2005-05-05
申请号：US10699903
申请日：2003-11-03
申请人： Christopher Lyons , Mark Chang , Sergey Lopatin , Ramkumar Subramanian , Patrick Cheung , Minh Ngo , Jane Oglesby
发明人： Christopher Lyons , Mark Chang , Sergey Lopatin , Ramkumar Subramanian , Patrick Cheung , Minh Ngo , Jane Oglesby
IPC分类号： G11C11/56 , G11C13/02 , H01L27/115 , H01L27/28 , H01L29/68 , H01L45/00 , H01L51/00 , H01L29/73
CPC分类号： G11C11/5664 , B82Y10/00 , G11C13/0014 , G11C13/0016 , H01L27/285 , H01L51/0595
摘要： Systems and methodologies are disclosed for increasing the number of memory cells associated with a lithographic feature. The systems comprise memory elements that are formed on the sidewalls of the lithographic feature by employing various depositing and etching processes. The side wall memory cells can have a bit line of the wafer as the first electrode and operate with a second formed electrode to activate a portion of an organic matter that is formed there between.
摘要翻译：公开了用于增加与光刻特征相关联的存储单元的数量的系统和方法。这些系统包括通过采用各种沉积和蚀刻工艺在光刻特征的侧壁上形成的记忆元件。侧壁存储单元可以具有作为第一电极的晶片的位线，并且与第二形成的电极一起操作以激活在其间形成的有机物的一部分。

19. 发明授权

US5494271A Transmission system for a document feeder 失效
标题翻译：文件传送系统
公开(公告)号：US5494271A
公开(公告)日：1996-02-27
申请号：US257570
申请日：1994-06-10
申请人： Jeffrey Wun , Steven Chiu , Mark Chang
发明人： Jeffrey Wun , Steven Chiu , Mark Chang
IPC分类号： B65H3/06 , B65H5/06
CPC分类号： B65H3/0669 , Y10T74/19172 , Y10T74/1921
摘要： An improved transmission system for a document feeder, in which a constant one-way-rotating gear train is mounted in an output zone so as to cause a transmission shaft in the output zone to rotate in one direction only to send out a sheet of document no matter the driving gear rotates clockwise or counter-clockwise; therefore, as soon as a first sheet of document moves out of the scanning line without moving out of the output zone, the driving gear will change its rotation clockwise so as to have a next sheet of document fed into the scanning zone; therefore, the feeding distance between two sheets of document will be reduced, and consequently the whole feeding time for a document will be reduced, too.
摘要翻译：一种用于文件馈送器的改进的传输系统，其中恒定的单向旋转齿轮系安装在输出区域中，以便使得输出区域中的传动轴在一个方向上旋转，仅发出一张文件无论主动齿轮顺时针还是逆时针旋转; 因此，只要第一张原稿从扫描线移出而不移出输出区域，驱动齿轮将顺时针转动其旋转，以便将下一张原稿送入扫描区域; 因此，两纸张之间的进纸距离将减小，因此文件的整个进纸时间也将减少。

20. 发明申请

US20080061359A1 Dual charge storage node with undercut gate oxide for deep sub-micron memory cell 审中-公开
标题翻译：具有底切栅极氧化物的双电荷存储节点用于深亚微米存储单元
公开(公告)号：US20080061359A1
公开(公告)日：2008-03-13
申请号：US11702847
申请日：2007-02-05
申请人： Chungho Lee , Hiroyuki Kinoshita , Zoran Krivokapic , Wei Zheng , Mark Chang , Rinji Sugino , Chi Chang
发明人： Chungho Lee , Hiroyuki Kinoshita , Zoran Krivokapic , Wei Zheng , Mark Chang , Rinji Sugino , Chi Chang
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/11568 , H01L27/11521 , H01L29/40114 , H01L29/40117 , H01L29/42332 , H01L29/42348 , H01L29/7885 , H01L29/7887 , H01L29/792 , H01L29/7923
摘要： An embodiment of the present invention is directed to a memory cell. The memory cell includes a stack formed over a substrate. The stack includes a gate oxide layer and an overlying polycrystalline silicon layer. The stack further includes first and second undercut regions formed under the polycrystalline silicon layer and adjacent to the gate oxide layer. The memory cell further includes a first charge storage element formed in the first undercut region and a second charge storage element formed in the second undercut region.
摘要翻译：本发明的实施例涉及存储单元。存储单元包括形成在衬底上的堆叠。堆叠包括栅极氧化物层和上覆的多晶硅层。堆叠还包括形成在多晶硅层下方并与栅极氧化物层相邻的第一和第二底切区域。存储单元还包括形成在第一底切区域中的第一电荷存储元件和形成在第二底切区域中的第二电荷存储元件。

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