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11. 发明授权

US09020779B2 Detecting cross-talk on processor links 有权
标题翻译：检测处理器链路上的串扰
公开(公告)号：US09020779B2
公开(公告)日：2015-04-28
申请号：US13281097
申请日：2011-10-25
申请人： Robert W. Berry, Jr. , Anand Haridass , Prasanna Jayaraman
发明人： Robert W. Berry, Jr. , Anand Haridass , Prasanna Jayaraman
IPC分类号： G06F11/263 , G06F9/30 , G06F11/34
CPC分类号： G06F9/30145 , G06F9/30 , G06F11/3409 , G06F11/3414 , G06F11/3466 , G06F11/349
摘要： A first of a plurality of data lanes of a first of a plurality of processor links is determined to have a weakest of base performance measurements for the plurality of data lanes. A switching data pattern is transmitted via a first set of the remainder processor links and a quiet data pattern is transmitted via a second set of the remainder processor links. If performance of the first data lane increases vis-à-vis the corresponding base performance measurement, the first set of remainder processor links is eliminated from the remainder processor links. If performance of the first data lanes decreases vis-à-vis the corresponding base performance measurement, the second set of remainder processor links is eliminated from the remainder processor links. The above operations are repeatedly executed until an aggressor processor link that is determined to decrease performance of the first of the plurality of data lanes is identified.
摘要翻译：多个处理器链路中的第一个处理器链路的多个数据通路中的第一个被确定为对于多个数据通道具有最弱的基本性能测量。经由剩余处理器链路的第一组发送切换数据模式，并且经由剩余处理器链路的第二组发送安静数据模式。如果第一数据线的性能相对于相应的基本性能测量增加，则剩余处理器链路的第一组从剩余处理器链路中消除。如果第一数据通道的性能相对于相应的基本性能测量值降低，则剩余处理器链路的第二组从剩余处理器链路中消除。重复执行上述操作，直到识别出被确定为降低多个数据通道中的第一个数据通道的性能的攻击者处理器链路。

12. 发明授权

US08826092B2 Characterization and validation of processor links 有权
公开(公告)号：US08826092B2
公开(公告)日：2014-09-02
申请号：US13281081
申请日：2011-10-25
申请人： Robert W. Berry, Jr. , Anand Haridass , Prasanna Jayaraman
发明人： Robert W. Berry, Jr. , Anand Haridass , Prasanna Jayaraman
IPC分类号： G06F11/00 , G01R31/319 , G06F11/22
CPC分类号： G06F11/3089 , G01R31/31926 , G06F9/30 , G06F9/30007 , G06F11/22 , G06F11/221 , G06F11/3409 , G06F11/3414 , G06F11/349 , G06F15/00
摘要： A processor link that couples a first processor and a second processor is selected for validation and a plurality of communication parameter settings associated with the first and the second processors is identified. The first and the second processors are successively configured with each of the communication parameter settings. One or more test data pattern(s) are provided from the first processor to the second processor in accordance with the communication parameter setting. Performance measurements associated with the selected processor link and with the communication parameter setting are determined based, at least in part, on the test data pattern as received at the second processor. One of the communication parameter settings that is associated with the highest performance measurements is selected. The selected communication parameter setting is applied to the first and the second processors for subsequent communication between the first and the second processors via the processor link.

13. 发明授权

US08165847B2 Implementing a programmable DMA master with write inconsistency determination 失效
标题翻译：实现具有写入不一致性确定的可编程DMA主机
公开(公告)号：US08165847B2
公开(公告)日：2012-04-24
申请号：US12187199
申请日：2008-08-06
申请人： Robert W. Berry, Jr. , Michael Criscolo , Christopher J. Kuruts , James P. Kuruts , Steven J. Smolski
发明人： Robert W. Berry, Jr. , Michael Criscolo , Christopher J. Kuruts , James P. Kuruts , Steven J. Smolski
IPC分类号： G06F11/30 , G11C29/00
CPC分类号： G11C29/48 , G06F11/26
摘要： A method, system, and computer-usable medium for implementing a programmable DMA master with data checking utilizing a drone system controller. According to an embodiment of the present invention, a drone processor generates a collection of random data and stores a first and second copy of the collection of random data in a first and second memory location in a drone memory. The drone processor writes a third copy of the collection of random data in a processor memory. When the drone processor retrieves the third copy from the processor memory, the drone processor writes the third copy in the second memory location in the drone memory. When the drone processor compares the first copy with the third copy, the results of the compare is written in a status location within the drone processor.
摘要翻译：一种用于使用无人机系统控制器实现具有数据检查的可编程DMA主机的方法，系统和计算机可用介质。根据本发明的实施例，无人机处理器生成随机数据的集合，并将随机数据的集合的第一和第二副本存储在无人机存储器中的第一和第二存储器位置中。无人机处理器将随机数据集合的第三副本写入处理器存储器。当无人机处理器从处理器存储器检索第三副本时，无人机处理器将第三副本写入无人机存储器中的第二存储器位置。当无人机处理器将第一副本与第三副本进行比较时，将比较结果写入无人机处理器内的状态位置。

14. 发明授权

US07430487B2 System and method for implementing a programmable DMA master with data checking utilizing a drone system controller 失效
标题翻译：使用无人机系统控制器实现具有数据检查的可编程DMA主机的系统和方法
公开(公告)号：US07430487B2
公开(公告)日：2008-09-30
申请号：US11470282
申请日：2006-09-06
申请人： Robert W. Berry, Jr. , Michael Criscolo , Christopher J. Kuruts , James P. Kuruts , Steven J. Smolski
发明人： Robert W. Berry, Jr. , Michael Criscolo , Christopher J. Kuruts , James P. Kuruts , Steven J. Smolski
IPC分类号： G11C29/00 , G06F19/00
CPC分类号： G11C29/48 , G06F11/26
摘要： A method, system, and computer-usable medium for implementing a programmable DMA master with data checking utilizing a drone system controller. According to an embodiment of the present invention, a drone processor generates a collection of random data and stores a first and second copy of the collection of random data in a first and second memory location in a drone memory. The drone processor writes a third copy of the collection of random data in a processor memory. When the drone processor retrieves the third copy from the processor memory, the drone processor writes the third copy in the second memory location in the drone memory. When the drone processor compares the first copy with the third copy, the results of the compare is written in a status location within the drone processor.
摘要翻译：一种用于使用无人机系统控制器实现具有数据检查的可编程DMA主机的方法，系统和计算机可用介质。根据本发明的实施例，无人机处理器生成随机数据的集合，并将随机数据的集合的第一和第二副本存储在无人机存储器中的第一和第二存储器位置中。无人机处理器将随机数据集合的第三副本写入处理器存储器。当无人机处理器从处理器存储器检索第三副本时，无人机处理器将第三副本写入无人机存储器中的第二存储器位置。当无人机处理器将第一副本与第三副本进行比较时，将比较结果写入无人机处理器内的状态位置。

15. 发明授权

US6006345A Pattern generator for memory burn-in and test 失效
标题翻译：图形发生器用于内存老化和测试
公开(公告)号：US6006345A
公开(公告)日：1999-12-21
申请号：US853597
申请日：1997-05-09
申请人： Robert W. Berry, Jr.
发明人： Robert W. Berry, Jr.
IPC分类号： G11C29/20 , G11C29/36 , G11C29/38 , G06F11/00
CPC分类号： G11C29/36 , G11C29/20 , G11C29/38
摘要： A system and method for testing of a memory during burn-in is disclosed. In one aspect, the method and system include an address generator. The address generator includes a shift register means. The shift register includes n bit positions. The n bit positions are for storing n bits. The n bits are capable of being in a plurality of patterns. The address generator further includes a counter coupled to the shift register means. The counter includes a value that is incremented in response to a particular pattern of the plurality of patterns. The address generator has a complement mechanism coupled to the shift register and the counter which provides a complement of at least a portion of the n bits stored in the n bit positions in response to the value in the counter. In another aspect, the method and system comprise the address generator previously discussed coupled to the memory undergoing testing. In this aspect, the method and system further have a data generator coupled to the address generator and the memory and compare circuitry coupled to the memory and the data generator. In this aspect, a fail is detected when data from the data generator does not match data stored in the memory.
摘要翻译：公开了一种用于在老化期间测试存储器的系统和方法。一方面，该方法和系统包括地址生成器。地址发生器包括移位寄存器装置。移位寄存器包括n位位置。 n位位置用于存储n位。 n位能够处于多个模式。地址发生器还包括耦合到移位寄存器装置的计数器。计数器包括响应于多个模式的特定模式而递增的值。地址发生器具有耦合到移位寄存器和计数器的补码机制，该计数器响应于计数器中的值提供存储在n位位置中的n位的至少一部分的补码。在另一方面，该方法和系统包括先前讨论的地址生成器，其耦合到正在进行测试的存储器。在这方面，该方法和系统还具有耦合到地址发生器和存储器的数据发生器，以及耦合到存储器和数据发生器的比较电路。在这方面，当来自数据发生器的数据与存储在存储器中的数据不匹配时，检测到故障。

16. 发明授权

US4089100A Method and apparatus for installing a cutterhead upon a box hole boring machine 失效
标题翻译：将刀架安装在箱孔钻孔机上的方法和装置
公开(公告)号：US4089100A
公开(公告)日：1978-05-16
申请号：US602775
申请日：1975-08-07
申请人： Robert W. Berry, Jr.
发明人： Robert W. Berry, Jr.
IPC分类号： E21B19/18 , B23P19/04 , B60P1/02
CPC分类号： E21B19/18 , Y10T29/49826
摘要： In order to install a heavy cutterhead upon a box hole boring machine, within the confined working space available in underground mining operations, the cutterhead is placed upon a wheeled dolly having a central opening through which the attachment stem of the cutterhead depends downwardly, a temporary bridge including a pair of rails is rested upon the top of the machine frame, and the dolly with cutterhead supported thereon is moved along the bridge to a position where the cutterhead can be attached to the machine. The vertical drive of the machine is then utilized to lift the cutterhead, and the dolly and temporary bridge are removed.
摘要翻译：为了在箱孔钻孔机上安装一个重的刀架，在地下采矿作业中可用的密闭工作空间内，刀盘放置在一个带有中心开口的轮式小车上，刀架的附件杆通过该中心开口向下，临时包括一对轨道的桥梁搁置在机架的顶部，并且支撑在其上的刀架的台车沿着桥移动到刀盘可以附接到机器的位置。然后利用机器的垂直驱动来抬起刀架，并移除小车和临时桥。

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