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11. 发明授权

US5488015A Method of making an interconnect structure with an integrated low density dielectric 失效
标题翻译：制造具有集成低密度电介质的互连结构的方法
公开(公告)号：US5488015A
公开(公告)日：1996-01-30
申请号：US246432
申请日：1994-05-20
申请人： Robert H. Havemann , Shin-Puu Jeng , Bruce E. Gnade , Chih-Chen Cho
发明人： Robert H. Havemann , Shin-Puu Jeng , Bruce E. Gnade , Chih-Chen Cho
IPC分类号： H01L21/314 , H01L21/316 , H01L21/768 , H01L23/522 , H01L23/528 , H01L23/532 , H01L21/441 , H01L21/469
CPC分类号： H01L21/02362 , H01L21/02123 , H01L21/02126 , H01L21/02203 , H01L21/02216 , H01L21/02282 , H01L21/02359 , H01L21/31695 , H01L21/7682 , H01L21/76829 , H01L21/76834 , H01L23/5222 , H01L23/5226 , H01L23/5283 , H01L23/5329 , H01L2221/1047 , H01L2924/0002 , Y10S148/043 , Y10S148/118
摘要： This invention provides a semiconductor device and process for making the same with dramatically reduced capacitance between adjacent conductors and an interlayer dielectric construction which emphasizes mechanical strength, etch compatibility, and good heat transfer. This process can include applying a solution between conductors 24, and then gelling, surface modifying, and drying the solution to form an extremely porous dielectric layer 28. A non-porous dielectric layer 30 may be formed over porous layer 28, which may complete an interlayer dielectric and provide mechanical strength, heat transfer, and a solid layer for via etch. A novel process for creating the porous dielectric layer is disclosed, which can be completed at vacuum or ambient pressures, yet results in porosity, pore size, and shrinkage of the dielectric during drying comparable to that previously attainable only by drying gels at supercritical pressure.
摘要翻译：本发明提供了一种半导体器件及其制造方法，其显着降低了相邻导体之间的电容，以及强调机械强度，蚀刻兼容性和良好热传递的层间电介质结构。该方法可以包括在导体24之间施加溶液，然后将溶液凝胶化，表面改性和干燥以形成极其多孔的介电层28.多孔介质层30可形成在多孔层28之上，多孔层28可以完成层间电介质，并提供机械强度，热传递和用于通孔蚀刻的固体层。公开了一种用于产生多孔介电层的新方法，其可以在真空或环境压力下完成，但是在干燥期间导致电介质的孔隙率，孔径和收缩相当于仅通过在超临界压力下干燥凝胶可获得的电介质层。

12. 发明授权

US5403759A Method of making thin film transistor and a silicide local interconnect 失效
标题翻译：制造薄膜晶体管和硅化物局部互连的方法
公开(公告)号：US5403759A
公开(公告)日：1995-04-04
申请号：US955942
申请日：1992-10-02
申请人： Robert H. Havemann
发明人： Robert H. Havemann
IPC分类号： H01L21/768 , H01L27/11 , H01L21/265
CPC分类号： H01L27/1108 , H01L21/76889 , H01L21/76895 , Y10S257/903
摘要： A method of fabricating a transistor on a wafer including; forming a doped transistor body 42 on top of an insulator 34; doping source/drain regions in the transistor body; forming a gate oxide 44 on top of the transistor body; forming sidewall spacers along the transistor body; depositing a metal layer over the transistor body; forming an amorphous silicon layer over the metal layer, the amorphous silicon layer patterned in a gate and a local interconnect configuration; annealing to form silicided regions above the source/drain regions within the transistor body, and where the metal layer reacts with the amorphous silicon layer to create a silicided gate 50 and a silicided local interconnect 50; and etching unsilicided portions of the metal layer to leave silicided source/drain regions, a silicided gate, and a silicided local interconnect.
摘要翻译：一种在晶片上制造晶体管的方法，包括：在绝缘体34的顶部上形成掺杂晶体管体42; 晶体管体中的掺杂源极/漏极区域; 在晶体管本体的顶部形成栅极氧化物44; 沿着晶体管本体形成侧壁间隔物; 在所述晶体管本体上沉积金属层; 在所述金属层上形成非晶硅层，所述非晶硅层以栅极和局部互连配置构图; 退火以在晶体管体内的源极/漏极区之上形成硅化物区域，并且其中金属层与非晶硅层反应以产生硅化栅极50和硅化局部互连50; 并且蚀刻金属层的非硅化部分以留下硅化物源极/漏极区域，硅化栅极和硅化局部互连。

13. 发明授权

US5395798A Refractory metal silicide deposition process 失效
$Refractory metal silicide deposition process$
标题翻译：耐火金属硅化物沉积工艺
公开(公告)号：US5395798A
公开(公告)日：1995-03-07
申请号：US812241
申请日：1991-12-19
申请人： Robert H. Havemann
发明人： Robert H. Havemann
IPC分类号： H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L21/441
CPC分类号： H01L21/28518 , H01L21/76838 , Y10S148/147
摘要： A method for forming a refractory metal silicide on a semiconductor device is disclosed. The method comprises the steps of depositing a layer of refractory metal on the device and reacting the layer with nitrogen. The reaction is accomplished at a partial pressure of nitrogen greater than one atmosphere. The disclosed process allows thin layers of low resistance silicide to be formed for use as an ohmic contact while also forming a nitride layer for use as a device-to-device interconnection.
摘要翻译：公开了一种在半导体器件上形成难熔金属硅化物的方法。该方法包括以下步骤：在该装置上沉积难熔金属层并使该层与氮反应。反应在大于1个大气压的氮气分压下完成。所公开的方法允许形成薄层的低电阻硅化物以用作欧姆接触，同时还形成用作器件到器件互连的氮化物层。

14. 发明授权

US5252502A Method of making MOS VLSI semiconductor device with metal gate 失效
标题翻译：制造具有金属栅极的MOS VLSI半导体器件的方法
公开(公告)号：US5252502A
公开(公告)日：1993-10-12
申请号：US924209
申请日：1992-08-03
申请人： Robert H. Havemann
发明人： Robert H. Havemann
IPC分类号： H01L21/336 , H01L29/423 , H01L21/265 , H01L21/44
CPC分类号： H01L29/66757 , H01L29/42384
摘要： This is a method of fabricating a transistor on a wafer. The method comprises: forming an oxide layer 40 on a doped silicon layer 32; depositing a first resist over the oxide 40 and patterning the resist with a gate oxide configuration having a predetermined gate oxide length; etching to remove portions of the oxide layer 40 to expose portions of the silicon layer 32 using the resist as a mask; depositing a metal layer 42 over remaining portions of the oxide layer and exposed portions of the silicon layer; annealing the wafer to react portions of the metal layer with exposed portions of the silicon layer to form a metal silicide 44; depositing a second resist over the metal and patterning the second resist with a gate configuration having a gate length A smaller than the gate oxide length B; etching the metal to form a metal gate 42 and exposing portions of gate oxide; and implanting dopant adjacent the gate through the exposed gate oxide to provide source/drain regions 38 aligned to edges of the gate, utilizing the metal gate 42 as a mask to substantially prevent doping underneath the gate, whereby the gate need not be precisely centered on the gate oxide and thus difficulties in alignment are substantially eliminated.
摘要翻译：这是在晶片上制造晶体管的方法。该方法包括：在掺杂硅层32上形成氧化物层40; 在氧化物40上沉积第一抗蚀剂，并以具有预定栅极氧化物长度的栅极氧化物构型图案化抗蚀剂; 蚀刻以除去氧化物层40的部分，以使用抗蚀剂作为掩模来露出硅层32的部分; 在氧化物层的剩余部分和硅层的暴露部分上沉积金属层42; 退火晶片以使金属层的部分与硅层的暴露部分反应以形成金属硅化物44; 在所述金属上沉积第二抗蚀剂并且以栅极长度A小于所述栅极氧化物长度B的栅极配置图案化所述第二抗蚀剂; 蚀刻金属以形成金属栅极42并暴露栅极氧化物的部分; 以及通过所述暴露的栅极氧化物在所述栅极附近注入掺杂剂以提供与所述栅极的边缘对准的源极/漏极区域38，利用所述金属栅极42作为掩模，以基本上防止在所述栅极下面的掺杂，由此所述栅极不需要精确地居中在栅极氧化物因此基本上消除了对准困难。

15. 发明授权

US4635344A Method of low encroachment oxide isolation of a semiconductor device 失效
标题翻译：半导体器件的低侵蚀氧化物隔离方法
公开(公告)号：US4635344A
公开(公告)日：1987-01-13
申请号：US642320
申请日：1984-08-20
申请人： Robert H. Havemann
发明人： Robert H. Havemann
IPC分类号： H01L21/76 , H01L21/316 , H01L21/762
CPC分类号： H01L21/02238 , H01L21/02255 , H01L21/02299 , H01L21/31662 , H01L21/76213
摘要： A low temperature, low encroachment isolation technique using differential oxidation results in an isolated semiconductor body having an N+ substrate (12) and an N epi layer (14) forming a mesa. N+ implants (22a) and (22b) are implanted on opposite sides of the mesa. Oxide is grown over the surface of the device with differential oxidation thus resulting in thick regions (24) over the N+ dopant regions and a thin region (26) over the undopant mesa region.
摘要翻译：使用差分氧化的低温，低侵入隔离技术导致具有形成台面的N +衬底（12）和N外延层（14）的隔离半导体本体。 N +植入物（22a）和（22b）植入台面的相对侧。氧化物在器件的表面上生长，具有差异氧化，从而在N +掺杂剂区域上形成厚区域（24），在未掺杂的台面区域上形成薄的区域（26）。

16. 发明授权

US06844258B1 Selective refractory metal and nitride capping 有权
$Selective refractory metal and nitride capping$
标题翻译：选择性难熔金属和氮化物封盖
公开(公告)号：US06844258B1
公开(公告)日：2005-01-18
申请号：US10435010
申请日：2003-05-09
申请人： James A. Fair , Robert H. Havemann , Jungwan Sung , Nerissa Taylor , Sang-Hyeob Lee , Mary Anne Plano
发明人： James A. Fair , Robert H. Havemann , Jungwan Sung , Nerissa Taylor , Sang-Hyeob Lee , Mary Anne Plano
IPC分类号： H01L21/285 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/76856 , H01L21/28556 , H01L21/28562 , H01L21/76849 , H01L21/76867 , H01L21/76883 , H01L21/76889
摘要： A method for creating a refractory metal and refractory metal nitride cap effective for reducing copper electromigration and copper diffusion is described. The method includes depositing a refractory metal nucleation layer and nitriding at least the upper portion of the refractory metal layer to form a refractory metal nitride. Methods to reduce and clean the copper lines before refractory metal deposition are also described. Methods to form a thicker refractory metal layer using bulk deposition are also described.
摘要翻译：描述了一种用于制造有效减少铜电迁移和铜扩散的难熔金属和难熔金属氮化物盖的方法。该方法包括沉积难熔金属成核层并至少氮化至难熔金属层的上部以形成难熔金属氮化物。还描述了在难熔金属沉积之前减少和清洁铜线的方法。还描述了使用体积沉积形成较厚难熔金属层的方法。

17. 发明授权

US06677188B1 Methods for forming a fuse in a semiconductor device 有权
标题翻译：在半导体器件中形成熔丝的方法
公开(公告)号：US06677188B1
公开(公告)日：2004-01-13
申请号：US10188528
申请日：2002-07-03
申请人： Robert H. Havemann
发明人： Robert H. Havemann
IPC分类号： H01L2182
CPC分类号： H01L23/53238 , H01L23/5258 , H01L27/10897 , H01L2924/0002 , H01L2924/00
摘要： According to one embodiment of the invention, a method is provided. The method includes lining, with a conductive liner, a surface of a dielectric layer. The surface defines at least two trenches separated by a platform. Each of the defined trenches includes a conductor that overlies the conductive liner and is positioned within the each of the defined trenches. The conductor is electrically coupled to the conductive liner. The method also includes covering the portion of the conductive liner overlying the platform after lining the surface. The method also includes removing any uncovered portions of the conductive liner while leaving in place the portion of the conductive liner that was covered.
摘要翻译：根据本发明的一个实施例，提供了一种方法。该方法包括用导电衬垫衬里介电层的表面。表面限定了由平台隔开的至少两个沟槽。每个限定的沟槽包括覆盖导电衬垫并且定位在每个限定沟槽内的导体。导体电耦合到导电衬垫。该方法还包括在衬套表面之后覆盖覆盖平台的导电衬垫的部分。该方法还包括移除导电衬套的任何未覆盖部分，同时留下被覆盖的导电衬垫的部分。

18. 发明授权

US06261915B1 Process of making polysilicon resistor 失效
标题翻译：制造多晶硅电阻的工艺
公开(公告)号：US06261915B1
公开(公告)日：2001-07-17
申请号：US08247910
申请日：1994-05-23
申请人： Robert H. Eklund , Robert H. Havemann , Leo Stroth
发明人： Robert H. Eklund , Robert H. Havemann , Leo Stroth
IPC分类号： H01L213213
CPC分类号： H01L28/20
摘要： A method of forming an integrated circuit device including at least one polysilicon resistor 10 is disclosed herein. A polysilicon layer 24 is formed, possibly over a field oxide 12. The polysilicon layer 24 is then doped to achieve a selected sheet resistance. An insulating layer 18 (e.g., an oxide, a nitride, or a combination thereof) is then formed over the polysilicon layer 24. The insulating layer 18 is patterned and etched to define a resistor body 14 in the underlying polysilicon layer 24. The polysilicon layer 24 is then patterned and etched to define first and second resistor heads 16 abutting the resistor body 14 while simultaneously at least one polysilicon element 28 of a second electronic device is formed. Other systems and methods are also disclosed.
摘要翻译：本文公开了一种形成包括至少一个多晶硅电阻器10的集成电路器件的方法。形成多晶硅层24，可能在场氧化物12上方。然后掺杂多晶硅层24以获得选定的薄层电阻。然后在多晶硅层24上形成绝缘层18（例如，氧化物，氮化物或其组合）。图案化和蚀刻绝缘层18以在下面的多晶硅层24中限定电阻体14。然后对层24进行构图和蚀刻以限定邻接电阻体14的第一和第二电阻头16，同时形成第二电子器件的至少一个多晶硅元件28。还公开了其它系统和方法。

19. 发明授权

US06248638B1 Enhancements to polysilicon gate 有权
标题翻译：增强多晶硅门
公开(公告)号：US06248638B1
公开(公告)日：2001-06-19
申请号：US09262512
申请日：1999-03-04
申请人： Robert H. Havemann
发明人： Robert H. Havemann
IPC分类号： H01L213205
CPC分类号： H01L29/6659 , H01L21/28052 , H01L21/2807 , H01L21/28105 , H01L29/4983 , H01L29/665
摘要： The conductivity of gate structures can be improved by siliciding the entire gate. Additionally, silicon sidewalls can be added to the gate after the “smiling” oxidation, but before silicidation, which provides a new tool for drain profile engineering.
摘要翻译：通过硅化整个栅极可以提高栅极结构的导电性。此外，在“微笑”氧化之后，但在硅化之前，硅侧壁可以添加到栅极，这为漏极轮廓工程提供了新的工具。

20. 发明授权

US5668398A Multilevel interconnect structure with air gaps formed between metal leads 失效
标题翻译：金属引线之间形成气隙的多层互连结构
公开(公告)号：US5668398A
公开(公告)日：1997-09-16
申请号：US631437
申请日：1996-04-12
申请人： Robert H. Havemann , Shin-puu Jeng
发明人： Robert H. Havemann , Shin-puu Jeng
IPC分类号： H01L21/316 , H01L21/768 , H01L23/522 , H01L29/40
CPC分类号： H01L21/31695 , H01L21/02126 , H01L21/02203 , H01L21/02282 , H01L21/02304 , H01L21/02337 , H01L21/02362 , H01L21/7682 , H01L23/5222 , H01L2924/0002
摘要： A semiconductor device with air gaps 22 between metal leads 16, comprising metal leads 16 formed on a substrate 12, air gaps 22 between metal leads 16, a 10-50% porous dielectric layer 20 on the metal leads 16 and over the air gaps 22, and a non-porous dielectric layer 24 on the porous dielectric layer 20. Optional features include a patterned oxide 28 over the metal leads 16 and a passivation layer 26 over the metal leads 16 and patterned oxide 28. The porous dielectric layer 20 may comprise an aerogel or xerogel.
摘要翻译：在金属引线16之间具有气隙22的半导体器件，包括形成在基底12上的金属引线16，金属引线16之间的气隙22，金属引线16上的10-50％多孔电介质层20和气隙22之上以及多孔电介质层20上的无孔电介质层24.可选特征包括在金属引线16上的图案化氧化物28以及在金属引线16和图案化氧化物28上的钝化层26.多孔介电层20可以包括气凝胶或干凝胶。

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