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11. 发明申请

US20080258182A1 Bicmos Compatible Jfet Device and Method of Manufacturing Same 审中-公开
标题翻译： Bicmos兼容Jfet设备及其制造方法相同
公开(公告)号：US20080258182A1
公开(公告)日：2008-10-23
申请号：US11577311
申请日：2005-10-13
申请人： Prabhat Agarwal , Jan W. Slotboom , Wibo Van Noort
发明人： Prabhat Agarwal , Jan W. Slotboom , Wibo Van Noort
IPC分类号： H01L29/808 , H01L21/8232 , H01L21/337
CPC分类号： H01L27/098 , H01L21/8248 , H01L27/0623
摘要： A BiCMOS-compatible JFET device comprising source and drain regions (17, 18) which are formed in the same process as that used to form the emitter out-diffusion or a vertical bipolar device, wherein the semiconductor layer which forms the emitter cap in the bipolar device forms the channel (16) of the JFET device and the layer of material (i.e. the base epi-stack) which forms the intrinsic base region of the bipolar device forms the intrinsic gate region (14) of the JFET device. As a result, the integration of the JFET device into a standard BiCMOS process can be achieved without the need for any additional masking or other processing steps.
摘要翻译：一种BiCMOS兼容的JFET器件，包括以与用于形成发射极外扩散的相同的工艺形成的源极和漏极区域（17,18），或者垂直双极器件，其中形成发光极帽的半导体层双极器件形成JFET器件的沟道（16），并且形成双极器件的本征基极区域的材料层（即，基极外延堆叠）形成JFET器件的本征栅极区域（14）。结果，可以实现JFET器件到标准BiCMOS工艺的集成，而不需要任何额外的掩模或其他处理步骤。

12. 发明申请

US20080203434A1 Semiconductor Device with a Bipolar Transistor and Method of Manufacturing Such a Device 有权
标题翻译：具有双极晶体管的半导体器件及其制造方法
公开(公告)号：US20080203434A1
公开(公告)日：2008-08-28
申请号：US12088719
申请日：2006-09-22
申请人： Philippe Meunier-Beillard , Raymond James Duffy , Prabhat Agarwal , Godfridus Adrianus Maria Hurkx
发明人： Philippe Meunier-Beillard , Raymond James Duffy , Prabhat Agarwal , Godfridus Adrianus Maria Hurkx
IPC分类号： H01L29/737 , H01L21/331
CPC分类号： H01L29/7378 , H01L29/0817 , H01L29/66242
摘要： The invention relates to a semiconductor device (10) with a substrate and a semiconductor body of silicon comprising a bipolar transistor with an emitter region (1), a base region (2) and a collector region (3) which are respectively of the N-type conductivity, the P-type conductivity and the N-type conductivity by the provision of suitable doping atoms, wherein the base region (2) comprises a mixed crystal of silicon and germanium, the base region (2) is separated from the emitter region by an intermediate region (22) of silicon having a doping concentration which is lower than the doping concentration of the emitter region (1) and with a thickness smaller than the thickness of the emitter region (1) and the emitter region (1) comprises a sub-region comprising a mixed crystal of silicon and germanium which is positioned at the side of emitter region (1) remote from the intermediate region (22). According to the invention, the sub-region comprising the mixed crystal of silicon and germanium extend substantially through the whole emitter region (1) up to the interlace with the intermediate region (22) and the doping atoms of the emitter region (1) are arsenic atoms. Such a device has a very steep n-type doping profile (50) and a very steep p-type doping profile (20) at or within the intermediate region (22) and thus excellent high-frequency behavior with a high cut-off frequency (fr). Preferably the emitter region (1) is doped with an arsenic implantation (I) in its upper half, the final doping profile being formed after an RTA. The invention also comprises a method of manufacturing a device (10) according to the invention.
摘要翻译：本发明涉及一种具有衬底和硅半导体本体的半导体器件（10），其包括具有发射极区（1），基极区（2）和集电极区（3）的双极晶体管，所述发射极区分别为N 通过提供合适的掺杂原子，P型导电性和N型导电性，其中基区（2）包括硅和锗的混合晶体，基极区（2）与发射极分离通过具有低于发射极区域（1）的掺杂浓度的掺杂浓度并且具有小于发射极区域（1）和发射极区域（1）的厚度的厚度的硅的中间区域（22）包括位于远离中间区域（22）的发射极区域（1）侧的硅和锗的混合晶体的子区域。根据本发明，包括硅和锗的混合晶体的子区域基本上延伸穿过整个发射极区域（1）直到与中间区域（22）交错，并且发射极区域（1）的掺杂原子是砷原子这种器件在中间区域（22）处或中间区域（22）内具有非常陡峭的n型掺杂分布（50）和非常陡的p型掺杂分布（20），因此具有高截止频率的极好的高频特性（fr）。优选地，发射极区域（1）在其上半部分掺杂有砷注入（I），最后的掺杂分布在RTA之后形成。本发明还包括一种制造根据本发明的装置（10）的方法。

13. 发明申请

US20080144355A1 Dielectric Antifuse for Electro-Thermally Programmable Device 有权
标题翻译：电热可编程器件介质防腐剂
公开(公告)号：US20080144355A1
公开(公告)日：2008-06-19
申请号：US11720320
申请日：2005-11-24
申请人： Hans M.B. Boeve , Karen Attenborough , Godefridus A.M. Hurkx , Prabhat Agarwal , Hendrik G.A. Huizing , Michael A.A. In'T Zandt , Jan W. Slotboom
发明人： Hans M.B. Boeve , Karen Attenborough , Godefridus A.M. Hurkx , Prabhat Agarwal , Hendrik G.A. Huizing , Michael A.A. In'T Zandt , Jan W. Slotboom
IPC分类号： G11C17/18 , G11C11/00 , H01L21/326 , H01L29/02
CPC分类号： G11C11/5678 , G11C13/0004 , H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/144
摘要： A thermally programmable memory has a programmable element (20) of a thermally programmable resistance preferably of phase change material, material and a blown antifuse (80) located adjacent to the programmable material. Such a blown antifuse has a dielectric layer (100) surrounded by conductive layers (90, 110) to enable a brief high voltage to be applied across the dielectric to blow a small hole in the dielectric during manufacture to form a small conductive path which can be used as a tiny electrical heater for programming the material. Due to the current confinement by the hole, the volume of the material that must be heated in order to switch to a highly-resistive state is very small. As a result the programming power can be low.
摘要翻译：热可编程存储器具有可编程电阻的可编程电阻（20），优选地是相变材料的材料和位于可编程材料附近的吹制反熔丝（80）。这种吹制的反熔丝具有由导电层（90,110）包围的电介质层（100），以使得能够在制造期间在电介质两端施加短暂的高电压来吹动电介质中的小孔，以形成小导电路径，用作编程材料的微小电加热器。由于目前由孔的限制，为了切换到高电阻状态必须被加热的材料的体积非常小。因此，编程功率可能很低。

14. 发明申请

US20070279091A1 Digital Voltage Level Shifter 审中-公开
标题翻译：数字电压电平变换器
公开(公告)号：US20070279091A1
公开(公告)日：2007-12-06
申请号：US11663406
申请日：2004-09-22
申请人： Mayank Goel , Prabhat Agarwal
发明人： Mayank Goel , Prabhat Agarwal
IPC分类号： H03K3/356
CPC分类号： H03K3/356147 , H03K17/102
摘要： A digital voltage level shifter for converting an input signal with a low voltage swing to an output signal with a high voltage swing comprises a first inverter stage for generating an inverted signal from an input signal, the inverted signal having a voltage swing between a core voltage and ground, and a second inverter stage for producing an anti-phase signal from the inverted input signal, the anti-phase signal having a voltage swing between the core voltage and ground. The first and second inverters each drive a respective thin gate NMOS transistor connected in cascode with a respective NMOS transistor. The sources of the first and second thin gate NMOS transistors are connected to ground. The gates of the NMOS transistors are connected to the output of the respective inverters through a respective capacitor and are referenced to the core voltage through a respective resistor. The drains of the NMOS transistors are connected to an output circuit to provide an output signal having a voltage higher than the core voltage.
摘要翻译：用于将具有低电压摆幅的输入信号转换为具有高电压摆幅的输出信号的数字电压电平移位器包括用于从输入信号产生反相信号的第一反相器级，反相信号具有在核心电压以及用于从反相输入信号产生反相信号的第二反相器级，反相信号在核心电压和地之间具有电压摆幅。第一和第二反相器各自驱动以共源共栅连接的相应的薄栅极NMOS晶体管与相应的NMOS晶体管。第一和第二薄栅NMOS晶体管的源极连接到地。 NMOS晶体管的栅极通过相应的电容器连接到各个反相器的输出，并且通过相应的电阻器参考核心电压。 NMOS晶体管的漏极连接到输出电路，以提供具有高于核心电压的电压的输出信号。

15. 发明授权

US07839209B2 Tunnel field effect transistor 有权
标题翻译：隧道场效应晶体管
公开(公告)号：US07839209B2
公开(公告)日：2010-11-23
申请号：US12444140
申请日：2007-10-03
申请人： Gilberto Curatola , Prabhat Agarwal , Jan W. Slotboom , Godefridus A. M. Hurkx , Radu Surdeanu , Gerben Doornbos
发明人： Gilberto Curatola , Prabhat Agarwal , Jan W. Slotboom , Godefridus A. M. Hurkx , Radu Surdeanu , Gerben Doornbos
IPC分类号： H01L25/00
CPC分类号： H01L29/161 , H01L29/165 , H01L29/7391
摘要： A tunnel transistor includes source diffusion (4) of opposite conductivity type to a drain diffusion (6) so that a depletion layer is formed between source and drain diffusions in a lower doped region (8). An insulated gate (16) controls the position and thickness of the depletion layer. The device includes a quantum well formed in accumulation layer (20) which is made of a different material to the lower layer (2) and cap layer (22).
摘要翻译：隧道晶体管包括与漏扩散（6）相反的导电类型的源极扩散（4），使得在较低掺杂区域（8）中的源极和漏极扩散之间形成耗尽层。绝缘栅极（16）控制耗尽层的位置和厚度。该装置包括形成在由下层（2）和盖层（22）的不同材料制成的聚集层（20）中的量子阱。

16. 发明申请

US20100097135A1 TUNNEL FIELD EFFECT TRANSISTOR 有权
标题翻译：隧道场效应晶体管
公开(公告)号：US20100097135A1
公开(公告)日：2010-04-22
申请号：US12444140
申请日：2007-10-03
申请人： Gilberto Curatola , Prabhat Agarwal , Jan W. Slotboom , Godefridus A.M. Hurkx , Radu Surdeanu
发明人： Gilberto Curatola , Prabhat Agarwal , Jan W. Slotboom , Godefridus A.M. Hurkx , Radu Surdeanu
IPC分类号： H03K3/353 , H01L29/78
CPC分类号： H01L29/161 , H01L29/165 , H01L29/7391
摘要： A tunnel transistor includes source diffusion (4) of opposite conductivity type to a drain diffusion (6) so that a depletion layer is formed between source and drain diffusions in a lower doped region (8). An insulated gate (16) controls the position and thickness of the depletion layer. The device includes a quantum well formed in accumulation layer (20) which is made of a different material to the lower layer (2) and cap layer (22).
摘要翻译：隧道晶体管包括与漏扩散（6）相反的导电类型的源极扩散（4），使得在较低掺杂区域（8）中的源极和漏极扩散之间形成耗尽层。绝缘栅极（16）控制耗尽层的位置和厚度。该装置包括形成在由下层（2）和盖层（22）的不同材料制成的聚集层（20）中的量子阱。

17. 发明授权

US07671447B2 Bipolar transistor and method of manufacturing the same 有权
标题翻译：双极晶体管及其制造方法
公开(公告)号：US07671447B2
公开(公告)日：2010-03-02
申请号：US11632614
申请日：2005-07-07
申请人： Andreas Hubertus Montree , Jan Willem Slotboom , Prabhat Agarwal , Philippe Meunier-Beillard
发明人： Andreas Hubertus Montree , Jan Willem Slotboom , Prabhat Agarwal , Philippe Meunier-Beillard
IPC分类号： H01L23/58
CPC分类号： H01L29/7317 , H01L29/1004 , H01L29/365 , H01L29/66265 , H01L29/735 , H01L2924/0002 , H01L2924/00
摘要： The invention relates to a semiconductor device (10) with a semiconductor body (12) comprising a bipolar transistor with an emitter region (1), a base region (2) and a collector region (3) of, respectively, a first conductivity type, a second conductivity type, opposite to the first conductivity type, and the first conductivity type, wherein, viewed in projection, the emitter region (1) is positioned above or below the base region (2), and the collector region (3) laterally borders the base region (2). According to the invention, the base region (2) comprises a highly doped subregion (2A) the doping concentration of which has a delta-shaped profile in the thickness direction, and said highly doped sub-region (2A) extends laterally as far as the collector region (3). Such a lateral bipolar transistor has excellent high-frequency properties and a relatively high breakdown voltage between the base and collector regions (2, 3), implying that the device is suitable for high power applications. The doping concentration lies preferably between about 1019 and about 1020 at/cm3, and the thickness of the sub-region (2A) lies between 1 and 15 nm and preferably between 1 and 10 nm. The invention also comprises a method of manufacturing such a device (10).
摘要翻译：本发明涉及具有半导体本体（12）的半导体器件（10），该半导体器件（12）包括分别具有第一导电类型的发射极区域（1），基极区域（2）和集电极区域（3），与第一导电类型相反的第二导电类型和第一导电类型，其中，从投影中观察，发射极区域（1）位于基极区域（2）的上方或下方，并且集电极区域（3）横向地邻接基部区域（2）。根据本发明，基极区域（2）包括其掺杂浓度在厚度方向上具有δ形轮廓的高掺杂子区域（2A），并且所述高度掺杂子区域（2A）横向延伸至收集器区域（3）。这种横向双极晶体管在基极和集电极区域（2,3）之间具有优异的高频特性和较高的击穿电压，这意味着该器件适用于高功率应用。掺杂浓度优选介于约1019至约1020 at / cm3，子区（2A）的厚度在1至15nm之间，优选在1至10nm之间。本发明还包括制造这种装置（10）的方法。

18. 发明申请

US20090242964A1 NON-VOLATILE MEMORY DEVICE 有权
标题翻译：非易失性存储器件
公开(公告)号：US20090242964A1
公开(公告)日：2009-10-01
申请号：US12298267
申请日：2007-04-19
申请人： Nader Akil , Prabhat Agarwal , Robertus T.F. Van Schaijk
发明人： Nader Akil , Prabhat Agarwal , Robertus T.F. Van Schaijk
IPC分类号： H01L29/792 , H01L21/336 , H01L21/782
CPC分类号： H01L29/4234 , H01L21/28282 , H01L29/66787 , H01L29/66833 , H01L29/792
摘要： A finFET-based non-volatile memory device on a semiconductor substrate includes source and drain regions, a fin body, a charge trapping stack and a gate. The fin body extends between the source and the drain region as a connection. The charge trapping stack covers a portion of the fin body and the gate covers the charge trapping stack at the location of the fin body. The fin body has a corner-free shape for at least ¾ of the circumference of the fin body which lacks distinct crystal faces and transition zones in between the crystal faces.
摘要翻译：半导体衬底上的基于finFET的非易失性存储器件包括源区和漏区，翅片体，电荷俘获堆和栅极。翅片体作为连接在源极和漏极区域之间延伸。电荷捕获堆叠覆盖翅片体的一部分，并且栅极在翅片体的位置处覆盖电荷捕获堆叠。翅片体具有无角形的形状，用于在翅片体的周边的至少3/4处，其在晶面之间缺少明显的晶面和过渡区。

19. 发明申请

US20090146068A1 RADIATION DOSIMETER 审中-公开
标题翻译：辐射剂量计
公开(公告)号：US20090146068A1
公开(公告)日：2009-06-11
申请号：US11719550
申请日：2005-11-17
申请人： Prabhat Agarwal
发明人： Prabhat Agarwal
IPC分类号： G01T1/24
CPC分类号： G01T1/026 , G01T1/2018 , G01T1/245
摘要： A personal X-ray dosimeter system, comprising a portable detector (100) and a reader device (114). The portable detector (100) comprises an array (104) of programmed non-volatile memory elements (102) and a scintillator element (106) for converting a portion of X-radiation incident thereon to UV radiation. As a result of exposure to X-radiation (112) not converted to UV radiation, some of the memory elements (102) will have the charge on their floating gates, thereby causing a corresponding shift in threshold voltage (VT). After some exposure time, the reader device (114) reads from the detector (100) data representative of the number of VT shifted memory elements (102), and determines therefrom using predetermined calibration curves, the radiation dose (122) to which the user has been exposed.
摘要翻译：一种个人X射线剂量计系统，包括便携式检测器（100）和读取器装置（114）。便携式检测器（100）包括编程的非易失性存储元件（102）的阵列（104）和用于将入射到其上的X射线的一部分转换为紫外线辐射的闪烁器元件（106）。作为未被转换成UV辐射的X辐射（112）的结果，一些存储元件（102）将在其浮动栅极上具有电荷，从而导致阈值电压（VT）的相应偏移。在一些曝光时间之后，读取器设备（114）从检测器（100）读取表示VT移位存储器元件（102）的数量的数据，并且使用预定的校准曲线来确定用户的辐射剂量（122）已经曝光

20. 发明申请

US20090008630A1 TUNNELING TRANSISTOR WITH BARRIER 有权
标题翻译：具有障碍物的隧道式晶体管
公开(公告)号：US20090008630A1
公开(公告)日：2009-01-08
申请号：US12161571
申请日：2007-01-24
申请人： Godefridus Adrianus Maria Hurkx , Prabhat Agarwal
发明人： Godefridus Adrianus Maria Hurkx , Prabhat Agarwal
IPC分类号： H01L29/06
CPC分类号： H01L29/1054 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/068 , H01L29/47 , H01L29/66666 , H01L29/78 , H01L29/7827 , Y10S977/762 , Y10S977/938
摘要： The invention suggests a transistor (21) comprising a source (24) and a drain (29) as well as a barrier region (27) located between the source and the drain. The barrier region is separated from the source and the drain by intrinsic or lowly doped regions (26, 28) of a semiconductor material. Potential barriers are formed at the interfaces of the barrier region and the intrinsic or lowly doped regions. A gate electrode (32) is provided in the vicinity of the potential barriers such that the effective height and/or width of the potential barriers can be modulated by applying an appropriate voltage to the gate electrode.
摘要翻译：本发明提出了一种包括源极（24）和漏极（29）的晶体管（21）以及位于源极和漏极之间的阻挡区域（27）。通过半导体材料的本征或低掺杂区域（26,28）将势垒区域与源极和漏极分离。在屏障区域和本征或低掺杂区域的界面处形成势垒。栅电极（32）设置在势垒附近，使得可以通过向栅电极施加适当的电压来调制势垒的有效高度和/或宽度。

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