专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20090242964A1 NON-VOLATILE MEMORY DEVICE 有权
标题翻译：非易失性存储器件
公开(公告)号：US20090242964A1
公开(公告)日：2009-10-01
申请号：US12298267
申请日：2007-04-19
申请人： Nader Akil , Prabhat Agarwal , Robertus T.F. Van Schaijk
发明人： Nader Akil , Prabhat Agarwal , Robertus T.F. Van Schaijk
IPC分类号： H01L29/792 , H01L21/336 , H01L21/782
CPC分类号： H01L29/4234 , H01L21/28282 , H01L29/66787 , H01L29/66833 , H01L29/792
摘要： A finFET-based non-volatile memory device on a semiconductor substrate includes source and drain regions, a fin body, a charge trapping stack and a gate. The fin body extends between the source and the drain region as a connection. The charge trapping stack covers a portion of the fin body and the gate covers the charge trapping stack at the location of the fin body. The fin body has a corner-free shape for at least ¾ of the circumference of the fin body which lacks distinct crystal faces and transition zones in between the crystal faces.
摘要翻译：半导体衬底上的基于finFET的非易失性存储器件包括源区和漏区，翅片体，电荷俘获堆和栅极。翅片体作为连接在源极和漏极区域之间延伸。电荷捕获堆叠覆盖翅片体的一部分，并且栅极在翅片体的位置处覆盖电荷捕获堆叠。翅片体具有无角形的形状，用于在翅片体的周边的至少3/4处，其在晶面之间缺少明显的晶面和过渡区。

2. 发明授权

US08159018B2 Non-volatile memory device 有权
标题翻译：非易失性存储器件
公开(公告)号：US08159018B2
公开(公告)日：2012-04-17
申请号：US12298267
申请日：2007-04-19
申请人： Nader Akil , Prabhat Agarwal , Robertus T. F. Van Schaijk
发明人： Nader Akil , Prabhat Agarwal , Robertus T. F. Van Schaijk
IPC分类号： H01L29/792 , H01L21/336 , H01L21/8239 , H01L21/8246 , H01L21/84
CPC分类号： H01L29/4234 , H01L21/28282 , H01L29/66787 , H01L29/66833 , H01L29/792
摘要： A finFET-based non-volatile memory device on a semiconductor substrate includes source and drain regions, a fin body, a charge trapping stack and a gate. The fin body extends between the source and the drain region as a connection. The charge trapping stack covers a portion of the fin body and the gate covers the charge trapping stack at the location of the fin body. The fin body has a corner-free shape for at least ¾ of the circumference of the fin body which lacks distinct crystal faces and transition zones in between the crystal faces.
摘要翻译：半导体衬底上的基于finFET的非易失性存储器件包括源区和漏区，翅片体，电荷俘获堆和栅极。翅片体作为连接在源极和漏极区域之间延伸。电荷捕获堆叠覆盖翅片体的一部分，并且栅极在翅片体的位置处覆盖电荷捕获堆叠。翅片体具有无角形的形状，用于在翅片体的周边的至少3/4处，其在晶面之间缺少明显的晶面和过渡区。

3. 发明授权

US07915709B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07915709B2
公开(公告)日：2011-03-29
申请号：US11658228
申请日：2005-07-07
申请人： Godefridus Adrianus Maria Hurkx , Prabhat Agarwal , Abraham Rudolf Balkenende , Petrus Hubertus Cornelis Magnee , Melanie Maria Hubertina Wagemans , Erik Petrus Antonius Maria Bakkers , Erwin Hijzen
发明人： Godefridus Adrianus Maria Hurkx , Prabhat Agarwal , Abraham Rudolf Balkenende , Petrus Hubertus Cornelis Magnee , Melanie Maria Hubertina Wagemans , Erik Petrus Antonius Maria Bakkers , Erwin Hijzen
IPC分类号： H01L29/66 , H01L21/8222
CPC分类号： H01L29/0804 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/0821 , H01L29/7378 , Y10S977/936
摘要： The invention relates to a semiconductor device (10) with a semiconductor body (12) comprising a bipolar transistor with an emitter region, a base region and a collector region (1, 2, 3) of, respectively, a first conductivity type, a second conductivity type opposite to the first conductivity type, and the first conductivity type. One of the emitter or collector regions (1, 3) comprises a nanowire (30). The base region (2) has been formed from a layer (20) at the surface of the semiconductor body (12); the other one (3, 1) of the emitter or collector regions (1, 3) has been formed in the semiconductor body (12) below the base region (2). The emitter or collector region (1, 3) comprising the nanowire (30) has been provided on the surface of the semiconductor body (12) such that its longitudinal axis extends perpendicularly to the surface.
摘要翻译：本发明涉及具有半导体本体（12）的半导体器件（10），该半导体器件（12）包括分别具有第一导电类型的发射极区，基极区和集电极区（1,2,3）的双极晶体管，与第一导电类型相反的第二导电类型和第一导电类型。发射极或集电极区域（1,3）中的一个包括纳米线（30）。基底区域（2）由半导体本体（12）表面的层（20）形成; 发射极或集电极区域（1,3）中的另一个（3,1）已经形成在基极区域（2）下方的半导体本体（12）中。包括纳米线（30）的发射极或集电极区域（1,3）已经设置在半导体本体（12）的表面上，使得其纵向轴线垂直于该表面延伸。

4. 发明授权

US07791108B2 Nanowire tunneling transistor 失效
标题翻译：纳米线隧道晶体管
公开(公告)号：US07791108B2
公开(公告)日：2010-09-07
申请号：US12161574
申请日：2007-01-24
申请人： Fred Hurkx , Prabhat Agarwal
发明人： Fred Hurkx , Prabhat Agarwal
IPC分类号： H01L21/336 , H01L21/8235
CPC分类号： H01L29/1054 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/068 , H01L29/66666 , H01L29/7827 , Y10S977/75 , Y10S977/813 , Y10S977/938
摘要： A transistor comprises a nanowire (22, 22′) having a source (24) and a drain (29) separated by an intrinsic or lowly doped region (26, 28). A potential barrier is formed at the interface of the intrinsic or lowly doped region (26, 28) and one of the source (24) and the drain (29). A gate electrode (32) is provided in the vicinity of the potential barrier such that the height of the potential barrier can be modulated by applying an appropriate voltage to the gate electrode (32).
摘要翻译：晶体管包括具有由本征或低掺杂区域（26,28）分开的源极（24）和漏极（29）的纳米线（22,22'）。在本征或低掺杂区域（26,28）和源极（24）和漏极（29）中的一个的界面处形成势垒。在势垒附近设置栅电极（32），使得可以通过向栅极（32）施加适当的电压来调制势垒的高度。

5. 发明授权

US07538593B2 Circuit and method to convert a single ended signal to duplicated signals 有权
标题翻译：将单端信号转换为重复信号的电路和方法
公开(公告)号：US07538593B2
公开(公告)日：2009-05-26
申请号：US11710270
申请日：2007-02-23
申请人： Prabhat Agarwal , Mayank Goel , Pradip Mandal
发明人： Prabhat Agarwal , Mayank Goel , Pradip Mandal
IPC分类号： G06F1/04
CPC分类号： H03K5/151
摘要： A circuit to convert a single ended signal to differential signals is disclosed. The circuit has two paths with each of the two paths comprising a plurality of stages. The number of stages in each of the two paths is the same. A first path of the two paths includes a buffer stage and at least one inverter stage. A second path of the two paths includes at least two inverter stages. The buffer stage has a delay matched to that of a first inverter stage of the second path. The buffer stage comprises a first pair of transistors comprising a first transistor of a first category operatively connected to a first transistor of a second category with their channel connections being connected in series.
摘要翻译：公开了将单端信号转换为差分信号的电路。该电路具有两条路径，其中两条路径中的每条路径包括多个级。两个路径中的每个路段的数量是相同的。两个路径的第一路径包括缓冲段和至少一个逆变器级。两路径的第二路径包括至少两个逆变器级。缓冲级具有与第二路径的第一反相器级的延迟匹配的延迟。缓冲级包括第一对晶体管，其包括第一类别的第一晶体管，其可操作地连接到第二类别的第一晶体管，其沟道连接串联连接。

6. 发明申请

US20090008631A1 NANOWIRE TUNNELING TRANSISTOR 失效
标题翻译： NANOWIRE隧道晶体管
公开(公告)号：US20090008631A1
公开(公告)日：2009-01-08
申请号：US12161574
申请日：2007-01-24
申请人： Godefridus Andrianus Maria Hurkx , Prabhat Agarwal
发明人： Godefridus Andrianus Maria Hurkx , Prabhat Agarwal
IPC分类号： H01L29/06
CPC分类号： H01L29/1054 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/068 , H01L29/66666 , H01L29/7827 , Y10S977/75 , Y10S977/813 , Y10S977/938
摘要： A transistor comprises a nanowire (22, 22′) having a source (24) and a drain (29) separated by an intrinsic or lowly doped region (26, 28). A potential barrier is formed at the interface of the intrinsic or lowly doped region (26, 28) and one of the source (24) and the drain (29). A gate electrode (32) is provided in the vicinity of the potential barrier such that the height of the potential barrier can be modulated by applying an appropriate voltage to the gate electrode (32).
摘要翻译：晶体管包括具有由本征或低掺杂区域（26,28）分开的源极（24）和漏极（29）的纳米线（22,22'）。在本征或低掺杂区域（26,28）和源极（24）和漏极（29）中的一个的界面处形成势垒。在势垒附近设置栅电极（32），使得可以通过向栅极（32）施加适当的电压来调制势垒的高度。

7. 发明申请

US20090008566A1 GEIGER MODE AVALANCHE PHOTODIODE 有权
公开(公告)号：US20090008566A1
公开(公告)日：2009-01-08
申请号：US12162999
申请日：2007-01-17
申请人： Prabhat Agarwal , Jan Sonsky , Lasse Juhana Kauppinen
发明人： Prabhat Agarwal , Jan Sonsky , Lasse Juhana Kauppinen
IPC分类号： G01T1/24 , H01L31/107 , H01L31/18
CPC分类号： H01L27/14658 , H01L27/1464 , H01L27/14683 , H01L31/107
摘要： A avalanche mode photodiode array (102) is fabricated using a silicon on insulator wafer and substrate transfer process. The array includes a plurality of photodiodes (100). The photodiodes (100) include an electrically insulative layer (206), a depletion region (204), and first (208) and second (210) doped regions. An interconnection layer (212) includes electrodes (214, 216) which provides electrical connections to the photodiodes. The photodiode array (102) is carried by a handle wafer (217).
摘要翻译：使用绝缘体上硅晶片和衬底转移工艺制造雪崩模式光电二极管阵列（102）。阵列包括多个光电二极管（100）。光电二极管（100）包括电绝缘层（206），耗尽区（204）以及第一（208）和第二（210）掺杂区。互连层（212）包括提供到光电二极管的电连接的电极（214,216）。光电二极管阵列（102）由处理晶片（217）承载。

8. 发明申请

US20070262397A1 Nanoscale Fet 有权
标题翻译：纳米级食物
公开(公告)号：US20070262397A1
公开(公告)日：2007-11-15
申请号：US11632738
申请日：2005-07-12
申请人： Radu Surdeanu , Prabhat Agarwal , Abraham Balkenende , Erik Bakkers
发明人： Radu Surdeanu , Prabhat Agarwal , Abraham Balkenende , Erik Bakkers
IPC分类号： H01L29/775 , H01L21/336
CPC分类号： H01L29/78 , B82Y10/00 , B82Y40/00 , H01L29/0665 , H01L29/0673 , H01L29/20 , H01L29/76 , Y10S438/962 , Y10S977/762 , Y10S977/818 , Y10S977/938
摘要： A transistor device is formed of a continuous linear nanostructure having a source region, a drain region and a channel region between the source and drain regions. The source (20) and drain (26) regions are formed of nanowire ania the channel region (24) is in the form of a nanotube. An insulated gate (32) is provided adjacent to the channel region (24) for controlling conduction i ni the channel region between the source and drain regions.
摘要翻译：晶体管器件由具有源极区，漏极区和源极和漏极区之间的沟道区的连续线性纳米结构形成。源极（20）和漏极（26）区域由纳米线形成，沟道区域（24）呈纳米管形式。绝缘栅极（32）设置成邻近沟道区（24），用于控制源极和漏极区之间的沟道区。

9. 发明授权

US09231201B2 Electric device with a layer of conductive material contacted by nanowires 有权
标题翻译：具有与纳米线接触的导电材料层的电气装置
公开(公告)号：US09231201B2
公开(公告)日：2016-01-05
申请号：US11631212
申请日：2005-06-28
申请人： Robertus Theodorus Fransiscus Van Schaijk , Prabhat Agarwal , Erik Petrus Antonius Maria Bakkers , Martijn Henri Richard Lankhorst , Michiel Jos Van Duuren , Abraham Rudolf Balkenende , Louis Felix Feiner , Pierre Hermanus Woerlee
发明人： Robertus Theodorus Fransiscus Van Schaijk , Prabhat Agarwal , Erik Petrus Antonius Maria Bakkers , Martijn Henri Richard Lankhorst , Michiel Jos Van Duuren , Abraham Rudolf Balkenende , Louis Felix Feiner , Pierre Hermanus Woerlee
IPC分类号： H01L47/00 , H01L45/00 , B82Y10/00 , G11C13/02 , H01L21/285 , H01L21/768 , H01L27/24 , G11C13/00
CPC分类号： H01L45/1273 , B82Y10/00 , G11C13/0004 , G11C13/025 , G11C2213/81 , H01L21/28525 , H01L21/76879 , H01L27/2409 , H01L27/2436 , H01L27/2472 , H01L27/2481 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/148 , H01L45/16
摘要： The electric device (100) according to the invention comprises a layer (107) of a memory material which has an electrical resistivity switchable between a first value and a second value. The memory material may be a phase change material. The electric device (100) further comprises a set of nanowires (NW) electrically connecting a first terminal (172) of the electric device and the layer (107) of memory material thereby enabling conduction of an electric current from the first terminal via the nanowires (NW) and the layer (107) of memory material to a second terminal (272) of the electric device. Each nanowire (NW) electrically contacts the layer (107) of memory material in a respective contact area. All contact areas are substantially identical. The method according to the invention is suited to manufacture the electric device (100) according to the invention.
摘要翻译：根据本发明的电子设备（100）包括存储材料的层（107），其具有可在第一值和第二值之间切换的电阻率。记忆材料可以是相变材料。电气设备（100）还包括电连接电子设备的第一端子（172）和存储器材料层（107）的一组纳米线（NW），从而能够经由纳米线传导来自第一端子的电流（NW）和存储器材料层（107）连接到电气设备的第二端子（272）。每个纳米线（NW）在相应的接触区域中电接触存储器材料的层（107）。所有接触区域基本相同。根据本发明的方法适用于制造根据本发明的电子设备（100）。

10. 发明授权

US07759650B2 Implementation of avalanche photo diodes in (Bi)CMOS processes 有权
标题翻译：（Bi）CMOS工艺中雪崩光电二极管的实现
公开(公告)号：US07759650B2
公开(公告)日：2010-07-20
申请号：US12298206
申请日：2007-04-10
申请人： Anco Heringa , Thomas Frach , Prabhat Agarwal
发明人： Anco Heringa , Thomas Frach , Prabhat Agarwal
IPC分类号： G01T1/24
CPC分类号： H01L31/115 , H01L27/1446 , H01L31/107 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： A radiation detector (46) includes a semiconductor layer(s) (12) formed on a substrate (14) and a scintillator (30) formed on the semiconductor layer(s) (12). The semiconductor layer(s) (12) includes an n-doped region (16) disposed adjacent to the substrate (14), and a p-doped region (18) disposed adjacent to the n-doped region (16). A trench (20) is formed within the semiconductor layer(s) (12) and around the p-doped region (18) and is filled with a material (22) that reduces pn junction curvature at the edges of the pn junction, which reduces breakdown at the edges. The scintillator (30) is disposed over and optically coupled to the p-doped regions (18). The radiation detector (46) further includes at least one conductive electrode (24) that electrically contacts the n-doped region.
摘要翻译：辐射检测器（46）包括形成在衬底（14）上的半导体层（12）和形成在半导体层（12）上的闪烁体（30）。半导体层（12）包括邻近衬底（14）设置的n掺杂区域（16）和邻近于n掺杂区域（16）设置的p掺杂区域（18）。沟槽（20）形成在半导体层（12）内并且围绕p掺杂区域（18）并且填充有减小pn结边缘处的pn结曲率的材料（22），其中减少边缘的破坏。闪烁体（30）设置在p掺杂区域（18）上并且光耦合到p掺杂区域（18）。辐射检测器（46）还包括与n掺杂区域电接触的至少一个导电电极（24）。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式