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    • 11. 发明授权
    • Cache memory store buffer
    • 缓存存储器缓冲区
    • US06434665B1
    • 2002-08-13
    • US09410678
    • 1999-10-01
    • David ShepherdRajesh Chopra
    • David ShepherdRajesh Chopra
    • G06F1100
    • G06F12/0855
    • Methods and an apparatus for storing information in a processing device with flexible security are disclosed. In one embodiment, an apparatus processes back-to-back write and read operations without stalling the processor. A cache memory subsystem buffers write operations between a central processing unit (CPU) and the cache memory subsystem. Included in the cache memory subsystem are a tag memory, a data memory and a store buffer. The store buffer is coupled to both the data memory and the tag memory. Additionally, the store buffer stores a write operation.
    • 公开了一种在具有灵活安全性的处理设备中存储信息的方法和装置。 在一个实施例中,设备在不停止处理器的情况下处理背靠背写入和读取操作。 缓存存储器子系统缓冲中央处理单元(CPU)和高速缓冲存储器子系统之间的写入操作。 高速缓冲存储器子系统中包括标签存储器,数据存储器和存储缓冲器。 存储缓冲器耦合到数据存储器和标签存储器。 另外,存储缓冲器存储写入操作。
    • 12. 发明授权
    • Feeder for centrifugal apparatus
    • 离心设备进料器
    • US4534754A
    • 1985-08-13
    • US615273
    • 1984-05-30
    • David Shepherd
    • David Shepherd
    • B03B5/00B04B5/00B04B11/02B01D45/12B04B11/00
    • B03B5/00B04B11/02B04B5/00B04B2005/045
    • An apparatus and method for providing an accurately regulated flow of liquid medium to a device mounted in or on a rotor of a centrifuge, comprises a scoop on the rotor having a mouth opening forwards in the direction of rotation, with a duct connecting the mouth to the device; the liquid medium being projected as a jet into the path of the rotating scoop so that the mouth chops out a mid-portion of the jet during each revolution, and feeds it to the device. Rotation rates are high, typically 50,000 rpm for devices like liquid flow density balances for mass detection, but may be less and/or variable with SFFF devices.
    • 一种用于向安装在离心机的转子中或其上的设备提供精确调节的液体介质流的装置和方法,包括转子上的勺子,其具有在旋转方向上向前开口的口, 装置; 液体介质以喷射的方式投射到旋转勺的路径中,使得在每次旋转期间嘴部剔除喷射的中间部分,并将其馈送到装置。 旋转速率高,对于质量检测的液体流量密度平衡等设备,通常为50,000 rpm,但SFFF装置可能较少和/或变化。
    • 13. 发明授权
    • Chromatography columns
    • 色谱柱
    • US4497711A
    • 1985-02-05
    • US524073
    • 1983-08-17
    • David Shepherd
    • David Shepherd
    • B01D15/08G01N30/56
    • G01N30/56G01N2030/565
    • A method for packing a chromatography column having an inlet port at one end and an outlet port at the other, comprises feeding a slurry or smoke of particulate bed material in a carrier fluid and applying a predetermined pressure to the bed material while allowing the carrier fluid to escape, wherein both the inlet and outlet ports are protected by porous bed-retaining means positioned apart to provide a space for the bed between them, at least a final portion of the slurry or smoke being fed through a filler tube into the space for the bed until the space is full and the bed extends back into the filler tube, predetermined pressure to the bed being applied via the slurry or smoke in the filler tube, and the filler tube then sealed being against relaxation of the bed pressure.
    • 一种用于填充具有一端的入口和另一端的出口的色谱柱的方法包括将载体流体中的颗粒床材料的浆料或烟雾供给到床材料中,同时允许载体流体 其中入口端口和出口端口都被多孔床保持装置保护,所述多孔床保持装置被分开设置以为它们之间的床提供空间,浆料或烟的至少最后部分通过填充管进入到空间中 床直到空间充满并且床延伸回到填充管中,通过填料管中的浆料或烟雾施加预定的压力,并且填充管然后被密封以防止床压力的松弛。
    • 16. 发明申请
    • COMPLEXITY MANAGEMENT IN A MULTI-USER COMMUNICATIONS SYSTEM
    • 多用户通信系统中的复杂性管理
    • US20110164517A1
    • 2011-07-07
    • US12989938
    • 2009-04-28
    • David ShepherdMark ReedZhennig Shi
    • David ShepherdMark ReedZhennig Shi
    • H04L12/26
    • H04L1/0048H04B1/707H04B2201/70707H04L1/005H04L25/03331H04W52/346H04W72/1205
    • The invention concerns complexity management of a receiver in a multi-access/user communication system where interference exists. For example, but not limited to, multi-user detection at the receiver in the uplink of a code division multiple access DS/CDMA system. The invention provides a method for power management and decoding schedule optimisation by deriving (40) an extrinsic information transfer (EXIT) function for an interference canceller and a plurality of decoders. Then, determining (42) a power level for each of the plurality of users based on the derived EXIT functions; and then deriving (44) a decoding schedule for the plurality of decoders based on the derived EXIT functions and determined power levels. It is an advantage of the invention that optimization is broken into two parts. There is no trade-off between computational complexity (number of iterations) and the improvement in bit error rate performance at a given signal-to-noise ratio. Using the invention, large gains in receiver sensitivity (i.e. in power efficiency and/or spectrum efficiency therefore reducing interference from the terminals) and computational complexity can be achieved simultaneously.
    • 本发明涉及存在干扰的多址/用户通信系统中的接收机的复杂度管理。 例如但不限于在码分多址DS / CDMA系统的上行链路中的接收机处的多用户检测。 本发明提供一种通过导出(40)干扰消除器和多个解码器的外在信息传输(EXIT)功能来对功率管理和解码进度优化的方法。 然后,基于导出的EXIT功能确定(42)多个用户中的每一个的功率电平; 然后基于导出的EXIT函数和确定的功率电平导出(44)多个解码器的解码调度。 本发明的优点是将优化分为两部分。 在给定的信噪比下,计算复杂度(迭代次数)和误码率性能的改善之间不存在折衷。 使用本发明,可以同时实现接收机灵敏度(即,功率效率和/或频谱效率,从而减少来自终端的干扰)的大增益和计算复杂度。
    • 18. 发明授权
    • Microprocessor having improved memory management unit and cache memory
    • US06598128B1
    • 2003-07-22
    • US09410567
    • 1999-10-01
    • Shinich YoshiokaDavid ShepherdRajesh Chopra
    • Shinich YoshiokaDavid ShepherdRajesh Chopra
    • G06F1200
    • G06F12/1063G06F12/0835
    • Methods of maintaining cache coherency of a virtual cache memory system in a data processing system are disclosed. The entries of the virtual cache memory include physical address information and logical address information. A memory access operation may be initiated on one or more predetermined memory locations based on physical address information. A determination may be made if the memory access operation may involve cache coherent memory. If the memory access operation may involve cache coherent memory, then a cache coherency command may be issued that contains physical address information of the memory access operation. Based on the cache coherency command and the physical address information, a determination may be made if there is a match between the physical address information of the memory access operation and the physical address information stored in the virtual cache. If there is a match, then a determination may be made whether data associated with the particular entry of the virtual cache memory is dirty. If the data associated with the particular entry of the virtual cache memory is dirty, then a write back operation may be initiated, and data in the particular entry of the virtual cache memory may be written to memory. A command may then be issued that indicates that the virtual cache memory and the memory locations of the memory access operation are cohered, and the memory access operation may be completed. A determination also may be made whether the memory access operation is a write operation. If the memory access operation is a write operation, then the particular entry of the virtual cache memory may be invalidated. The virtual cache memory may be included in a single chip microprocessor, and a device external to the single chip microprocessor may initiate the memory access operation. A circuit that bridges between the external device and an internal bus may receive a command from the external device to initiate the memory access operation.