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1. 发明授权

US08069385B1 Programmable built-in self-test architecture 失效
标题翻译：可编程内置自检架构
公开(公告)号：US08069385B1
公开(公告)日：2011-11-29
申请号：US12501995
申请日：2009-07-13
申请人： Rajesh Chopra
发明人： Rajesh Chopra
IPC分类号： G11C29/44 , G11C29/54
CPC分类号： G11C29/16
摘要： A PBIST architecture is described. A data path circuit is configured for bit-to-associated bit comparisons of expected result data read from a tile with the expected result data read from result memory. The data path circuit is configured to write a first type of failure indication to first failure memory responsive to a data 0 being read from the result memory and a data 1 being read from the tile for a bit-to-associated bit comparison failure. The data path circuit is further configured to write a second type of failure indication to second failure memory responsive to a data 1 being read from the result memory and a data 0 being read from the tile for the bit-to-associated bit comparison.
摘要翻译：描述了PBIST架构。数据路径电路被配置用于从瓦片读取的预期结果数据与从结果存储器读取的预期结果数据进行比特到比特比较。数据路径电路被配置为响应于从结果存储器读取的数据0以及从瓦片读取的数据1用于比特到关联比特比较失败，向第一故障存储器写入第一类型的故障指示。数据路径电路还被配置为响应于从结果存储器读取的数据1和从片中读取用于比特到关联比特比较的数据0，将第二类型的故障指示写入第二故障存储器。

2. 发明申请

US20110257167A1 IDENTIFICATION OF LKB1 MUTATION AS A PREDICTIVE BIOMARKER FOR SENSITIVITY TO TOR KINASE INHIBITORS 有权
标题翻译：鉴定LKB1突变作为预测生物标志物，用于感应激酶激酶抑制剂
公开(公告)号：US20110257167A1
公开(公告)日：2011-10-20
申请号：US13020031
申请日：2011-02-03
申请人： Rajesh Chopra , Yuhong Ning , Sabita Sankar , Shuichan Xu , Weiming Xu
发明人： Rajesh Chopra , Yuhong Ning , Sabita Sankar , Shuichan Xu , Weiming Xu
IPC分类号： A61K31/5383 , C12Q1/68 , A61K31/437 , A61K31/4985 , A61K31/4709 , A61J1/00 , A61K31/519 , A61K31/5377 , A61K31/498 , A61K31/4738 , A61P35/00 , A61K31/53 , A61K31/52
CPC分类号： A61K31/519 , A61K31/155 , A61K31/4985 , A61K31/7004 , A61K2300/00
摘要： Provided herein are methods for treating and/or preventing a cancer or a tumor syndrome in a patient, comprising administering an effective amount of a TOR kinase inhibitor to a patient having cancer or a tumor syndrome, characterized by a LKB1 and/or AMPK gene or protein loss or mutation.
摘要翻译：本文提供了用于治疗和/或预防患者中的癌症或肿瘤综合征的方法，包括向具有癌症或肿瘤综合征的患者施用有效量的TOR激酶抑制剂，其特征在于LKB1和/或AMPK基因或蛋白质丢失或突变。

3. 发明申请

US20110209002A1 Programmable Test Engine (PCDTE) For Emerging Memory Technologies 有权
标题翻译：可编程测试引擎（PCDTE）用于新兴内存技术
公开(公告)号：US20110209002A1
公开(公告)日：2011-08-25
申请号：US13030358
申请日：2011-02-18
申请人： Rajesh Chopra
发明人： Rajesh Chopra
IPC分类号： G06F11/267
CPC分类号： G06F11/263 , G06F11/27 , G11C29/56 , G11C29/56004
摘要： A programmable characterization-debug-test engine (PCDTE) on an integrated circuit chip. The PCDTE includes an instruction memory that receives and stores instructions provided on a chip interface, and a configuration memory that receives and stores configuration values provided on the chip interface. The PCDTE also includes a controller that configures a plurality of address counters and data registers in response to the configuration values. The controller also executes the instructions, wherein read/write addresses and write data are retrieved from the counters in response to the instructions. The retrieved read/write addresses and write data are used to access a memory under test. Multiple ports of the memory under test may be simultaneously accessed. Multiple instructions may be linked. The instructions may specify special counting functions within the counters and/or specify integrated (linked) counters. The PCDTE may transmit information off of the chip to exercise transmit/receive circuitry of the chip.
摘要翻译：集成电路芯片上的可编程特征调试测试引擎（PCDTE）。 PCDTE包括接收并存储提供在芯片接口上的指令的指令存储器，以及接收并存储在芯片接口上提供的配置值的配置存储器。 PCDTE还包括响应于配置值配置多个地址计数器和数据寄存器的控制器。控制器还执行指令，其中响应于指令从计数器检索读/写地址和写数据。检索到的读/写地址和写数据用于访问被测内存。可以同时访问被测存储器的多个端口。可以链接多个指令。指令可以指定计数器内的特殊计数功能和/或指定集成（链接）计数器。 PCDTE可以从芯片传送信息来锻炼芯片的发射/接收电路。

4. 发明申请

US20100305988A1 Enhancing Quality of Contact Lists for Direct Marketing Campaigns 审中-公开
标题翻译：提高直接营销活动联系人名单的质量
公开(公告)号：US20100305988A1
公开(公告)日：2010-12-02
申请号：US12471941
申请日：2009-05-26
申请人： Nishant AGARWAL , Rajesh Chopra , Sharat Rapur
发明人： Nishant AGARWAL , Rajesh Chopra , Sharat Rapur
IPC分类号： G06Q10/00 , G06F17/30 , G06Q30/00
CPC分类号： G06Q10/06395 , G06Q30/02
摘要： A method, system, and computer program product are used for enhancing quality of contact lists for direct marketing campaigns. An embodiment of the method includes receiving a contact list that includes a plurality of customer profiles, and performing at least one of a counts verification check, a criteria outlier check, a data values check, and an output file check on the contact list. The method performs the aforementioned checks based at least partially on one or more quality check (QC) parameters. Further, the method includes generating a QC report that includes error statistics pertaining to at least one of the aforementioned checks. The method further generates an exceptions report based on the QC report and the QC parameters, and modifies the QC parameters based on the exceptions report.
摘要翻译：方法，系统和计算机程序产品用于提高直接营销活动的联系人列表的质量。该方法的实施例包括接收包括多个客户简档的联系人列表，并且在联系人列表上执行计数验证检查，标准异常检查，数据值检查和输出文件检查中的至少一个。该方法至少部分地基于一个或多个质量检查（QC）参数执行上述检查。此外，该方法包括生成包括与上述检查中的至少一个相关的错误统计的QC报告。该方法还基于QC报告和QC参数生成异常报告，并根据异常报告修改QC参数。

5. 发明申请

US20090228867A1 Methods for Configuring Software Package 有权
标题翻译：配置软件包的方法
公开(公告)号：US20090228867A1
公开(公告)日：2009-09-10
申请号：US12042529
申请日：2008-03-05
申请人： Tirthankar Bandyopadhyay , Kumar Bhaskaran , Rajesh Chopra , Christina Derra (Schmidt) , Shiwa S. Fu , Ying Huang , Stephen K. Kibby , Santhosh Kumaran , Igor A. Naumov , Thomas D. Rosinski , Gerhard Sigl
发明人： Tirthankar Bandyopadhyay , Kumar Bhaskaran , Rajesh Chopra , Christina Derra (Schmidt) , Shiwa S. Fu , Ying Huang , Stephen K. Kibby , Santhosh Kumaran , Igor A. Naumov , Thomas D. Rosinski , Gerhard Sigl
IPC分类号： G06F9/44
CPC分类号： G06F8/71
摘要： A method for configuring a software package for an enterprise includes gathering desired To-be configuration requirements for a software package through at least one questionnaire; gathering current As-is raw data for the enterprise; displaying the To-Be configuration requirements and As-is raw data; comparing the To-Be configuration requirements and As-is raw data; selecting final To-Be configuration requirements; and generating and executing configuration code for the software package to pre-configure the software package with the final To-Be configuration requirements.
摘要翻译：用于配置企业的软件包的方法包括通过至少一个问卷收集对软件包的期望的To-be配置要求; 收集当前企业的原始数据; 显示To-Be配置要求和原始数据; 比较To-Be配置要求和原始数据; 选择最终的To-Be配置要求; 以及生成并执行软件包的配置代码以预配置具有最终To-Be配置要求的软件包。

6. 发明授权

US06591340B2 Microprocessor having improved memory management unit and cache memory 失效
公开(公告)号：US06591340B2
公开(公告)日：2003-07-08
申请号：US10166503
申请日：2002-06-10
申请人： Rajesh Chopra , Shinichi Yoshioka , Mark Debbage , David Shepherd
发明人： Rajesh Chopra , Shinichi Yoshioka , Mark Debbage , David Shepherd
IPC分类号： G06F1200
CPC分类号： G06F9/383 , G06F9/30032 , G06F9/30047 , G06F9/30087 , G06F9/3802 , G06F12/0888 , G06F12/1063 , G06F12/126 , G06F12/145
摘要： Methods of widening the permission for a memory access in a data processing system having a virtual cache memory and a translation lookaside buffer are disclosed. A memory access operation is initiated on a predetermined memory location based on logical address information and permission information associated with the memory access operation. The virtual cache memory is accessed and a determination may be made if there is a match between logical address information of the memory access operation and logical address information stored in the entries of the virtual cache. In the event of a match, then a determination may be made based on the permission information of the memory access operation and the permission information of the particular entry of the virtual cache memory as to whether the memory access operation is permitted. If the memory access operation is not permitted by the permission information of the particular entry of the virtual cache memory, then the translation lookaside buffer may be accessed based on the logical address information of the particular entry of the virtual cache memory. If there is a match between the logical address information of the particular entry of the virtual cache memory and the logical address information of a particular entry of the translation lookaside buffer, then a determination may be made based on the permission information of the memory access operation and the permission information of the particular entry of the translation lookaside buffer as to whether the memory access operation is permitted by the permission information of the particular entry of the translation lookaside buffer. If the memory access operation is permitted by the permission information of the particular entry of the translation lookaside buffer, then the permission information of the particular entry of the virtual cache memory may be updated based on the permission information of the particular entry of the translation lookaside buffer and the memory access operation may be completed.

7. 发明授权

US06412043B1 Microprocessor having improved memory management unit and cache memory 失效
公开(公告)号：US06412043B1
公开(公告)日：2002-06-25
申请号：US09410506
申请日：1999-10-01
申请人： Rajesh Chopra , Shinichi Yoshioka , Mark Debbage , David Shepherd
发明人： Rajesh Chopra , Shinichi Yoshioka , Mark Debbage , David Shepherd
IPC分类号： G06F1200
CPC分类号： G06F9/383 , G06F9/30032 , G06F9/30047 , G06F9/30087 , G06F9/3802 , G06F12/0888 , G06F12/1063 , G06F12/126 , G06F12/145
摘要： Methods of widening the permission for a memory access in a data processing system having a virtual cache memory and a translation lookaside buffer are disclosed. A memory access operation is initiated on a predetermined memory location based on logical address information and permission information associated with the memory access operation. The virtual cache memory is accessed and a determination may be made if there is a match between logical address information of the memory access operation and logical address information stored in the entries of the virtual cache. In the event of a match, then a determination may be made based on the permission information of the memory access operation and the permission information of the particular entry of the virtual cache memory as to whether the memory access operation is permitted. If the memory access operation is not permitted by the permission information of the particular entry of the virtual cache memory, then the translation lookaside buffer may be accessed based on the logical address information of the particular entry of the virtual cache memory. If there is a match between the logical address information of the particular entry of the virtual cache memory and the logical address information of a particular entry of the translation lookaside buffer, then a determination may be made based on the permission information of the memory access operation and the permission information of the particular entry of the translation lookaside buffer as to whether the memory access operation is permitted by the permission information of the particular entry of the translation lookaside buffer. If the memory access operation is permitted by the permission information of the particular entry of the translation lookaside buffer, then the permission information of the particular entry of the virtual cache memory may be updated based on the permission information of the particular entry of the translation lookaside buffer and the memory access operation may be completed.

8. 发明申请

US20140082453A1 SUBSTITUTE REDUNDANT MEMORY 审中-公开
标题翻译：备用冗余内存
公开(公告)号：US20140082453A1
公开(公告)日：2014-03-20
申请号：US14031031
申请日：2013-09-18
申请人： Dipak K. Sikdar , Rajesh Chopra
发明人： Dipak K. Sikdar , Rajesh Chopra
IPC分类号： G06F11/10
CPC分类号： G06F11/108 , G06F11/106 , G06F11/2094 , G11C29/06 , G11C29/12 , G11C29/42 , G11C29/44 , G11C29/4401 , G11C29/50 , G11C29/808
摘要： An integrated circuit (IC) chip for transparent and in-service or production repair of single to multiple memory cell defects in a word during the datapath transit of the word between core memory to the interface of the IC via capturing an accurate bit from a word during a write access to a known defective memory address, and by substituting in a non-defective bit into the word during a read access from a known defective memory address. The IC includes: address matching circuit (CAM), a random access memory (RAM) of substitute memory cells containing accurate associated bit data and bit location in word of defect, and data selection circuitry (MUXs) coupled together.
摘要翻译：一种集成电路（IC）芯片，用于通过从一个字中捕获一个精确的位，在核心存储器到IC的接口之间的数据路径传输期间，一个字中的单个到多个存储单元缺陷的单个或多个存储单元缺陷的透明和在线或生产修复在对已知的有缺陷的存储器地址进行写入访问期间，并且在从已知的有缺陷的存储器地址进行的读取访问期间通过将非有缺陷的位替换成该字。 IC包括：地址匹配电路（CAM），包含精确关联位数据的替代存储单元的随机存取存储器（RAM）和缺陷字中的位位置，以及耦合在一起的数据选择电路（MUX）。

9. 发明申请

US20130173970A1 MEMORY DEVICE WITH BACKGROUND BUILT-IN SELF-TESTING AND BACKGROUND BUILT-IN SELF-REPAIR 有权
标题翻译：具有背景技术的存储器件内置自检和背景技术自我修复
公开(公告)号：US20130173970A1
公开(公告)日：2013-07-04
申请号：US13732783
申请日：2013-01-02
申请人： Bendik Kleveland , Dipak K. Sikdar , Rajesh Chopra , Jay Patel
发明人： Bendik Kleveland , Dipak K. Sikdar , Rajesh Chopra , Jay Patel
IPC分类号： G11C29/44
CPC分类号： G06F11/2094 , G06F11/106 , G11C29/06 , G11C29/12 , G11C29/16 , G11C29/42 , G11C29/44 , G11C29/4401 , G11C29/50 , G11C29/808 , G11C2029/0409
摘要： A memory device with background built-in self-testing (BBIST) includes a plurality of memory blocks; a memory buffer to offload data from one of the plurality of memory blocks temporarily; and a memory block stress controller to control a stress test applied to the one of the memory blocks when the data is temporarily offloaded on the memory buffer. The stress test tests for errors in the one of the plurality of the memory blocks.
摘要翻译：具有背景内置自检（BBIST）的存储器件包括多个存储器块; 一个用于临时从多个存储块中的一个存储器块中的一个卸载数据的存储器缓冲器; 以及存储器块应力控制器，用于当数据被暂时地卸载到存储器缓冲器上时，控制施加到存储器块之一的压力测试。压力测试测试多个存储器块中的一个存储器块中的错误。

10. 发明授权

US08451035B2 Synthesizable DLL on system-on-chip 有权
标题翻译：片上系统上的合成DLL
公开(公告)号：US08451035B2
公开(公告)日：2013-05-28
申请号：US12969220
申请日：2010-12-15
申请人： Prateek Sikka , Rajesh Chopra , Manoj Yadav
发明人： Prateek Sikka , Rajesh Chopra , Manoj Yadav
IPC分类号： H03L7/06
CPC分类号： H03K5/135 , G06F17/5045
摘要： The present disclosure provides an emulator mapping process on a system-on-a-chip (SoC) for debugging. The implementation reduces manual intervention and makes the emulation mapping process very generic and technology independent and hence it reduces overall project cycle time. In the present disclosure, the SoCs containing analog delay locked loops are made suitable for emulation by configuring analog delay locked loop module in parallel with a synthesizable delay logic module. Further, selection logic is provided to select any one of the module at a time.
摘要翻译：本公开提供了用于调试的片上系统（SoC）上的仿真器映射过程。该实现减少了手动干预，并使仿真映射过程非常通用和独立于技术，从而减少了整个项目周期的时间。在本公开中，通过与可合成的延迟逻辑模块并联配置模拟延迟锁定环模块，包含模拟延迟锁定环路的SoC适于仿真。此外，提供选择逻辑以一次选择模块中的任何一个。

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