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11. 发明授权

US08026169B2 Cu annealing for improved data retention in flash memory devices 有权
标题翻译： Cu退火以改善闪存器件中的数据保留
公开(公告)号：US08026169B2
公开(公告)日：2011-09-27
申请号：US11593086
申请日：2006-11-06
申请人： Lu You , Alexander Nickel , Minh Q. Tran , Minh-Van Ngo , Hieu Pham , Erik Wilson , Hirokazu Tokuno , Amir Hossein Jafarpour , Inkuk Kang , Robert Huertas
发明人： Lu You , Alexander Nickel , Minh Q. Tran , Minh-Van Ngo , Hieu Pham , Erik Wilson , Hirokazu Tokuno , Amir Hossein Jafarpour , Inkuk Kang , Robert Huertas
IPC分类号： H01L21/4763
CPC分类号： H01L21/76883 , H01L27/11521
摘要： Data retention in flash memory devices, such as mirrorbit devices, is improved by reducing the generation and/or diffusion of hydrogen ions during back end processing, such as annealing inlaid Cu. Embodiments include annealing inlaid Cu in an N2 atmosphere containing low H2 or no H2, and at temperatures less than 200° C., e.g., 100° C. to 150° C.
摘要翻译：通过减少后端处理中的氢离子的产生和/或扩散（例如退火的Cu）来改善闪存器件（例如镜像位装置）中的数据保留。实施方案包括在含有低H 2或不含H 2的N 2气氛中以及在低于200℃，例如100℃至150℃的温度下退火镶嵌Cu。

12. 发明授权

US07884030B1 Gap-filling with uniform properties 有权
标题翻译：间隙填充均匀性
公开(公告)号：US07884030B1
公开(公告)日：2011-02-08
申请号：US11408086
申请日：2006-04-21
申请人： Alexander Nickel , Lu You , Hirokazu Tokuno , Minh Tran , Minh Van Ngo , Hieu Pham , Erik Wilson , Robert Huertas
发明人： Alexander Nickel , Lu You , Hirokazu Tokuno , Minh Tran , Minh Van Ngo , Hieu Pham , Erik Wilson , Robert Huertas
IPC分类号： H01L21/31 , H01L21/469 , H01L23/58
CPC分类号： H01L21/022 , H01L21/02348 , H01L21/76224 , H01L21/76828 , H01L21/76829 , H01L21/76837
摘要： During semiconductor fabrication homogeneous gap-filling is achieved by depositing a thin dielectric layer into the gap, post deposition curing, and then repeating deposition and post deposition curing until gap-filling is completed. Embodiments include depositing a layer of low deposition temperature gap-fill dielectric into a high aspect ratio opening, such as a shallow trench or a gap between closely spaced apart gate electrode structures, as at a thickness of about 10 Å to about 500 Å, curing after deposition, as by UV radiation or by heating at a temperature of about 400° C. to about 1000° C., depositing another layer of low deposition temperature gap-filled dielectric, and curing after deposition. Embodiments include separately depositing and separately curing multiple layers.
摘要翻译：在半导体制造期间，通过将薄介电层沉积到间隙中，后沉积固化，然后重复沉积和后沉积固化直到间隙填充完成来实现均匀间隙填充。实施例包括将低沉积温度间隙填充电介质的层沉积到高纵横比开口中，例如浅沟槽或紧密间隔开的栅电极结构之间的间隙，其厚度约为至约500，固化在沉积之后，如通过UV辐射或在约400℃至约1000℃的温度下加热，沉积另一层低沉积温度充满间隙的电介质，并在沉积后固化。实施例包括分别沉积和分别固化多层。

13. 发明授权

US07307027B1 Void free interlayer dielectric 有权
标题翻译：无空隙层间电介质
公开(公告)号：US07307027B1
公开(公告)日：2007-12-11
申请号：US11201378
申请日：2005-08-11
申请人： Minh Van Ngo , Alexander Nickel , Hieu Pham , Jean Yang , Hirokazu Tokuno , Weidong Qian
发明人： Minh Van Ngo , Alexander Nickel , Hieu Pham , Jean Yang , Hirokazu Tokuno , Weidong Qian
IPC分类号： H01L21/31
CPC分类号： H01L21/31625 , H01L21/02129 , H01L21/02274 , H01L21/02304 , H01L21/76837 , H01L27/115 , H01L27/11521 , H01L27/11568
摘要： A method of forming a dielectric between memory cells in a device includes forming multiple memory cells, where a gap is formed between each of the multiple memory cells. The method further includes performing a high density plasma deposition (HDP) process to fill at least a portion of the gap between each of the multiple memory cells with a dielectric material.
摘要翻译：在器件中的存储器单元之间形成电介质的方法包括形成多个存储器单元，其中在多个存储器单元中的每一个之间形成间隙。该方法还包括执行高密度等离子体沉积（HDP）工艺以用电介质材料填充每个多个存储器单元之间的间隙的至少一部分。

14. 发明申请

US20060214218A1 Semiconductor device and method of fabricating the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060214218A1
公开(公告)日：2006-09-28
申请号：US11258823
申请日：2005-10-25
申请人： Kiyokazu Shishido , Masahiko Higashi , Minh Ngo , Angela Hui , Wenmei Li , Ning Cheng , Mark Ramsbey , Hirokazu Tokuno , Pei-Yuan Gao , Takayuki Enda
发明人： Kiyokazu Shishido , Masahiko Higashi , Minh Ngo , Angela Hui , Wenmei Li , Ning Cheng , Mark Ramsbey , Hirokazu Tokuno , Pei-Yuan Gao , Takayuki Enda
IPC分类号： H01L29/792
CPC分类号： H01L21/76801 , H01L21/02129 , H01L21/022 , H01L21/3144 , H01L21/31625 , H01L21/76829 , H01L27/11568 , H01L29/40117 , H01L29/513
摘要： A semiconductor device includes a semiconductor substrate, an ONO film that is provided on the semiconductor substrate and has a contact hole, and an interlayer insulating film that is provided directly on the ONO film and contains phosphorus. The interlayer insulating film contains 4.5 wt % of phosphorus or more in an interface portion that interfaces with the ONO film. The interlayer insulating film comprises a first portion that contacts the ONO film, and a second portion provided on the first portion. The first portion has a phosphorus concentration more than that of the second portion.
摘要翻译：半导体器件包括半导体衬底，设置在半导体衬底上并具有接触孔的ONO膜，以及直接设置在ONO膜上并含有磷的层间绝缘膜。在与ONO膜接合的界面部分中，层间绝缘膜含有4.5重量％以上的磷。层间绝缘膜包括接触ONO膜的第一部分和设置在第一部分上的第二部分。第一部分的磷浓度大于第二部分的磷浓度。

15. 发明申请

US20120045888A1 MULTILAYER LOW REFLECTIVITY HARD MASK AND PROCESS THEREFOR 有权
标题翻译：多层低反射率硬掩模及其过程
公开(公告)号：US20120045888A1
公开(公告)日：2012-02-23
申请号：US13283076
申请日：2011-10-27
申请人： Kouros Ghandehari , Anna M. Minvielle , Marina V. Plat , Hirokazu Tokuno
发明人： Kouros Ghandehari , Anna M. Minvielle , Marina V. Plat , Hirokazu Tokuno
IPC分类号： H01L21/28
CPC分类号： H01L21/32139 , H01L21/0276
摘要： A method utilizing a multilayer anti-reflective coating layer structure can achieve low reflectivity at high numerical apertures. The multilayer anti-reflective coating structure can be utilized as a hard mask forming various integrated circuit structures. A multilayer anti-reflective coating structure can be utilized to form gate stacks comprised of polysilicon and a dielectric layer. A photoresist is applied above the multilayer anti-reflective coating which can include silicon oxynitride (SiON) and silicon rich nitride (SiRN).
摘要翻译：利用多层抗反射涂层结构的方法可以在高数值孔径下实现低反射率。多层抗反射涂层结构可以用作形成各种集成电路结构的硬掩模。可以使用多层抗反射涂层结构来形成由多晶硅和电介质层组成的栅叠层。在多层抗反射涂层之上施加光致抗蚀剂，其可以包括氮氧化硅（SiON）和富含硅的氮化物（SiRN）。

16. 发明授权

US08309457B2 Multilayer low reflectivity hard mask and process therefor 有权
标题翻译：多层低反射率硬掩模及其工艺
公开(公告)号：US08309457B2
公开(公告)日：2012-11-13
申请号：US13283076
申请日：2011-10-27
申请人： Kouros Ghandehari , Anna M. Minvielle , Marina V. Plat , Hirokazu Tokuno
发明人： Kouros Ghandehari , Anna M. Minvielle , Marina V. Plat , Hirokazu Tokuno
IPC分类号： H01L21/4763
CPC分类号： H01L21/32139 , H01L21/0276
摘要： A method utilizing a multilayer anti-reflective coating layer structure can achieve low reflectivity at high numerical apertures. The multilayer anti-reflective coating structure can be utilized as a hard mask forming various integrated circuit structures. A multilayer anti-reflective coating structure can be utilized to form gate stacks comprised of polysilicon and a dielectric layer. A photoresist is applied above the multilayer anti-reflective coating which can include silicon oxynitride (SiON) and silicon rich nitride (SiRN).
摘要翻译：利用多层抗反射涂层结构的方法可以在高数值孔径下实现低反射率。多层抗反射涂层结构可以用作形成各种集成电路结构的硬掩模。可以使用多层抗反射涂层结构来形成由多晶硅和电介质层组成的栅叠层。在多层抗反射涂层之上施加光致抗蚀剂，其可以包括氮氧化硅（SiON）和富含硅的氮化物（SiRN）。

17. 发明授权

US06894342B1 Structure and method for preventing UV radiation damage in a memory cell and improving contact CD control 有权
标题翻译：用于防止存储单元中的紫外线辐射损伤的结构和方法，并改善接触式CD控制
公开(公告)号：US06894342B1
公开(公告)日：2005-05-17
申请号：US10460278
申请日：2003-06-12
申请人： Angela Hui , Minh V. Ngo , Ning Cheng , Jaeyong Park , Jean Y. Yang , Hirokazu Tokuno , Kouros Ghandehari , Hidehiko Shiraiwa
发明人： Angela Hui , Minh V. Ngo , Ning Cheng , Jaeyong Park , Jean Y. Yang , Hirokazu Tokuno , Kouros Ghandehari , Hidehiko Shiraiwa
IPC分类号： H01L21/336 , H01L21/8246 , H01L23/532 , H01L23/552 , H01L29/788
CPC分类号： H01L27/11568 , H01L23/53295 , H01L23/552 , H01L27/112 , H01L29/66833 , H01L2924/0002 , H01L2924/00
摘要： According to one exemplary embodiment, a structure comprises a substrate. The structure further comprises at least one memory cell situated on the substrate. The at least one memory cell may be, for example, a SONOS flash memory cell. The structure further comprises an interlayer dielectric layer situated over at least one memory cell and over the substrate. The structure further comprises a first antireflective coating layer situated over the interlayer dielectric layer. According to this exemplary embodiment, the structure further comprises a second antireflective coating layer situated directly over the first anti reflective coating layer. Either the first antireflective coating layer or second antireflective coating layer must be a silicon-rich layer. The first antireflective coating layer and the second antireflective coating may form a UV radiation blocking layer having a UV transparency less than approximately 1.0 percent, for example.
摘要翻译：根据一个示例性实施例，一种结构包括基底。该结构还包括位于基板上的至少一个存储单元。至少一个存储单元可以是例如SONOS闪存单元。该结构还包括位于至少一个存储器单元上方和衬底上方的层间电介质层。该结构还包括位于层间电介质层上的第一抗反射涂层。根据该示例性实施例，该结构还包括直接位于第一抗反射涂层上的第二抗反射涂层。第一抗反射涂层或第二抗反射涂层必须是富硅层。第一抗反射涂层和第二抗反射涂层可以形成例如UV透明度小于约1.0％的UV辐射阻挡层。

18. 发明授权

US07538026B1 Multilayer low reflectivity hard mask and process therefor 有权
标题翻译：多层低反射率硬掩模及其工艺
公开(公告)号：US07538026B1
公开(公告)日：2009-05-26
申请号：US11098262
申请日：2005-04-04
申请人： Kouros Ghandehari , Anna M. Minvielle , Marina V. Plat , Hirokazu Tokuno
发明人： Kouros Ghandehari , Anna M. Minvielle , Marina V. Plat , Hirokazu Tokuno
IPC分类号： H01L21/4763
CPC分类号： H01L21/32139 , H01L21/0276
摘要： A method utilizing a multilayer anti-reflective coating layer structure can achieve low reflectivity at high numerical apertures. The multilayer anti-reflective coating structure can be utilized as a hard mask forming various integrated circuit structures. A multilayer anti-reflective coating structure can be utilized to form gate stacks comprised of polysilicon and a dielectric layer. A photoresist is applied above the multilayer anti-reflective coating which can include silicon oxynitride (SiON) and silicon rich nitride (SiRN).
摘要翻译：利用多层抗反射涂层结构的方法可以在高数值孔径下实现低反射率。多层抗反射涂层结构可以用作形成各种集成电路结构的硬掩模。可以使用多层抗反射涂层结构来形成由多晶硅和电介质层组成的栅叠层。在多层抗反射涂层之上施加光致抗蚀剂，其可以包括氮氧化硅（SiON）和富含硅的氮化物（SiRN）。

19. 发明授权

US07220643B1 System and method for gate formation in a semiconductor device 有权
标题翻译：用于半导体器件中栅极形成的系统和方法
公开(公告)号：US07220643B1
公开(公告)日：2007-05-22
申请号：US11147207
申请日：2005-06-08
申请人： Hajime Wada , Jaeyong Park , Hirokazu Tokuno , Rinji Sugino
发明人： Hajime Wada , Jaeyong Park , Hirokazu Tokuno , Rinji Sugino
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L21/7624
摘要： A method for forming a memory device is provided. A memory cell stack is formed over a substrate. The memory cell stack includes a first layer formed over the substrate and a second layer formed over the first layer. A dielectric layer is formed over the first and second layers and the substrate. The dielectric layer is etched to expose at least an upper surface of the memory cell stack. The second layer is etched to recess the second layer with respect to an upper surface of the dielectric layer. A silicide region is formed on the second layer in the memory cell stack, where the silicide region in each memory cell stack is bounded by the dielectric layer extending above the upper surface of the memory cell stack.
摘要翻译：提供了一种用于形成存储器件的方法。在衬底上形成存储单元堆叠。存储单元堆叠包括形成在衬底上的第一层和形成在第一层上的第二层。介电层形成在第一层和第二层和衬底之上。蚀刻电介质层以暴露存储单元堆叠的至少上表面。蚀刻第二层以使第二层相对于电介质层的上表面凹陷。在存储单元堆叠中的第二层上形成硅化物区域，其中每个存储单元堆叠中的硅化物区域由在存储单元堆叠的上表面上方延伸的介电层界定。

20. 发明申请

US20070093070A1 Triple layer anti-reflective hard mask 有权
标题翻译：三层防反光硬面罩
公开(公告)号：US20070093070A1
公开(公告)日：2007-04-26
申请号：US11256184
申请日：2005-10-24
申请人： Kouros Ghandehari , Hirokazu Tokuno , David Matsumoto , Christopher Raeder , Christopher Foster , Weidong Qian , Minh Ngo
发明人： Kouros Ghandehari , Hirokazu Tokuno , David Matsumoto , Christopher Raeder , Christopher Foster , Weidong Qian , Minh Ngo
IPC分类号： H01L21/302 , H01L21/31
CPC分类号： G03F7/091 , H01L21/0276
摘要： A method includes forming a layer of silicon oxynitride (SiON), silicon rich nitride (SiRN) or silicon nitride (Si3N4) over a layer of semiconducting material. The method further includes forming a first layer of anti-reflective material over the layer of SiON, SiRN or Si3N4 and forming a second layer of anti-reflective material over the first layer. The method also includes using the first layer, second layer and layer of SiON, SiRN or Si3N4 as a mask when etching a pattern in the layer of semiconducting material.
摘要翻译：一种方法包括在半导体材料层上形成氮氧化硅（SiON），富硅氮化物（SiRN）或氮化硅（Si 3 N 4 N 4）层。该方法还包括在SiON，SiRN或Si 3 N 4 S层上形成第一层抗反射材料，并形成第二层抗反射材料第一层。该方法还包括当蚀刻半导体材料层中的图案时，使用SiON，SiRN或Si 3 N 4 N 4的第一层，第二层和第Si层作为掩模。

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